Data Sheet

0.1 µF
VM
AOUT1
AOUT2
BOUT1
BOUT2
GND
VCC
MODE
AIN1/APHASE
AIN2/AENBL
BIN1/BPHASE
10 µF
BIN2/BENBL
14
DRV8835
SLVSB18G –MARCH 2012 –REVISED MAY 2016 www.ti.com
Product Folder Links: DRV8835
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10 Layout
10.1 Layout Guidelines
The VCC pin should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value
of 0.1 μF rated for VCC. This capacitor should be placed as close to the VCC pin as possible with a thick trace.
The VM pin should be bypassed to GND using low-ESR ceramic bypass capacitors with a recommended value
of 0.1 μF rated for VM. This capacitor should be placed as close to the VM pin as possible with a thick trace. The
VM pin must bypass to ground using an appropriate bulk capacitor. This component can be an electrolytic and
should be located close to the DRV8835.
10.2 Layout Example
Figure 8. Layout Recommendation
10.3 Thermal Considerations
The DRV8835 has thermal shutdown (TSD) as described above. If the die temperature exceeds approximately
150°C, the device disables until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation,
insufficient heatsinking, or excessively high ambient temperature.
10.3.1 Power Dissipation
Power dissipation in the DRV8835 is dominated by the power dissipated in the output FET resistance, or R
DS(on)
.
Average power dissipation when running both H-bridges can be roughly estimated by Equation 1:
P
TOT
= 2 × R
DS(ON)
× (I
OUT(RMS)
)
2
where
• P
TOT
is the total power dissipation, R
DS(ON)
is the resistance of the HS plus LS FETs, and I
OUT(RMS)
is the RMS
output current being applied to each winding. I
OUT(RMS)
is equal to the approximately 0.7× the full-scale output
current setting. The factor of 2 comes from the fact that there are two H-bridges. (1)
The maximum amount of power dissipated in the device is dependent on ambient temperature and heatsinking.