Data Sheet

AMIS−30543
http://onsemi.com
9
DIR
NXT
VALID
t
NXT_HI
t
NXT_LO
t
DIR_SET
t
DIR_HOLD
0.5 V
CC
Figure 5. NXT−Input Timing Diagram
Table 6. SPI TIMING PARAMETERS
Symbol Parameter Min Typ Max Unit
t
CLK
SPI Clock Period 1
ms
t
CLK_HIGH
SPI Clock High Time 100 ns
t
CLK_LOW
SPI Clock Low Time 100 ns
t
SET_DI
DI Set Up Time, Valid Data Before Rising Edge of CLK 50 ns
t
HOLD_DI
DI Hold Time, Hold Data After Rising Edge of CLK 50 ns
t
CSB_HIGH
CS High Time 2.5
ms
t
SET_CSB
CS Set Up Time, CS Low Before Rising Edge of CLK 100 ns
t
SET_CLK
CLK Set Up Time, CLK Low Before Rising Edge of CS 100 ns
DI
CLK
t
SET _CSB
CS
t
CLK
t
SET_CLK
0.2 V
CC
0.8V
CC
0.2 V
CC
0,2 V
CC
0.8 V
CC
0. 2 V
CC
t
CLK_HI t
CLK _LO
t
SET_DI t
HOLD_DI
VALID
Figure 6. SPI Timing