Data Sheet

AMIS−30543
http://onsemi.com
34
DI
CS
DO
WRITE DATA
to ADDR2
OLD DATA
or NOT VALID
COMMAND
DATA DATA
DATA from previous
command or NOT VALID
after POR or RESET
COMMANDDATA
DATADATA
OLD DATA
from ADDR2
NEW DATA
for ADDR2
OLD DATA
from ADDR2
READ DATA
from ADDR2
COMMAND
or DUMMY
NEW DATA
from ADDR2
Figure 23. A WRITE Operation Where DATA from the Master is Written in SPI Register with Address 2 Followed by
a READ Back Operation to Confirm a Correct WRITE Operation
Registers are updated with
the internal status at the
rising edge of CS
The NEW DATA is written into the
corresponding internal register at
the rising edge of CS
NOTE: The internal data−out shift buffer of AMIS−30543 is updated with the content of the selected SPI register only at the last (every
eight) falling edge of the CLK signal (see SPI Transfer Format and Pin Signals). As a result, new data for transmission cannot be
written to the shift buffer at the beginning of the transfer packet and the first byte shifted out might represent old data.
Table 11. SPI CONTROL REGISTERS (All SPI control registers have Read/Write Access and default to “0” after power−on or hard
reset)
Address
Content
Structure
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
WR (00h) Data WDEN WDT[3:0] − − −
CR0 (01h) Data SM[2:0] CUR[4:0]
CR1 (02h) Data DIRCTRL NXTP − − PWMF PWMJ EMC[1:0]
CR2 (03h) Data MOTEN SLP SLAG SLAT − − − −
CR3 (09h) Data − − − − − ESM[2:0]
Where:
R/W Read and Write access
Reset: Status after power−On or hard reset