Data Sheet

AMIS−30543
http://onsemi.com
30
The voltage regulator remains active but with reduced
current−output capability (I
LOADSLP
). The watchdog timer
stops running and it’s value is kept in the counter. Upon
leaving sleep mode, this timer continues from the value it
had before entering sleep mode.
Normal operation is resumed after writing logic ‘0’ to bit
<SLP>. A startup time is needed for the charge pump to
stabilize. After this time, NXT commands can be issued.
t
PU
POR/WD pin
t
POR
VBB
V
DDH
VDD
t
t
t
DSPI
Enable WD
Acknowledge WD
WD timer
t
POR
t
WDRD
= t
WDPR
or = t
WDTO
>t
WDPR
and < t
WDTO
t
t
t
WDTO
Figure 17. Watchdog Timing Diagram
NOTE: t
DSPI
is the time needed by the external microcontroller to shift−in the <WDEN> bit after a powerup.
The duration of the watchdog timeout interval is programmable through the WDT[3:0] bits (See also Table 11: SPI
CONTROL REGISTERS. The timing is given in Table 10 below.
Table 10. WATCHDOG TIMEOUT INTERVAL AS FUNCTION OF WDT[3.0]
Index WDT[3:0] t
WDTO
(ms) Index WDT[3:0] t
WDTO
(ms)
0 0000 32 8 1000 288
1 0001 64 9 1001 320
2 0010 96 10 1010 352
3 0011 128 11 1011 384
4 0100 160 12 1100 416
5 0101 192 13 1101 448
6 0110 224 14 1110 480
7 0111 256 15 1111 512