Data Sheet

ManualsBrandsPololu ManualsStepper Motor ControllersAMIS-30543 Stepper Motor Driver Carrier

March, 2014 − Rev. 2

1 Publication Order Number:

AMIS−30543/D

AMIS-30543

Micro-Stepping Motor

Driver

Introduction

The AMIS−30543 is a micro−stepping stepper motor driver for

bipolar stepper motors. The chip is connected through I/O pins and an

SPI interface with an external microcontroller. It has an on−chip

voltage regulator, reset−output and watchdog reset, able to supply

peripheral devices. AMIS−30543 contains a current−translation table

and takes the next micro−step depending on the clock signal on the

“NXT” input pin and the status of the “DIR” (=direction) register or

input pin. The chip provides a so−called “speed and load angle”

output. This allows the creation of stall detection algorithms and

control loops based on load−angle to adjust torque and speed. It is

using a proprietary PWM algorithm for reliable current control.

The AMIS−30543 is implemented in I2T100 technology, enabling

both high−voltage analog circuitry and digital functionality on the

same chip. The chip is fully compatible with the automotive voltage

requirements.

The AMIS−30543 is ideally suited for general−purpose stepper

motor applications in the automotive, industrial, medical, and marine

environment. With the on−chip voltage regulator it further reduces the

BOM for mechatronic stepper applications.

Key Features

• Dual H−Bridge for 2−Phase Stepper Motors

• Programmable Peak−Current Up to 3 A

• On−Chip Current Translator

• SPI Interface

• Speed and Load Angle Output

• Eleven Step Modes from Full Step Up to 128 Micro−Steps

• Fully Integrated Current−Sense

• PWM Current Control with Automatic Selection of Fast and Slow

Decay

• Low EMC PWM with Selectable Voltage Slopes

• Active Fly−Back Diodes

• Full Output Protection and Diagnosis

• Thermal Warning and Shutdown

• Compatible with 5 V and 3.3 V Microcontrollers

• Integrated 5 V Regulator to Supply External Microcontroller

• Integrated Reset Function to Reset External Microcontroller

• Integrated Watchdog Function

• These Devices are Pb−Free and are RoHS Compliant

See detailed ordering and shipping information in the package

dimensions section on page 37 of this data sheet.

ORDERING INFORMATION

http://onsemi.com

MARKING DIAGRAM

QFN32

CASE 485J

132

AMIS30543

0C543−001

AWLYYWWG

A = Assembly Location

WL = Wafer Lot

YY = Year

WW = Work Week

G = Pb−Free Package

Summary of content (38 pages)

PAGE 1
AMIS-30543 Micro-Stepping Motor Driver Introduction The AMIS−30543 is a micro−stepping stepper motor driver for bipolar stepper motors. The chip is connected through I/O pins and an SPI interface with an external microcontroller. It has an on−chip voltage regulator, reset−output and watchdog reset, able to supply peripheral devices.
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AMIS−30543 BLOCK DIAGRAM CLK Timebase VDD CPN CPP VCP Vreg Chargepump POR EMC CS DI DO NXT Logic & Registers DIR P W M T R A N S L A T O R OTP SPI Load Angle SLA I−sense EMC P W M Temp . Sense POR/WD AMIS−30543 Band− gap TST0 GND Figure 1.
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AMIS−30543 Table 1.
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AMIS−30543 EQUIVALENT SCHEMATICS Following figure gives the equivalent schematics of the user relevant inputs and outputs. The diagrams are simplified representations of the circuits used. 4K IN OUT Rin TYPE 1: CLR input IN TYPE 4: DO, ERRB and PORB/WD open drain outputs 4K Rout TYPE 2 : CLK , DI, CSB , NXT , DIR inputs TYPE 5: SLA analog output VDD VBB VDD VBB . TYPE 3: VDD and VBB power supply inputs Figure 3. In− and Output Equivalent Diagrams http://onsemi.
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AMIS−30543 PACKAGE THERMAL CHARACTERISTICS The Rthja for 2S2P is simulated conform JEDEC JESD−51 as follows: • A 4−layer printed circuit board with inner power planes and outer (top and bottom) signal layers is used • Board thickness is 1.
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AMIS−30543 Table 4. DC PARAMETERS (The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified) Convention: currents flowing in the circuit are defined as positive. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit 30 V 12 mA 5.5 V 5.
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AMIS−30543 Table 4. DC PARAMETERS (The DC parameters are given for VBB and temperature in their operating ranges unless otherwise specified) Convention: currents flowing in the circuit are defined as positive. Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit 0.
PAGE 8
AMIS−30543 Table 5. AC PARAMETERS (The AC parameters are given for VBB and temperature in their operating ranges) Symbol Pin(s) Parameter Remark/Test Conditions Min Typ Max Unit 3.6 4 4.4 MHz 20.5 22.8 25.1 kHz 41.0 45.6 50.
PAGE 9
AMIS−30543 tNXT_LO tNXT_HI 0.5 VCC NXT tDIR_SET ÌÌÌ ÌÌÌ ÌÌÌ DIR tDIR_HOLD ÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌ VALID Figure 5. NXT−Input Timing Diagram Table 6. SPI TIMING PARAMETERS Symbol tCLK Parameter Min SPI Clock Period Typ Max Unit 1 ms tCLK_HIGH SPI Clock High Time 100 ns tCLK_LOW SPI Clock Low Time 100 ns DI Set Up Time, Valid Data Before Rising Edge of CLK 50 ns DI Hold Time, Hold Data After Rising Edge of CLK 50 ns tSET_DI tHOLD_DI tCSB_HIGH CS High Time 2.
PAGE 10
AMIS−30543 TYPICAL APPLICATION SCHEMATIC 100 nF 100 nF C2 C4 C5 R2 100 nF R3 D1 100 nF C6 R4 VDD VBB 32 14 DIR VBB 4 DO 31 3 CS 10 25, 26 2 CLK 21, 22 13 CLR 15, 16 12 ERR 6 SLA C8 9 AMIS−30543 NXT DI mC 28 5 100mF 220 nF 27 11 POR/WD V BAT C1 C3 19, 20 VCP CPN C7 220 nF CPP MOTXP MOTXN MOTYP M MOTYN 7 R1 1 17 18 23 24 29 TSTO GND Figure 7. Typical Application Schematic AMIS−30543 Table 7.
PAGE 11
AMIS−30543 FUNCTIONAL DESCRIPTION H−Bridge Drivers A full H−bridge is integrated for each of the two stator windings. Each H−bridge consists of two low−side and two high−side N−type MOSFET switches. Writing logic ‘0’ in bit disables all drivers (high−impedance). Writing logic ‘1’ in this bit enables both bridges and current can flow in the motor stator windings.
PAGE 12
AMIS−30543 Automatic Duty Cycle Adaptation In case the supply voltage is lower than 2*Bemf, then the duty cycle of the PWM is adapted automatically to > 50% to maintain the requested average current in the coils. This process is completely automatic and requires no additional parameters for operation.
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AMIS−30543 Table 9.
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AMIS−30543 Table 9.
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AMIS−30543 Table 9.
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AMIS−30543 Table 9.
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AMIS−30543 Table 9.
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AMIS−30543 Table 9.
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AMIS−30543 Table 9.
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AMIS−30543 Table 9.
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AMIS−30543 Table 9.
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AMIS−30543 Table 9.
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AMIS−30543 Table 9.
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AMIS−30543 Table 9.
PAGE 25
AMIS−30543 IY IY IY Start = 0 Start = 0 Start = 0 Step 1 Step 2 Step 1 Step 1 Step 3 Step 2 Step 2 IX IX IX Step 3 Step 3 1/4th micro step Uncompensated half step IY Compensated half step IY Step 3 IY Start = 0 Start = 0 Step 3 Step 3 Step 1 IX IX Uncompensated full step IX Step 2 Step 1 Step 2 Start = 0 Step 1 Step 2 Compensated full step, 1 phase on Compensated full step, 2 phase on Figure 10.
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AMIS−30543 Change from lower to higher resolution Iy Iy DIR endpos NXT3 NXT2 Change from higher to lower resolution Iy DIR NXT1 NXT4 NXT1 endpos startpos Ix DIR startpos NXT2 Ix Ix 1/4th step Halfstep Iy DIR Ix NXT3 1/8th step Halfstep PC20070604.6 Figure 12. NXT−Step Mode Synchronization Left: Change from lower to higher resolution. The left−hand side depicts the ending half−step position during which a new step mode resolution was programmed.
PAGE 27
AMIS−30543 Speed and Load Angle Output The SLA−pin provides an output voltage that indicates the level of the Back−e.m.f. voltage of the motor. This Back−e.m.f. voltage is sampled during every so−called ”coil current zero crossings”. Per coil, two zero−current positions exist per electrical period, yielding in total four zero−current observation points per electrical period.
PAGE 28
AMIS−30543 VCOIL div2 div4 Ssh Sh buf SLA−pin Ch Csh Icoil=0 PWMsh SLAT NOT(Icoil=0) PWMsh Icoil=0 SLAT VCOIL t SLA−pin last sample is retained VBEMF retain last sample previous output is kept at SLA pin SLAT = 1 => SLA−pin is “transparent” during VBEMF sampling @ Coil Current Zero Crossing. SLA−pin is updated “real−time”. t SLAT = 0 => SLA−pin is not “transparent” during VBEMF sampling @ Coil Current Zero Crossing. SLA−pin is updated when leaving current−less state. Figure 15.
PAGE 29
AMIS−30543 Error Output This is a digital output to flag a problem to the external microcontroller. The signal on this output is active low and the logic combination of: NOT(ERRB) = OR OR OR OR OR circuitry, the specified Iload should be reduced with the consumption of internal circuitry (unloaded outputs) and the loads connected to logic outputs. See Table 4.
PAGE 30
AMIS−30543 The voltage regulator remains active but with reduced current−output capability (ILOADSLP). The watchdog timer stops running and it’s value is kept in the counter. Upon leaving sleep mode, this timer continues from the value it had before entering sleep mode. Normal operation is resumed after writing logic ‘0’ to bit . A startup time is needed for the charge pump to stabilize. After this time, NXT commands can be issued.
PAGE 31
AMIS−30543 SPI INTERFACE DO signal is the output from the Slave (AMIS−30543), and DI signal is the output from the Master. A chip select line (CS) allows individual selection of a Slave SPI device in a multiple−slave system. The CS line is active low. If AMIS−30543 is not selected, DO is pulled up with the external pull up resistor. Since AMIS−30543 operates as a Slave in MODE 0 (CPOL = 0; CPHA = 0) it always clocks data out on the falling edge and samples data in on rising edge of clock.
PAGE 32
AMIS−30543 READ command. This READ command contains the address of the SPI register to be read out. At the falling edge of the eight clock pulse the data−out shift register is updated with the content of the corresponding internal SPI register. In the next 8−bit clock pulse train this data is shifted out via DO pin. At the same time the data shifted in from DI (Master) should be interpreted as the following successive command or dummy data.
PAGE 33
AMIS−30543 The NEW DATA is written into the corresponding internal register at the rising edge of CS CS COMMAND DI DATA NEW DATA for ADDR3 WRITE DATA to ADDR3 DATA from previous command or NOT VALID after POR or RESET DATA DO DATA OLD DATA or NOT VALID OLD DATA from ADDR3 Figure 21. Single WRITE Operation Where DATA from the Master is Written in SPI Register with Address 3 Examples of combined READ and WRITE Operations In the following examples successive READ and WRITE operations are combined.
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AMIS−30543 The NEW DATA is written into the corresponding internal register at the rising edge of CS Registers are updated with the internal status at the rising edge of CS CS DI COMMAND DATA COMMAND WRITE DATA to ADDR2 NEW DATA for ADDR2 READ DATA from ADDR2 DATA from previous command or NOT VALID after POR or RESET DATA DO DATA DATA OLD DATA from ADDR2 NEW DATA from ADDR2 DATA OLD DATA or NOT VALID OLD DATA from ADDR2 COMMAND or DUMMY Figure 23.
PAGE 35
AMIS−30543 Table 12.
PAGE 36
AMIS−30543 CUR[4:0] Selects IMCmax peak. This is the peak or amplitude of the regulated current waveform in the motor coils. Table 13.
PAGE 37
AMIS−30543 Table 15. SPI STATUS FLAGS OVERVIEW Mnemonic Flag Length (bit) Related SPI Register CPFail Charge pump failure 1 Status Register 0 MSP[8:0] Micro−step position 9 OPENX OPEN Coil X 1 Status Register 0 ‘1’ = Open coil detected ‘0’ OPENY OPEN Coil Y 1 Status Register 0 ‘1’ = Open coil detected ‘0’ OVCXNB OVer Current on X H−bridge; MOTXN terminal; Bottom tran.
PAGE 38
AMIS−30543 PACKAGE DIMENSIONS QFN32 7x7, 0.65P CASE 485J−02 ISSUE E ÇÇ PIN 1 INDICATOR A B D NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.25MM FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. L L L1 DETAIL A E ALTERNATE TERMINAL CONSTRUCTIONS DIM A A1 A3 b D D2 E E2 e K L L1 0.15 C 2X 2X TOP VIEW DETAIL B 0.