Datasheet
Table Of Contents
- Introduction
- Features
- Table of Contents
- 1. Description
- 2. Configuration Summary
- 3. Ordering Information
- 4. Block Diagram
- 5. Pin Configurations
- 6. I/O Multiplexing
- 7. Resources
- 8. About Code Examples
- 9. AVR CPU Core
- 10. AVR Memories
- 11. System Clock and Clock Options
- 11.1. Clock Systems and Their Distribution
- 11.2. Clock Sources
- 11.3. Low-Power Crystal Oscillator
- 11.4. Low Frequency Crystal Oscillator
- 11.5. Calibrated Internal RC Oscillator
- 11.6. 128 kHz Internal Oscillator
- 11.7. External Clock
- 11.8. Clock Output Buffer
- 11.9. Timer/Counter Oscillator
- 11.10. System Clock Prescaler
- 11.11. Register Description
- 12. CFD - Clock Failure Detection mechanism
- 13. Power Management and Sleep Modes
- 14. System Control and Reset
- 15. INT- Interrupts
- 16. EXTINT - External Interrupts
- 16.1. Pin Change Interrupt Timing
- 16.2. Register Description
- 16.2.1. External Interrupt Control Register A
- 16.2.2. External Interrupt Mask Register
- 16.2.3. External Interrupt Flag Register
- 16.2.4. Pin Change Interrupt Control Register
- 16.2.5. Pin Change Interrupt Flag Register
- 16.2.6. Pin Change Mask Register 3
- 16.2.7. Pin Change Mask Register 2
- 16.2.8. Pin Change Mask Register 1
- 16.2.9. Pin Change Mask Register 0
- 17. I/O-Ports
- 17.1. Overview
- 17.2. Ports as General Digital I/O
- 17.3. Alternate Port Functions
- 17.4. Register Description
- 17.4.1. MCU Control Register
- 17.4.2. Port B Data Register
- 17.4.3. Port B Data Direction Register
- 17.4.4. Port B Input Pins Address
- 17.4.5. Port C Data Register
- 17.4.6. Port C Data Direction Register
- 17.4.7. Port C Input Pins Address
- 17.4.8. Port D Data Register
- 17.4.9. Port D Data Direction Register
- 17.4.10. Port D Input Pins Address
- 17.4.11. Port E Data Register
- 17.4.12. Port E Data Direction Register
- 17.4.13. Port E Input Pins Address
- 18. TC0 - 8-bit Timer/Counter0 with PWM
- 19. TC1, 3, 4 - 16-bit Timer/Counter1, 3, 4 with PWM
- 19.1. Features
- 19.2. Overview
- 19.3. Accessing 16-bit Timer/Counter Registers
- 19.4. Timer/Counter Clock Sources
- 19.5. Counter Unit
- 19.6. Input Capture Unit
- 19.7. Compare Match Output Unit
- 19.8. Output Compare Units
- 19.9. Modes of Operation
- 19.10. Timer/Counter Timing Diagrams
- 19.11. Register Description
- 19.11.1. TC1 Control Register A
- 19.11.2. TC1 Control Register B
- 19.11.3. TC1 Control Register C
- 19.11.4. TC1 Counter Value Low and High byte
- 19.11.5. Input Capture Register 1 Low and High byte
- 19.11.6. Output Compare Register 1 A Low and High byte
- 19.11.7. Output Compare Register 1 B Low and High byte
- 19.11.8. TC3 Control Register A
- 19.11.9. TC3 Control Register B
- 19.11.10. TC3 Control Register C
- 19.11.11. TC3 Counter Value Low and High byte
- 19.11.12. Input Capture Register 3 Low and High byte
- 19.11.13. Output Compare Register 3 A Low and High byte
- 19.11.14. Output Compare Register 3 B Low and High byte
- 19.11.15. TC4 Control Register A
- 19.11.16. TC4 Control Register B
- 19.11.17. TC4 Control Register C
- 19.11.18. TC4 Counter Value Low and High byte
- 19.11.19. Input Capture Register 4 Low and High byte
- 19.11.20. Output Compare Register 4 A Low and High byte
- 19.11.21. Output Compare Register 4 B Low and High byte
- 19.11.22. Timer/Counter 1 Interrupt Mask Register
- 19.11.23. Timer/Counter 3 Interrupt Mask Register
- 19.11.24. Timer/Counter 4 Interrupt Mask Register
- 19.11.25. TC1 Interrupt Flag Register
- 19.11.26. TC3 Interrupt Flag Register
- 19.11.27. TC4 Interrupt Flag Register
- 20. Timer/Counter 0, 1, 3, 4 Prescalers
- 21. TC2 - 8-bit Timer/Counter2 with PWM and Asynchronous Operation
- 21.1. Features
- 21.2. Overview
- 21.3. Timer/Counter Clock Sources
- 21.4. Counter Unit
- 21.5. Output Compare Unit
- 21.6. Compare Match Output Unit
- 21.7. Modes of Operation
- 21.8. Timer/Counter Timing Diagrams
- 21.9. Asynchronous Operation of Timer/Counter2
- 21.10. Timer/Counter Prescaler
- 21.11. Register Description
- 21.11.1. TC2 Control Register A
- 21.11.2. TC2 Control Register B
- 21.11.3. TC2 Counter Value Register
- 21.11.4. TC2 Output Compare Register A
- 21.11.5. TC2 Output Compare Register B
- 21.11.6. TC2 Interrupt Mask Register
- 21.11.7. TC2 Interrupt Flag Register
- 21.11.8. Asynchronous Status Register
- 21.11.9. General Timer/Counter Control Register
- 22. OCM - Output Compare Modulator
- 23. SPI – Serial Peripheral Interface
- 24. USART - Universal Synchronous Asynchronous Receiver Transceiver
- 24.1. Features
- 24.2. Overview
- 24.3. Block Diagram
- 24.4. Clock Generation
- 24.5. Frame Formats
- 24.6. USART Initialization
- 24.7. Data Transmission – The USART Transmitter
- 24.8. Data Reception – The USART Receiver
- 24.9. Asynchronous Data Reception
- 24.10. Multi-Processor Communication Mode
- 24.11. Examples of Baud Rate Setting
- 24.12. Register Description
- 25. USARTSPI - USART in SPI Mode
- 26. TWI - Two-Wire Serial Interface
- 26.1. Features
- 26.2. Two-Wire Serial Interface Bus Definition
- 26.3. Data Transfer and Frame Format
- 26.4. Multi-Master Bus Systems, Arbitration, and Synchronization
- 26.5. Overview of the TWI Module
- 26.6. Using the TWI
- 26.7. Transmission Modes
- 26.8. Multi-Master Systems and Arbitration
- 26.9. Register Description
- 27. AC - Analog Comparator
- 28. ADC - Analog-to-Digital Converter
- 29. PTC - Peripheral Touch Controller
- 30. debugWIRE On-chip Debug System
- 31. BTLDR - Boot Loader Support – Read-While-Write Self-Programming
- 31.1. Features
- 31.2. Overview
- 31.3. Application and Boot Loader Flash Sections
- 31.4. Read-While-Write and No Read-While-Write Flash Sections
- 31.5. Entering the Boot Loader Program
- 31.6. Boot Loader Lock Bits
- 31.7. Addressing the Flash During Self-Programming
- 31.8. Self-Programming the Flash
- 31.8.1. Performing Page Erase by SPM
- 31.8.2. Filling the Temporary Buffer (Page Loading)
- 31.8.3. Performing a Page Write
- 31.8.4. Using the SPM Interrupt
- 31.8.5. Consideration While Updating Boot Loader Section (BLS)
- 31.8.6. Prevent Reading the RWW Section During Self-Programming
- 31.8.7. Setting the Boot Loader Lock Bits by SPM
- 31.8.8. EEPROM Write Prevents Writing to SPMCSR
- 31.8.9. Reading the Fuse and Lock Bits from Software
- 31.8.10. Reading the Signature Row from Software
- 31.8.11. Preventing Flash Corruption
- 31.8.12. Programming Time for Flash when Using SPM
- 31.8.13. Simple Assembly Code Example for a Boot Loader
- 31.8.14. Boot Loader Parameters
- 31.9. Register Description
- 32. MEMPROG - Memory Programming
- 32.1. Program And Data Memory Lock Bits
- 32.2. Fuse Bits
- 32.3. Signature Bytes
- 32.4. Calibration Byte
- 32.5. Serial Number
- 32.6. Page Size
- 32.7. Parallel Programming Parameters, Pin Mapping, and Commands
- 32.8. Parallel Programming
- 32.8.1. Entering Programming Mode
- 32.8.2. Considerations for Efficient Programming
- 32.8.3. Chip Erase
- 32.8.4. Programming the Flash
- 32.8.5. Programming the EEPROM
- 32.8.6. Reading the Flash
- 32.8.7. Reading the EEPROM
- 32.8.8. Programming the Fuse Low Bits
- 32.8.9. Programming the Fuse High Bits
- 32.8.10. Programming the Extended Fuse Bits
- 32.8.11. Programming the Lock Bits
- 32.8.12. Reading the Fuse and Lock Bits
- 32.8.13. Reading the Signature Bytes
- 32.8.14. Reading the Calibration Byte
- 32.8.15. Parallel Programming Characteristics
- 32.9. Serial Downloading
- 33. Electrical Characteristics
- 33.1. Absolute Maximum Ratings
- 33.2. DC Characteristics
- 33.3. Power Consumption
- 33.4. Speed Grades
- 33.5. Clock Characteristics
- 33.6. System and Reset Characteristics
- 33.7. SPI Timing Characteristics
- 33.8. Two-Wire Serial Interface Characteristics
- 33.9. ADC Characteristics
- 33.10. Parallel Programming Characteristics
- 34. Typical Characteristics
- 34.1. Active Supply Current
- 34.2. Idle Supply Current
- 34.3. ATmega328PB Supply Current of I/O Modules
- 34.4. Power-Down Supply Current
- 34.5. Pin Pull-Up
- 34.6. Pin Driver Strength
- 34.7. Pin Threshold and Hysteresis
- 34.8. BOD Threshold
- 34.9. Analog Comparator Offset
- 34.10. Internal Oscillator Speed
- 34.11. Current Consumption of Peripheral Units
- 34.12. Current Consumption in Reset and Reset Pulse Width
- 35. Register Summary
- 36. Instruction Set Summary
- 37. Packaging Information
- 38. Errata
- 39. Revision History
- The Microchip Web Site
- Customer Change Notification Service
- Customer Support
- Microchip Devices Code Protection Feature
- Legal Notice
- Trademarks
- Quality Management System Certified by DNV
- Worldwide Sales and Service
rising TOSC1 edge. When waking up from Power-Save mode, and the I/O clock (clk
I/O
) again
becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising
TOSC1 edge. The phase of the TOSC clock after waking up from Power-Save mode is essentially
unpredictable, as it depends on the wake-up time. The recommended procedure for reading
TCNT2 is thus as follows:
8.1. Wait for the corresponding update busy flag to be cleared.
8.2. Read TCNT2.
• During asynchronous operation, the synchronization of the interrupt flags for the asynchronous
timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least
one before the processor can read the timer value causing the setting of the interrupt flag. The
output compare pin is changed on the timer clock and is not synchronized to the processor clock.
21.10 Timer/Counter Prescaler
Figure 21-12. Prescaler for TC2
10-BIT T/C PRESCALER
TIMER/COUNTER2 CLOCK SOURCE
I/O
clk
T2S
TOSC1
clk
T2S
/8
clk
T2S
/64
clk
T2S
/128
clk
T2S
/1024
clk
T2S
/256
clk
T2S
/32
0
PSRASY
T2
AS2
CS20
CS21
CS22
Clear
clk
clk
The clock source for TC2 is named clk
T2S
. It is by default connected to the main system I/O clock clk
I/O
.
By writing a '1' to the Asynchronous TC2 bit in the Asynchronous Status Register (ASSR.AS2), TC2 is
asynchronously clocked from the TOSC1 pin. This enables the use of TC2 as a Real Time Counter
(RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port B. A crystal can then be
connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for TC2. The
oscillator is optimized for use with a 32.768 kHz crystal.
For TC2, the possible prescaled selections are: clk
T2S
/8, clk
T2S
/32, clk
T2S
/64, clk
T2S
/128, clk
T2S
/256, and
clk
T2S
/1024. Additionally, clk
T2S
, as well as 0 (stop), may be selected. The prescaler is reset by writing a
'1' to the Prescaler Reset TC2 bit in the General TC2 Control Register (GTCCR.PSRASY). This allows
the user to operate with a defined prescaler.
21.11 Register Description
ATmega328PB
TC2 - 8-bit Timer/Counter2 with PWM and Asynchrono...
© 2018 Microchip Technology Inc.
Datasheet Complete
40001906b-page 231










