Datasheet

Table Of Contents

19.11.7 Output Compare Register 1 B Low and High byte

Name: OCR1BL and OCR1BH

Offset: 0x8A

Reset: 0x00

Property: -

The OCR1BL and OCR1BH register pair represents the 16-bit value, OCR1B. The low byte [7:0] (suffix L)

is accessible at the original offset. The high byte [15:8] (suffix H) can be accessed at offset + 0x01. For

more details on reading and writing 16-bit registers, refer to Accessing 16-bit Timer/Counter Registers.

Bit 15 14 13 12 11 10 9 8

OCR1B[15:8]

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bit 7 6 5 4 3 2 1 0

OCR1B[7:0]

Access

R/W R/W R/W R/W R/W R/W R/W R/W

Reset 0 0 0 0 0 0 0 0

Bits 15:0 – OCR1B[15:0] Output Compare 1 B

The output compare registers contain a 16-bit value that is continuously compared with the counter value

(TCNT1). A match can be used to generate an output compare interrupt or to generate a waveform

output on the OC1B pin.

The output compare registers are 16-bit in size. To ensure that both the high and low bytes are written

simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary

high byte register (TEMP). This temporary register is shared by all the other 16-bit registers. Refer to

Accessing 16-bit Timer/Counter Registers for details.