TB67S128FTG TOSHIBA BiCD Integrated Circuit Silicon Monolithic TB67S128FTG CLOCK-in and Serial controlled Bipolar Stepping Motor Driver 1. Outline The TB67S128FTG is a two-phase bipolar stepping motor driver using a PWM chopper. The clock in decoder is built in. Fabricated with the BiCD process, output rating is 50 V/5.0 A (Motor supply voltage = 44 V). 2. Features P-VQFN64-0909-0.50-006 BiCD process integrated monolithic IC. Capable of controlling 1 bipolar stepping motor.
TB67S128FTG 3. Pin Assignment Pin assignment in CLK mode (IF_SEL pin = L) is shown in below figure.
TB67S128FTG 4. Pin Description Pin No. Symbol Description CLK mode Serial mode 1 TESTO_1 (Note1) TESTO_1 (Note1) TEST OUT pin No.1 2 TESTO_2 (Note1) TESTO_2 (Note1) TEST OUT pin No.2 3 TESTO_3 (Note1) TESTO_3 (Note1) TEST OUT pin No.3 4 SGND SGND 5 OSCM OSCM 6 CLIM0 (Note1) NC AGC current limiter setup pin No.0 7 CLIM1 (Note1) NC AGC current limiter setup pin No.
TB67S128FTG Pin No. Symbol Description CLK mode Serial mode 44 TORQE0 NC Torque setting pin No.0 45 TORQE1 NC Torque setting pin No.1 46 TORQE2 NC Torque setting pin No.2 47 AGC NC Active Gain Control setup pin 48 NC NC NC pin 49 MODE0 NC Excitation setting pin No.0 50 MODE1 NC Excitation setting pin No.1 51 MODE2 NC Excitation setting pin No.
TB67S128FTG 5. Block Diagram MODE0 MODE1 MODE2 CLK ENABLE RESET STANDBY CW/CCW TORQUE0 TORQUE1 TORQUE2 EDG_SEL MDT0 MDT1 RS_SEL GAIN_SEL IF_SEL AGC CLIM0 CLIM1 FLIM BST LO0 LO1 MO CP+ CPOUT OSCM CP－ VM Charge Pump BUF_MULTI OUT_NOD BIAS VREG_5 OSC_CR BUF_HYS BGR OSC_6.
TB67S128FTG 6. INPUT/OUTPUT Equivalent Circuit LO0, LO1 MO IN/OUT signal Equivalent circuit 1 kΩ Logic input pin Digital Input (VIH/VIL) VIH: 2.0 V (min) to 5.5 V (max) VIL: 0 V (min) to 0.8 V (max) 100 kΩ Pin name MODE0, 1, 2 CLK ENABLE RESET CW/CCW TORQE0, 1, 2 EDG_SEL MDT0, 1 RS_SEL GAIN_SEL IF_SEL STANDBY CLIM0 AGC GND Logic Output Pin Digital Output (VOH/VOL) (Pullup resistance:10 k to 100 kΩ) GND VCC VREF VCC VCC voltage range 4.75 V (min) 5.0 V (typ.) 5.
TB67S128FTG Pin name IN/OUT signal CLIM1 FLIM BST Multi state input pin voltage Connect to VCC Connect to GND Connect to VCC with 100 kΩ pull-up resistor Connect to GND with 100 kΩ pull-down resister (Resistor accuracy should be within ±20 %.) LTH Equivalent circuit VCC Multi state input pin 100 kΩ 1 kΩ 100 kΩ 500 Ω Connect to GND with 100 kΩ pull-down resistor (Resistance accuracy should be within ±20 %.) LTH 500 Ω CPOUT CP+ CP- CPOUT VM power supply voltage range 6.
TB67S128FTG 7. IF Select Function IF can be selected from CLK type or serial type. IF_SEL pin input Function L CLK mode H Serial mode 8. Functional Description 1 (for CLK mode when IF_SEL pin = L) 8.1. CLK Function Each up-edge of the CLK signal will shift the motor’s electrical angle per step. When EDG_SEL pin = L (Single Edge) CLK pin input Function Up-edge Shifts the electrical angle per step. Down-edge (State of the electrical angle does not change.
TB67S128FTG 8.4. Step Resolution Select Function MODE 0, MODE1, and MODE2 pins control the step resolution. Pin levels of MODE0, MODE1, and MODE2 can be switched during operation. The following step current depends on the electrical angle.
TB67S128FTG 8.5. Timing Chart of Step Resolution Setting and Initial Angel [Full step resolution] CLK MO H L H L +100% Iout (A) 0% -100% +100% Iout (B) 0% -100% CCW CW [Half step resolution] CLK MO H L H L +100% +71% Iout (A) 0% -71% -100% +100% +71% Iout (B) 0% -71% -100% CCW CW Note: MO signal is shown in the above timing chart when MO pin is connected with a pull-up resistor to VCC. Note: Timing charts may be simplified for explanatory purpose.
TB67S128FTG [Quarter step resolution] CLK MO Iout (A) Iout (B) H L H L +100% +71% +38% 0% -38% -71% -100% +100% +71% +38% 0% -38% -71% -100% CCW CW Note: MO signal is shown in the above timing chart when MO pin is connected with a pull-up resistor to VCC. Note: Timing charts may be simplified for explanatory purpose.
TB67S128FTG [1/8 step resolution] CLK MO H L H L +100% +98% +96% +83% +71% +56% +38% +20% Iout (A) 0% -20% -38% -56% -71% -83% -96% -98% -100% +100% +98% +96% +83% +71% +56% +38% +20% Iout (B) 0% -20% -38% -56% -71% -83% -96% -98% -100% CCW CW Note: MO signal is shown in the above timing chart when MO pin is connected with a pull-up resistor to VCC. Note: Timing charts may be simplified for explanatory purpose.
TB67S128FTG [1/16 step resolution] CLK MO H L H L +100% +98% +96% +83% +71% +56% +38% +20% Iout (A) 0% -20% -38% -56% -71% -83% -96% -98% -100% +100% +98% +96% +83% +71% +56% +38% +20% Iout (B) 0% -20% -38% -56% -71% -83% -96% -98% -100% CCW CW Note: MO signal is shown in the above timing chart when MO pin is connected with a pull-up resistor to VCC. Note: Timing charts may be simplified for explanatory purpose.
TB67S128FTG 8.6.
TB67S128FTG Current (%) Full Half Quarter 1/8 1/16 1/32 45% 1/64 1/128 Available Available 44% Available 43% Available Available 42% Available 41% Available 39% Available Available 38% Available Available Available Available Available 37% Available Available 36% Available 35% Available Available 34% Available Available 33% Available Available 31% Available 30% Available Available 29% Available Available Available 28% Available Available 27% Available 25%
TB67S128FTG 8.7.
TB67S128FTG STEP 1/128 — Ach (%) Bch (%) θ35 91 42 θ36 90 43 θ37 90 44 θ38 89 45 θ39 89 46 θ40 88 47 θ41 88 48 θ42 87 49 θ43 86 50 θ44 86 51 θ45 85 52 θ46 84 53 θ47 84 55 θ48 83 56 θ49 82 57 θ50 82 58 θ51 81 59 θ52 80 60 θ53 80 61 θ54 79 62 θ55 78 62 θ56 77 63 θ57 77 64 θ58 76 65 θ59 75 66 θ60 74 67 θ61 73 68 θ62 72 69 θ63 72 70 θ64 71 71 θ65 70 72 θ66 69 72 θ67 68 73 θ68 67 74 θ69 66 75 θ70 65 76
TB67S128FTG STEP 1/128 — Ach (%) Bch (%) θ71 64 77 θ72 63 77 θ73 62 78 θ74 62 79 θ75 61 80 θ76 60 80 θ77 59 81 θ78 58 82 θ79 57 82 θ80 56 83 θ81 55 84 θ82 53 84 θ83 52 85 θ84 51 86 θ85 50 86 θ86 49 87 θ87 48 88 θ88 47 88 θ89 46 89 θ90 45 89 θ91 44 90 θ92 43 90 θ93 42 91 θ94 41 91 θ95 39 92 θ96 38 92 θ97 37 93 θ98 36 93 θ99 35 94 θ100 34 94 θ101 33 95 θ102 31 95 θ103 30 95 θ104 29 96 θ105 28 96 θ106
TB67S128FTG STEP 1/128 — Ach (%) Bch (%) θ107 25 97 θ108 24 97 θ109 23 97 θ110 22 98 θ111 21 98 θ112 20 98 θ113 18 98 θ114 17 99 θ115 16 99 θ116 15 99 θ117 13 99 θ118 12 99 θ119 11 99 θ120 10 100 θ121 9 100 θ122 7 100 θ123 6 100 θ124 5 100 θ125 4 100 θ126 2 100 θ127 1 100 θ128 0 100 1/64 1/32 1/16 Ach (%) Bch (%) Ach (%) Bch (%) 24 97 24 97 22 98 20 98 20 98 17 99 15 99 15 99 12 99 10 100 10 100 7 100 5 10
TB67S128FTG 8.8. RESET Function The RESET pin initializes the internal electrical angle. RESET pin input Function L Normal operation mode H Sets the electrical angle to the initial condition. Note: Digital filter of 0.625 μs (±20 %) is implemented to the RESET pin. The current for each channel (while RESET pin is applied) is shown in the table below. MO pin will show L at this time.
TB67S128FTG 8.10. CLK Edge Function CLK edge function can be selected the CLK signal's rising edge or the CLK edge's dual (up and down). EDG_SEL pin input Function L Single edge (Only Up Edge of CLK Signal) H Dual edge (Up and Down edge) 8.11. RS Function RS function can be selected either ACDS mode or external sense RS resistor mode. RS_SEL pin input Function L ACDS (RS resistor less) mode H External sense RS resistor mode Note: PCB board should be designed according to RS Function. 8.12.
TB67S128FTG 8.13. Selectable Mixed Decay Function The Selectable Mixed Decay can adjust the current regeneration amount during the period of current regeneration (Decay) using pins. Though the Mixed Decay is determined by controlling 2 different types of decay (Fast Decay and Slow Decay), this function enables the user to select the ratio of the Mixed Decay using MDT0 and MDT1 pin. (2bit, 4 function) MDT1 pin input MDT0 pin input Function L L Fast Decay: 37.
TB67S128FTG 8.13.1. Mixed Decay Waveform (Current Waveform) fchop fchop OSC internal signal NF detection Current setting NF detection Iout Charge Slow Decay Fast Decay Note: Timing charts may be simplified for explanatory purpose. 8.13.2.
TB67S128FTG 8.13.3. Constant Current PWM Function and Timing OSC internal signal MDT setting NF detection Charge Fast Decay fchop If NF is detected within the MDT0 pin and MDT1 pin setting, Decay sequence will only be Fast Decay (Slow Decay does not appear). Note: Timing charts may be simplified for explanatory purpose.
TB67S128FTG 8.13.4. Mixed Decay current waveform When the next current step is higher: fchop fchop fchop fchop OSC internal Signal Current Setting Current Setting NF NF Fast Charge Slow Fast NF Slow Fast Charge NF Slow Fast Charge Charge Slow When Charge Period is More Than 1 fchop Cycle: When the Charge period is longer than fchop cycle, the Charge period extends until the motor current reaches the NF threshold.
TB67S128FTG 8.13.5. ADMD (Advanced Dynamic Mixed Decay) Constant Current Control (MDT0 pin = H, MDT1 pin = H) The TB67S128FTG supports the Advanced Dynamic Mixed Decay (ADMD) which monitors both charge and discharge current during constant current PWM. The basic sequence of the ADMD is as shown below.
TB67S128FTG 8.13.5.2. Auto Decay Mode Current Waveform When the Next Current Step is Higher: fchop fchop fchop fchop OSC internal signal Setting current value NF NF Fast Charge Setting current value NF Charge Slow NF Fast Charge Fast Slow Fast Slow Charge Slow When Charge Period is More Than 1 fchop Cycle: When the Charge period is longer than fchop cycle, the Charge period will be extended until the motor current reaches the NF threshold.
TB67S128FTG When the Next Current Step is Lower: fchop fchop fchop fchop OSC internal signal Setting current value NF Charge Charge Mode will appear per each fchop cycle to check the current level using RS comparator. If the current level is already above the current set level, the sequence will be switched to Fast Decay in a very short period.
TB67S128FTG 9. Functional Description 2 (for Serial mode when IF_SEL pin = H) When IF_SEL pin = H, the interface is serial input. It performs setting and motor control in the following 32 bit format. When BANK_EN pin is L, initial setting is performed. When the BANK_EN pin is H, the motor is controlled. For the motor control, each current value is set in the serial setting, and the output is updated to the set current value at the timing of the LATCH signal.
TB67S128FTG 9.1. Registers When BANK_EN pin = H The registers when BANK_EN pin = H are shown below. 9.1.1. PHx (x = A and B) The polality of the output current can be selected by PHx register for each channels. PHx register setting Function L Setting the direction of the output current to minus H Setting the direction of the output current to plus 9.1.2. Cx0 to Cx9 (x = A or B) The output of each channel’s DAC for current limitation can be set by Cx0 to Cx9.
TB67S128FTG 9.2. Serial setting example when driving a motor Serial setting example for motor operation is shown below. 1. 2. 3. Set the BANK_EN pin L. Initial setting for AGC, etc. is performed under this condition. Then, set the BANK_EN pin H and configure the motor control to turn on the output transistors. Transmit the 1st to 4th commands repeatedly by keeping the BANK_EN pin level H. The motor operates with full step resolution.
TB67S128FTG 10. Stepping Motor Application Features (Anti-stall, RS resistor less PWM) 10.1. Active Gain Control (Anti-stall) Function AGC pins will set the Active Gain Control to turn on or off. When this pins are set to H, the AGC is turned on, and when this pins are set to L, the AGC is turned off. When the AGC is ON, the motor current is equal or more than the value by setting the VREF pin. The TB67S128FTG reduces gradually the motor current depending on the load torque.
TB67S128FTG 10.4. FLIM (AGC Frequency limit) function The FLIM pin will set the frequency limit for the AGC to be active. The FLIM function is effective when the AGC is used to avoid the motor resonance frequency during ramp up. The FLIM pin is a 4 stated logic input.
TB67S128FTG 11. Common Function (When CLK Mode and Serial Mode) 11.1. LO (Error detect flag output) Function When an error detection function performs, the LO function outputs an error detection as a signal from LO0 and LO1 pins to the outside of TB67S128FTG. The LO0 and LO1 pins are open-drain output pins. The LO0 and LO1 pins need to be pulled up to VCC level via 10 k to 100 kΩ resistor.
TB67S128FTG 12. Output Transistor Function Mode VM VM U1 VM U2 U1 U2 U1 U2 OFF OFF OFF OFF ON L1 L2 L1 OFF ON ON ON Load Load ON L1 Load L2 ON RS_x pin RS_x pin Charge mode A current flow into the motor coil. L2 OFF RS_x pin Fast mode The energy of the motor coil is feed back to the power. Slow mode A current circulates around the motor coil and this device.
TB67S128FTG 13. Calculation of the Predefined Output Current 13.1. External Sense Resistor mode For PWM constant-current control, this IC uses a clock generated by the OSCM oscillator. The peak output current (Setting current value) can be set via the current-sensing resistor (RS) and the reference voltage (Vref), as follows: Iout (max) = Vref(gain) × Note: When GAIN_SEL pin = L, Vref(gain) = For example: 1 5 Vref (V) RS (Ω) (typ. ). And When GAIN_SEL pin = H, Vref(gain) = When Vref = 3.0 (V), RS = 0.
TB67S128FTG 15. Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit Remarks Motor output voltage Vout 50 V — Motor power supply (non active) Motor power supply (active) VM 50 V STANDBY pin = L -0.4 to 44 V STANDBY pin = H (Note1) Motor output current Iout 5.0 A VCPP VM ± 6 V V — Charge pump voltage VCPM VM ± 6 V V — VCPO 50 V — Internal Logic power supply Logic input voltage VCC 6.0 V VIN(H) 6.0 When externally applied. V — VIN(L) -0.
TB67S128FTG 16. Operation Ranges (Ta=-40 to 85°C) Characteristics Motor power supply Motor output current Symbol Min Typ. Max Unit VM 6.5 24 44 V — Iout — 3.0 5.0 A (Note1) VIN(H) 2.0 — 5.5 V VIN(L) 0 — 0.8 V VMO VLO fCLK fchop (range) Vref — — — 40 GND 3.3 3.3 — 70 2.0 5.0 5.0 200 150 3.
TB67S128FTG 18. Electrical Specifications 2 (Ta =25°C, VM = 24 V, unless specified otherwise) Characteristics Symbol Test condition Min Typ. Max Unit Vref input current VCC voltage VCC current Iref VCC ICC — 4.75 — 0 5 2.5 1 5.25 5 μA V mA Vref gain rate Vref(gain) Vref = 2.0 V ICC = 5.0 mA VCC = 5.0 V Vref = 2.0 V GAIN_SEL pin = L 1/5.2 1/5 1/4.
TB67S128FTG 19. AC Electrical Specification (Ta = 25°C, VM = 24 V, 6.8 mH/5.7 Ω) Characteristics Symbol Test condition Min Typ.
TB67S128FTG 20. Other AC Electrical Specification (Ta = 25°C, VM = 24 V, unless specified otherwise) Symbol Test condition Min Typ. Max Unit No. in Timing Chart Serial CLK frequency fSCLK 1.0 — 25 MHz — CLK Cycle tsCKW VIN = 3.3 V VIH = 3.
TB67S128FTG 21. Application Circuit Example (RS_SEL pin = H, IF_SEL pin = L) The application circuit shown in this document is provided for reference purposes only. The data for mass production are not guaranteed.
TB67S128FTG 22. Package Dimensions P-VQFN64-0909-0.50-006 Unit: mm Weight: 0.229 g (typ.
TB67S128FTG Notes on Contents 1. Block Diagrams Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing Charts Timing charts may be simplified for explanatory purposes. 4. Application Circuits The application circuits shown in this document are provided for reference purposes only.
TB67S128FTG IC Usage Considerations Notes on handling of ICs (1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause the device breakdown, damage or deterioration, and may result injury by explosion or combustion. (2) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in case of over current and/or IC failure.
TB67S128FTG Points to remember on handling of ICs (1) Over current Protection Circuit Over current protection circuits (referred to as current limiter circuits) do not necessarily protect ICs under all circumstances. If the Over current protection circuits operate against the over current, clear the over current status immediately.
TB67S128FTG RESTRICTIONS ON PRODUCT USE Toshiba Corporation and its subsidiaries and affiliates are collectively referred to as “TOSHIBA”. Hardware, software and systems described in this document are collectively referred to as “Product”. • TOSHIBA reserves the right to make changes to the information in this document and related Product without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA.
