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STSPIN820 Layout recommendations

7 Layout recommendations

The STSPIN820 integrates the power stage; in order to improve the thermal dissipation, the

exposed pad must be connected to the ground plane on the bottom layer using multiple vias

equally spaced. This ground plane acts as a heatsink, for this reason it should be as wide as

possible.

The voltage supply V

must be stabilized and filtered with a ceramic bypass capacitor,

typically 330 nF. It must be placed on the same side and as close as possible to the VS pin

in order to reject high frequency noise components on the supply. A bulk capacitor could

also be required (typically a 33 F). The connection between the power supply connector

and the V

pins must be as short as possible using wide traces.

In order to ensure the best ground connection between the STSPIN820 and the other

components, a GND plane surrounding the device is recommended.

A capacitor between the REF pin and ground should be positioned as near as possible to

the device in order to filter the noise and stabilize the reference voltage.

Several vias should be positioned as near as possible each sense resistor connecting them

to the ground plane on the bottom layer. In this way, both the GND planes provide a path for

the current flowing into the power stage.

The path between the ground of the shunt resistors and the ceramic bypass capacitor of the

device is critical; for this reason it must be as short as possible minimizing parasitic

inductances that can cause voltage spikes on SENSE and OUT pins.

The OUT pins and the VS nets can be routed using the bottom layer, it is recommended to

use two vias for output connections.

Figure 14. PCB layout example (top layer)

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