Data Sheet

ISL85410
18
FN8375.5
July 24, 2014
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Where GM is the transconductance, g
m
, of the voltage error
amplifier in each phase. Compensator capacitor C
6
is then given
by Equation 10.
Put one compensator pole at zero frequency to achieve high DC
gain, and put another compensator pole at either ESR zero
frequency or half switching frequency, whichever is lower in
Equation 10
. An optional zero can boost the phase margin. 
CZ2
is a zero due to R
2
and C
3

Put compensator zero 2 to 5 times f
c
.
Example: V
IN
= 12V, V
O
= 5V, I
O
= 1A, f
SW
= 500kHz,
R
2
=90.9kΩ, C
o
= 22µF/5mΩ, L = 39µH, f
c
= 50kHz, then
compensator resistance R
6
:
It is acceptable to use 124kΩas theclosest standard value for
R
6
.
It is also acceptable to use the closest standard values for C
6
and
C
7
. There is approximately 3pF parasitic capacitance from V
COMP
to GND; Therefore, C
7
is optional. Use C
6
= 1500pF and
C
7
= OPEN.
Use C
3
= 68pF. Note that C
3
may increase the loop bandwidth
from previous estimated value. Figure 49
shows the simulated
voltage loop gain. It is shown that it has a 75kHz loop bandwidth
with a 61° phase margin and 6dB gain margin. It may be more
desirable to achieve an increased gain margin. This can be
accomplished by lowering R
6
by 20% to 30%. In practice,
ceramic capacitors have significant derating on voltage and
temperature, depending on the type. Please refer to the ceramic
capacitor datasheet for more details.
R
6
2f
c
V
o
C
o
R
t
GM V
FB

----------------------------------
22.75
3
10 f
c
V
o
C
o
==
(EQ. 9)
C
6
R
o
C
o
R
6
---------------
V
o
C
o
I
o
R
6
---------------
C
7
max
R
c
C
o
R
6
---------------
1
f
SW
R
6
----------------------(, )=,==
(EQ. 10)
C
3
1
f
c
R
2
----------------
=
(EQ. 11)
R
6
22.75
3
10 50kHz 5V 22F 125.12k==
(EQ. 12)
C
6
5V 22F
1A 124k
------------------------------
0.88nF==
(EQ. 13)
C
7
max
5m 22F
124k
---------------------------------
1
 500kHz 124k
----------------------------------------------------(, )0.88pF 5.1pF(,)==
(EQ. 14)
C
3
1
 50kHz 90.9k
--------------------------------------------------
= 70pF=
(EQ. 15)
FIGURE 49. SIMULATED LOOP GAIN
60
45
30
15
0
-15
-30
100 1k 10k 100k 1M
FREQUENCY (Hz)
180
150
120
90
60
30
0
100 1k 10k 100k 1M
FREQUENCY (Hz)
PHASE (°)
GAIN (dB)