MC33926 Datasheet
Table Of Contents
- 5.0 A Throttle Control H-Bridge
- Figure 1. 33926 Simplified Application Diagram
- Internal Block Diagram
- Pin Connections
- Electrical Characteristics
- Table 2. Maximum Ratings
- Table 3. Static Electrical Characteristics
- Table 4. Dynamic Electrical Characteristics
- Figure 4. Output Delay Time
- Figure 5. Disable Delay Time
- Figure 6. Output Switching Time
- Figure 7. Current Limit Blanking Time and Constant-OFF Time
- Figure 8. Short-circuit Detection Turn-OFF Time tFAULT
- Figure 9. Output Current Limiting Foldback Region
- Functional Description
- Functional Internal Block Description
- Functional Device operation
- Typical applications
- Packaging
- Additional Documentation
- Table 6. Thermal Performance Comparison
- Figure 15. Surface Mount for Power PQFN with Exposed Pads
- Figure 16. Thermal Test Board
- Table 7. Thermal Resistance Performance
- Figure 17. Device on Thermal Test Board RqJA
- Figure 18. Transient Thermal Resistance RqJA, 1.0 W Step response, Device on Thermal Test Board Area A = 600 (mm2)
- Revision History
Analog Integrated Circuit Device Data
Freescale Semiconductor 7
33926
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 3. Static Electrical Characteristics
Characteristics noted under conditions 8.0 V ≤ V
PWR
≤ 28 V, - 40°C ≤ T
A
≤ 125°C, GND = 0 V unless otherwise noted. Typical
values noted reflect the approximate parameter means at T
A
= 25°C under nominal conditions unless otherwise noted.
Characteristic Symbol Min Typ Max Unit
POWER INPUTS (VPWR)
Operating Voltage Range
(10)
Steady-state
Transient (t < 500 ms)
(11)
Quasi-functional (R
DS(ON)
May Increase by 50%)
V
PWR(SS)
V
PWR(t)
V
PWR(QF)
8.0
–
5.0
–
–
–
28
40
8.0
V
Sleep State Supply Current
(12)
EN, D2, INV, SLEW = Logic [0], IN1, IN2, D1 = Logic [1], and
I
OUT
= 0 A
I
PWR(SLEEP)
– – 50
μA
Standby Supply Current (Part Enabled)
I
OUT
= 0 A, V
EN
= 5.0 V
I
PWR(STANDBY)
– – 20
mA
Under-voltage Lockout Thresholds
V
PWR(FALLING)
V
PWR(RISING)
Hysteresis
V
UVLO(ACTIVE)
V
UVLO(INACTIVE)
V
UVLO(HYS)
4.15
–
150
–
–
200
–
5.0
350
V
V
mV
CHARGE PUMP
Charge Pump Voltage (CP Capacitor = 33 nF)
V
PWR
= 5.0 V
V
PWR
= 28 V
V
CP
- V
PWR
3.5
–
–
–
–
12
V
CONTROL INPUTS
Operating Input Voltage (EN, IN1, IN2, D1, D2, INV, SLEW)
V
I
– – 5.5 V
Input Voltage (IN1, IN2, D1, D2, INV, SLEW)
(13)
Logic Threshold HIGH
Logic Threshold LOW
Hysteresis
V
IH
V
IL
V
HYS
2.0
–
250
–
–
400
–
1.0
–
V
V
mV
Input Voltage (EN) Threshold
V
TH
1.0 – 2.0 V
Logic Input Currents, VPWR = 8.0 V
Inputs EN, D2, INV, SLEW (internal pull-downs), V
IH
= 5.0 V
Inputs IN1, IN2, D1 (internal pull-ups), VIL = 0V
I
IN
20
-200
80
-80
200
-20
μA
Notes
10. Device specifications are characterized over the range of 8.0 V ≤ V
PWR
≤ 28 V. Continuous operation above 28 V may degrade device
reliability. Device is operational down to 5.0
V, but below 8.0 V the output resistance may increase by 50 percent.
11. Device will survive the transient overvoltage indicated for a maximum duration of 500 ms. Transient not to be repeated more than once
every 10 seconds.
12. I
PWR(SLEEP)
is with Sleep mode activated and EN, D2, INV, SLEW = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating.
13. SLEW input voltage hysteresis is guaranteed by design.