VNH5019A-E datasheet
Table Of Contents
- 1 Block diagram and pin description
- 2 Electrical specifications
- Figure 3. Current and voltage conventions
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- 2.4 Waveforms and truth table
- Table 11. Truth table in normal operating conditions
- Figure 4. Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection (option A)
- Figure 5. Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection (option B)
- Table 12. Truth table in fault conditions (detected on OUTA)
- Figure 6. Behavior in fault condition (how a fault can be cleared)
- Table 13. Electrical transient requirements (part 1)
- Table 14. Electrical transient requirements (part 2)
- Table 15. Electrical transient requirements (part 3)
- 2.5 Reverse battery protection
- Figure 7. Definition of the delay times measurement
- Figure 8. Definition of the low-side switching times
- Figure 9. Definition of the high-side switching times
- Figure 10. Definition of dynamic cross conduction current during a PWM operation
- Figure 11. Waveforms in full bridge operation (part 1)
- Figure 12. Waveforms in full bridge operation (part 2)
- Figure 13. Definition of delay response time of sense current
- Figure 14. Half-bridge configuration
- Figure 15. Multi-motors configuration
- 3 Package and PCB thermal data
- 3.1 MultiPowerSO-30 thermal data
- 4 Package and packing information
- 5 Order codes
- 6 Revision history
VNH5019A-E Block diagram and pin description
Doc ID 15701 Rev 7 7/34
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9EN
B
/DIAG
B
Status of high-side and low-side switches B; Open drain output.
This pin must be connected to an external pull up resistor. When
externally pulled low, it disables half-bridge B. In case of fault
detection (thermal shutdown of a high-side FET or excessive
ON-state voltage drop across a low-side FET), this pin is pulled
low by the device (see Table 12: Truth table in fault conditions
(detected on OUTA).
10 IN
B
Counter clockwise input. CMOS compatible
11 CP
Connection to the gate of the external MOS used for the reverse
battery protection
15, 16, 21
OUT
B,
Heat Slug3
Source of high-side switch B / drain of low-side switch B, power
connection to the motor
26, 27, 28 GND
A
Source of low-side switch A and power ground
(1)
18, 19, 20 GND
B
Source of low-side switch B and power ground
(1)
1. GNDA and GNDB must be externally connected together
Table 2. Block descriptions
(1)
1. See Figure 1
Name Description
Logic control
Allows the turn-on and the turn-off of the high-side and the
low-side switches according to the Tabl e 1 1 .
Overvoltage + undervoltage
Shut down the device outside the range [4.5 V to 24 V] for the
battery voltage.
High-side, low-side and clamp
voltage
Protect the high-side and the low-side switches from the
high-voltage on the battery line in all configuration for the motor.
High-side and low-side driver
Drive the gate of the concerned switch to allow a proper R
DS(on)
for the leg of the bridge.
Linear current limiter
Limits the motor current, by reducing the high-side switch
gate-source voltage when short-circuit to ground occurs.
High-side and low-side
overtemperature protection
In case of short-circuit with the increase of the junction’s
temperature, it shuts down the concerned driver to prevent its
degradation and to protect the die.
Low-side overload detector
Detects when low-side current exceeds shutdown current and
latches off the concerned low-side.
Charge pump
Provides the voltage necessary to drive the gate of the external
PowerMOS used for the reverse polarity protection
Table 1. Pin definitions and functions (continued)
Pin Symbol Function