VNH5019A-E datasheet
Table Of Contents
- 1 Block diagram and pin description
- 2 Electrical specifications
- Figure 3. Current and voltage conventions
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- 2.4 Waveforms and truth table
- Table 11. Truth table in normal operating conditions
- Figure 4. Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection (option A)
- Figure 5. Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection (option B)
- Table 12. Truth table in fault conditions (detected on OUTA)
- Figure 6. Behavior in fault condition (how a fault can be cleared)
- Table 13. Electrical transient requirements (part 1)
- Table 14. Electrical transient requirements (part 2)
- Table 15. Electrical transient requirements (part 3)
- 2.5 Reverse battery protection
- Figure 7. Definition of the delay times measurement
- Figure 8. Definition of the low-side switching times
- Figure 9. Definition of the high-side switching times
- Figure 10. Definition of dynamic cross conduction current during a PWM operation
- Figure 11. Waveforms in full bridge operation (part 1)
- Figure 12. Waveforms in full bridge operation (part 2)
- Figure 13. Definition of delay response time of sense current
- Figure 14. Half-bridge configuration
- Figure 15. Multi-motors configuration
- 3 Package and PCB thermal data
- 3.1 MultiPowerSO-30 thermal data
- 4 Package and packing information
- 5 Order codes
- 6 Revision history
Electrical specifications VNH5019A-E
16/34 Doc ID 15701 Rev 7
Possible origins of fault conditions may be:
● OUT
A
is shorted to ground. It follows that, high-side A is in overtemperature state.
● OUT
A
is shorted to V
CC
. It follow that, low-side Power MOSFET is in saturation state.
When a fault condition is detected, the user can know which power element is in fault by
monitoring the IN
A
, IN
B
, DIAG
A
/EN
A
and DIAG
B
/EN
B
pins.
In any case, when a fault is detected, the faulty leg of the bridge is latched off. To turn-on the
respective output (OUT
X
) again, the input signal must rise from low-level to high-level.
Figure 6. Behavior in fault condition (how a fault can be cleared)
Note: In case of the fault condition is not removed, the procedure for unlatching and sending the
device in Stby mode is:
- Clear the fault in the device (toggle: INA if ENA=0 or INB if ENB=0)
- Pull low all inputs, PWM and Diag/EN pins within tDEL.
If the Diag/En pins are already low, PWM=0, the fault can be cleared simply toggling the
input. The device enters in stby mode as soon as the fault is cleared.