VNH5019A-E datasheet
Table Of Contents
- 1 Block diagram and pin description
- 2 Electrical specifications
- Figure 3. Current and voltage conventions
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- 2.4 Waveforms and truth table
- Table 11. Truth table in normal operating conditions
- Figure 4. Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection (option A)
- Figure 5. Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection (option B)
- Table 12. Truth table in fault conditions (detected on OUTA)
- Figure 6. Behavior in fault condition (how a fault can be cleared)
- Table 13. Electrical transient requirements (part 1)
- Table 14. Electrical transient requirements (part 2)
- Table 15. Electrical transient requirements (part 3)
- 2.5 Reverse battery protection
- Figure 7. Definition of the delay times measurement
- Figure 8. Definition of the low-side switching times
- Figure 9. Definition of the high-side switching times
- Figure 10. Definition of dynamic cross conduction current during a PWM operation
- Figure 11. Waveforms in full bridge operation (part 1)
- Figure 12. Waveforms in full bridge operation (part 2)
- Figure 13. Definition of delay response time of sense current
- Figure 14. Half-bridge configuration
- Figure 15. Multi-motors configuration
- 3 Package and PCB thermal data
- 3.1 MultiPowerSO-30 thermal data
- 4 Package and packing information
- 5 Order codes
- 6 Revision history
Electrical specifications VNH5019A-E
14/34 Doc ID 15701 Rev 7
Figure 4. Typical application circuit for DC to 20 kHz PWM operation with reverse battery
protection (option A)
M
μ
C
Reg 5V
+ 5V
HS
A
HS
B
LS
A
LS
B
V
BAT
DIAG
A
/EN
A
CS
IN
A
PWM
OUT
A
OUT
B
3.3K
1K
1K
1K
10K
33nF
1.5K
V
CC
V
BAT
D
S
G
CP
DIAG
B
/EN
B
+5V
1K
3.3K
IN
B
1K
GND
A
GND
B
C
Note:
The external N-channel Power MOSFET used for the reverse battery protection should have the following characteristics:
- BVdss > 20 V (for a reverse battery of -16 V);
- R
DS(on)
< 1/3 of H-bridge total R
DS(on)
- Standard Logic Gate Driving