VNH5019A-E datasheet
Table Of Contents
- 1 Block diagram and pin description
- 2 Electrical specifications
- Figure 3. Current and voltage conventions
- 2.1 Absolute maximum ratings
- 2.2 Thermal data
- 2.3 Electrical characteristics
- 2.4 Waveforms and truth table
- Table 11. Truth table in normal operating conditions
- Figure 4. Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection (option A)
- Figure 5. Typical application circuit for DC to 20 kHz PWM operation with reverse battery protection (option B)
- Table 12. Truth table in fault conditions (detected on OUTA)
- Figure 6. Behavior in fault condition (how a fault can be cleared)
- Table 13. Electrical transient requirements (part 1)
- Table 14. Electrical transient requirements (part 2)
- Table 15. Electrical transient requirements (part 3)
- 2.5 Reverse battery protection
- Figure 7. Definition of the delay times measurement
- Figure 8. Definition of the low-side switching times
- Figure 9. Definition of the high-side switching times
- Figure 10. Definition of dynamic cross conduction current during a PWM operation
- Figure 11. Waveforms in full bridge operation (part 1)
- Figure 12. Waveforms in full bridge operation (part 2)
- Figure 13. Definition of delay response time of sense current
- Figure 14. Half-bridge configuration
- Figure 15. Multi-motors configuration
- 3 Package and PCB thermal data
- 3.1 MultiPowerSO-30 thermal data
- 4 Package and packing information
- 5 Order codes
- 6 Revision history
Electrical specifications VNH5019A-E
12/34 Doc ID 15701 Rev 7
T
TR
Thermal reset temperature 135 °C
T
HYST
Thermal hysteresis 7 15 °C
1. The device is able to pass the ESD and ISO pulse requirements as specified in the Table 14.
Table 8. Protection and diagnostic (continued)
Symbol Parameter Test conditions Min Typ Max Unit
Table 9. Current sense (8 V < V
CC
< 21 V)
Symbol Parameter Test conditions Min Typ Max Unit
K
0
I
OUT
/I
SENSE
I
OUT
= 3 A, V
SENSE
= 0.5 V,
T
j
= - 40 °C to 150°C
4670 7110 10110
dK
0
/K
0
Analog current sense ratio
drift
I
OUT
= 3 A; V
SENSE
= 0.5 V,
T
j
= -40 °C to 150 °C
-19 19 %
K
1
I
OUT
/I
SENSE
I
OUT
= 8 A, V
SENSE
= 1.3V,
T
j
= - 40 °C to 150°C
6060 7030 8330
dK
1
/K
1
Analog current sense ratio
drift
I
OUT
= 8 A; V
SENSE
= 1.3V,
T
j
= -40 °C to 150 °C
-14 14 %
K
2
I
OUT
/I
SENSE
I
OUT
= 15 A, V
SENSE
= 2.4 V,
T
j
= - 40 °C to 150°C
6070 6990 7810
dK
2
/K
2
Analog current sense ratio
drift
I
OUT
= 15 A; V
SENSE
= 2.4 V,
T
j
= -40 °C to 150 °C
-12 12 %
K
3
I
OUT
/I
SENSE
I
OUT
= 25 A, V
SENSE
= 4 V,
T
j
= - 40 °C to 150°C
6000 6940 7650
dK
3
/K
3
Analog current sense ratio
drift
I
OUT
=25 A; V
SENSE
= 4 V,
T
j
= -40 °C to 150 °C
-12 12 %
V
SENSE
Max analog sense output
voltage
I
OUT
= 15 A, R
SENSE
= 1.1 kΩ 5V
I
SENSEO
Analog sense leakage current
I
OUT
= 0 A, V
SENSE
= 0 V, V
CSD
= 5 V,
V
IN
= 0 V,
T
j
= - 40 to 150°C
05
µA
I
OUT
= 0 A, V
SENSE
= 0 V, V
CSD
= 0 V,
V
IN
= 5 V,
T
j
= - 40 to 150°C
0 100
t
DSENSEH
Delay response time from
falling edge of CS_DIS pin
V
IN
= 5 V, V
SENSE
< 4 V, I
OUT
= 8 A,
I
SENSE
= 90% of I
SENSEmax
(see fig Figure 13)
50 µs
t
DSENSEL
Delay response time from
rising edge of CS_DIS pin
V
IN
= 5 V, V
SENSE
< 4 V, I
OUT
= 8 A,
I
SENSE
= 10% of I
SENSEmax
(see fig Figure 13)
20 µs










