Datasheet
www.sensirion.com Version 0.9 – August 2017 6/15
5 Timing Specifications
5.1 Sensor System Timings
The timings refer to the power up and reset of the ASIC part and do not reflect the usefulness of the readings.
Parameter
Symbol
Condition
Min.
Typ.
Max.
Unit
Comments
Power-up time
t
PU
After hard reset, V
DD
≥V
POR
-
0.4
0.6
ms
-
Soft reset time
t
SR
After soft reset
-
0.4
0.6
ms
-
Table 6 System timing specifications.
5.2 Communication Timings
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Comments
SCL clock frequency
f
SCL
-
0
-
400
kHz
-
Hold time (repeated) START
condition
t
HD;STA
After this period, the
first clock pulse is
generated
0.6
-
-
µs
-
LOW period of the SCL clock
t
LOW
-
1.3
-
-
µs
-
HIGH period of the SCL clock
t
HIGH
-
0.6
-
-
µs
-
Set-up time for a repeated
START condition
t
SU;STA
-
0.6
-
-
µs
-
SDA hold time
t
HD;DAT
-
0
-
-
ns
-
SDA set-up time
t
SU;DAT
-
100
-
-
ns
-
SCL/SDA rise time
t
R
-
-
-
300
ns
-
SCL/SDA fall time
t
F
-
-
-
300
ns
-
SDA valid time
t
VD;DAT
-
-
-
0.9
µs
-
Set-up time for STOP condition
t
SU;STO
-
0.6
-
-
µs
-
Capacitive load on bus line
C
B
-
400
pF
-
Table 7 Communication timing specifications.
Figure 8 Timing diagram for digital input/output pads. SDA directions are seen from the sensor.
Bold SDA lines are controlled by the sensor; plain SDA lines are controlled by the micro-controller.
Note that SDA valid read time is triggered by falling edge of preceding toggle.
SCL
70%
30%
t
LOW
1/f
SCL
t
HIGH
t
R
t
F
SDA
70%
30%
t
SU;DAT
t
HD;DAT
DATA IN
t
R
SDA
70%
30%
DATA OUT
t
VD;DAT
t
F