Datasheet

Bottom Layer Copper Fill (GND)
Direct to
Processor or
full high/low
for control
pins
12V
Top Layer
Copper Fill (GND)
3.3V
3.3V
DVDD 20
DGND 19
LDOO 18
XSMT 17
FMT 16
LRCK 15
DIN 14
BCK 13
SCK 12
FLT 11
1 CPVDD
2 CAPP
3 CPGND
4 CAPM
5 VNEG
6 OUTL
7 OUTR
8 AVDD
9 AGND
10 DEMP
PCM5100A , PCM5101A , PCM5102A
PCM5100A-Q1 , PCM5101A-Q1 , PCM5102A-Q1
SLAS859C –MAY 2012–REVISED MAY 2015 www.ti.com
12 Layout
12.1 Layout Guidelines
• The PCM510xA family of devices are simple to layout. Most engineers use a shared common ground for an
entire device. GND can be consider AGND and DGND connected.
• Good system partitioning should keep digital clock and interface traces away from the analog outputs for
highest analog performance. This reduces any high speed clock return currents influencing the analog
outputs.
• Power supply and charge pump decoupling capacitors should be placed as close as possible to the device.
• The top layer should be used for routing signals, whilst the bottom layer can be used for GND.
Figure 43. PCM510x Layout Example
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Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1