Datasheet

3.3V
XSMT
I2S Clocks
SCK, BCK, LRCK
3 ms
VDD
0V
High
Low
High
Low
Time
3.3V
XSMT
I
2
S Clocks
SCK, BCK, LRCK
150t + 0.2ms
S
VDD
0V
High
Low
High
Low
Time
PCM5100A , PCM5101A , PCM5102A
PCM5100A-Q1 , PCM5101A-Q1 , PCM5102A-Q1
www.ti.com SLAS859C –MAY 2012–REVISED MAY 2015
Recommended Powerdown Sequence (continued)
Figure 36. Assert XSMT
2. Stop I
2
S clocks (SCK, BCK, LRCK) 3 ms before powerdown as shown in Figure 37.
Figure 37. Stop I
2
C Clocks
11.2.2 Unplanned Shutdown
Many systems use a low-noise regulator to provide an AVDD 3.3-V supply for the DAC. The XSMT Pin can take
advantage of such a feature to measure the pre-regulated output from the system SMPS to mute the output
before the entire SMPS discharges. Figure 38 shows how to configure such a system to use the XSMT pin. The
XSMT pin can also be used in parallel with a GPIO pin from the system microcontroller/DSP or power supply.
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