Datasheet
PCM186x
DAC
Reference
PLL
Oscillator
AVDD 3.3V CPVDD 3.3V
Digital IO
Digital Core
(^W[, Logic etc)
DVDD (1.8V or 3.3v)
1.8V LDO Clock Halt Detect
LDOO 1.8V
Analog Circuits
Digital Circuits
Power Circuits
Line Driver
Charge Pump
PCM5100A
,
PCM5101A
,
PCM5102A
PCM5100A-Q1
,
PCM5101A-Q1
,
PCM5102A-Q1
SLAS859C –MAY 2012–REVISED MAY 2015
www.ti.com
11 Power Supply Recommendations
11.1 Power Supply Distribution and Requirements
The PCM510xA devices are powered through the following pins:
Figure 35. Power Distribution Tree within PCM510xA
Table 12. Power Supply Pin Descriptions
NAME USAGE / DESCRIPTION
AVDD Analog voltage supply; must be 3.3 V. This powers all analog circuitry that the DAC runs on.
DVDD Digital voltage supply. This is used as the I/O voltage control and the input to the onchip LDO.
CPVDD Charge Pump Voltage Supply - must be 3.3 V
Output from the onchip LDO. Should be used with a 0.1-µF decoupling cap. Can be driven (used as power
LDOO
input) with a 1.8-V supply to bypass the onchip LDO for lower power consumption.
AGND Analog ground
DGND Digital ground
11.2 Recommended Powerdown Sequence
Under certain conditions, the PCM510xA devices can exhibit some pop on power down. Pops are caused by a
device not having enough time to detect power loss and start the muting process.
The PCM510xA devices have two auto-mute functions to mute the device upon power loss (intentional or
unintentional).
XSMT = 0
When the XSMT pin is pulled low, the incoming PCM data is attenuated to 0, closely followed by a hard analog
mute. This process takes 150 sample times (t
s
) + 0.2 ms.
Because this mute time is mainly dominated by the sampling frequency, systems sampling at 192 kHz will mute
much faster than a 48-kHz system.
Clock Error Detect
When clock error is detected on the incoming data clock, the PCM510xA devices switch to an internal oscillator,
and continue to the drive the output, while attenuating the data from the last known value. Once this process is
complete, the PCM510xA outputs are hard muted to ground.
11.2.1 Planned Shutdown
These auto-muting processes can be manipulated by system designs to mute before power loss in the following
ways:
1. Assert XSMT low 150 t
S
+ 0.2 ms before power is removed.
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Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1