Datasheet

PCM5100A , PCM5101A , PCM5102A
PCM5100A-Q1 , PCM5101A-Q1 , PCM5102A-Q1
www.ti.com SLAS859C –MAY 2012–REVISED MAY 2015
9.3.5.3 Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM)
The system clock PLL mode allows designers to use a simple 3-wire I
2
S audio source. The 3-wire source
reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency
electromagnetic interference.
The internal PLL is disabled as soon as an external SCK is supplied.
The device starts up expecting an external SCK input, but if BCK and LRCK start correctly while SCK remains at
ground level for 16 successive LRCK periods, then the internal PLL starts, automatically generating an internal
SCK from the BCK reference. Specific BCK rates are required to generate an appropriate master clock. Table 11
describes the minimum and maximum BCK per LRCK for the integrated PLL to automatically generate an
internal SCK.
Table 11. BCK Rates (MHz) by LRCK Sample Rate for
PCM510xA PLL Operation
BCK (f
S
)
Sample f (kHz) 32 64
8 – –
16 – 1.024
32 1.024 2.048
44.1 1.4112 2.8224
48 1.536 3.072
96 3.072 6.144
192 6.144 12.288
384 12.288 24.576
9.4 Device Functional Modes
9.4.1 External SCK and PLL Activation
As discussed in Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM), the internal PLL of
a PCM510xA device supplies a SCK if an external SCK is not present at powerup.
9.4.1.1 Interpolation Filter Modes
Interpolation-filter options are controlled by the FLT pin. See Table 3.
9.4.1.2 44.1kHz De-emphasis
De-emphasis control for 44.1-kHz f
S
is controlled by the DEMP pin. See Pin Configuration and Functions.
9.4.1.3 Audio Format
Audio format is selected by the FMT pin. See Pin Configuration and Functions.
Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1