Sample & Buy Product Folder Support & Community Tools & Software Technical Documents PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 PCM510xA 2.1 VRMS, 112/106/100 dB Audio Stereo DAC with PLL and 32-bit, 384 kHz PCM Interface 1 Features • • 1 • • • • • • • • • • • Ultra Low Out-of-Band Noise Integrated High-Performance Audio PLL with BCK Reference to Generate SCK Internally Direct Line Level 2.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 8 Features .................................................................. Applications ........................................................... Description ............................................................. Simplified System Diagram .................................. Revision History.....................................................
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 • Clarified clock generation explanation.................................................................................................................................. 24 • Clarified external SCK discussion. .......................................................................................................................................
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 6 Device Comparison Differences Between PCM510xA Devices PART NUMBER DYNAMIC RANGE SNR THD PCM5102A 112dB 112dB –93 dB PCM5101A 106 dB 106 dB –92 dB PCM5100A 100 dB 100 dB –90 dB Typical Performance (3.3 V Power Supply) PARAMETER SNR 112 / 106 / 100 dB Dynamic range 112 /106 / 100 dB THD+N at –1 dBFS –93/ –92 / –90 dB Full-scale single-ended output 2.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 7 Pin Configuration and Functions PW 20-Pin Package (Top View) Pin Functions PIN TYPE DESCRIPTION NAME NO. AGND 9 — Analog ground AVDD 8 P Analog power supply, 3.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) Supply voltage Digital input voltage MIN MAX AVDD, CPVDD, DVDD –0.3 3.9 LDO with DVDD at 1.8 V –0.3 2.25 DVDD at 1.8 V –0.3 2.25 DVDD at 3.3 V –0.3 3.9 UNIT V Analog input voltage –0.3 3.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 8.5 Electrical Characteristics Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 Electrical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Electrical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C. All devices in the family are characterized with AVDD = CPVDD = DVD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 8.6 Timing Requirements Figure 1 shows the timing requirements for the system clock input. For optimal performance, use a clock source with low phase jitter and noise. MIN tSCY System clock pulse cycle time tSCKH System clock pulse width, High tSCKL System clock pulse width, Low TYP 20 DVDD = 1.8 V 8 DVDD = 3.3 V 9 DVDD = 1.8 V 8 DVDD = 3.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 8.8 Typical Characteristics 10 10 -10 -10 -30 -30 THD+N (dB) THD+N (dB) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 Typical Characteristics (continued) Q1 Automotive grade devices are specified for TA = –40°C to 125°C. Consumer grade (non-Q1) devices are specified at TA = 25°C, AVDD = CPVDD = DVDD = 3.3 V, fS = 48 kHz, system clock = 512 fS and 24-bit data unless otherwise noted.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 9 Detailed Description 9.1 Overview The integrated PLL on the device provided adds the flexibility to remove the system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI. Powersense undervoltage protection utilizes a two-level mute system.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 Feature Description (continued) Table 2.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 1tS LRCK L- channel R- channel BCK Audio data word = 16-bit, BCK = 32, 48, 64fS 1 2 15 16 1 2 15 16 DATA MSB LSB MSB LSB Audio data word = 24-bit, BCK = 48, 64fS 1 2 23 1 24 2 23 24 DATA MSB LSB MSB LSB Audio data word = 32-bit, BCK = 64fS 1 2 31 32 1 2 31 32 DATA MSB LSB MSB LSB I2S Data Format; L-channel = LOW, R-channel = HIGH Figure 14.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 9.3.4 Audio Processing 9.3.4.1 Interpolation Filter The PCM510xA provides two types of interpolation filter. Users can select which filter to use by using the FLT pin (pin 11). Table 3.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 0.05 0.04 0.03 Amplitude (dB) 0.02 0.01 0.00 −0.01 −0.02 −0.03 −0.04 −0.05 0.0 0.1 0.2 0.3 Frequency (x fS) 0.4 0.5 G034 Figure 17.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 The normal x4 / x2 / x1 (bypass) interpolation filter is programmed for sample rates from 8 kHz to 384 kHz. Table 5. Normal x4 Interpolation Filter Parameter Condition Filter gain pass band 0 ……. 0.45fS Value (Typ) Filter gain stop band 0.55fS ….. 7.455fS Filter group delay Value (Max) Units ±0.02 dB –60 dB 22tS s 1.0 0 0.8 −20 0.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Table 6. Normal x2 Interpolation Filter Parameter Condition Filter gain pass band 0 ……. 0.45fS Value (Typ) Filter gain stop band 0.55fS ….. 7.455fS Filter group delay Value (Max) Units ±0.02 dB –60 dB 22tS s 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 −0.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 The low-latency x8 / x4 / x2 / x1 (bypass) interpolation filter is programmed for sample rates from 8 kHz to 384 kHz. Table 7. Low Latency x8 Interpolation Filter Parameter Condition Filter gain pass band 0 ……. 0.45fS Filter gain stop band 0.55fS ….. 7.455fS Value (Typ) Units ±0.0001 dB –52 dB 3.5tS s Filter group delay 1.0 0 0.8 −20 0.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Table 8. Low Latency x4 Interpolation Filter Parameter Condition Filter gain pass band 0 ……. 0.45fS Filter gain stop band 0.55fS ….. 3.455fS Value (Typ) Units ±0.0001 dB –52 dB 3.5tS s Filter group delay 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 0.0 −80 −0.2 −100 −0.4 −120 0 1 2 Frequency (x fS) 3 −0.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 Table 9. Low Latency x2 Interpolation Filter Parameter Condition Filter gain pass band 0 ……. 0.45fS Filter gain stop band 0.55fS ….. 1.455fS Filter group delay Value (Typ) Units ±0.0001 dB –52 dB 3.5tS s space 1.0 0 0.8 −20 0.6 Amplitude (FFS) Amplitude (dB) −40 −60 0.4 0.2 −80 0.0 −100 −120 −0.2 0 1 2 Frequency (x fS) 3 −0.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 9.3.5 Reset and System Clock Functions 9.3.5.1 Clocking Overview The PCM510xA devices have flexible systems for clocking. Internally, the device requires a number of clocks, mostly at related clock rates to function correctly. All of these clocks can be derived from the serial audio interface in one form or another. The data flows at the sample rate (fS).
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 9.3.5.3 Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM) The system clock PLL mode allows designers to use a simple 3-wire I2S audio source. The 3-wire source reduces the need for a high frequency SCK, making PCB layout easier, and reduces high frequency electromagnetic interference. The internal PLL is disabled as soon as an external SCK is supplied.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 10 Applications and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 10.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 Application Information (continued) 10.1.1.3 Application Curve -20 -40 Amplitude (dB) -60 -80 -100 -120 -140 -160 0 5 10 Frequency (kHz) 15 20 Figure 34.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 11 Power Supply Recommendations 11.1 Power Supply Distribution and Requirements The PCM510xA devices are powered through the following pins: AVDD 3.3V CPVDD 3.3V DAC Charge Pump Reference Oscillator DVDD (1.8V or 3.3v) LDOO 1.8V Digital Core ( ^W[, Logic etc) Digital IO Analog Circuits 1.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 Recommended Powerdown Sequence (continued) 3.3V VDD 0V 150tS + 0.2ms High XSMT Low High I2 S Clocks SCK, BCK, LRCK Low Time Figure 36. Assert XSMT 2. Stop I2S clocks (SCK, BCK, LRCK) 3 ms before powerdown as shown in Figure 37. 3.3V VDD 0V High XSMT Low 3 ms High I2S Clocks SCK, BCK, LRCK Low Time Figure 37. Stop I2C Clocks 11.2.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com Recommended Powerdown Sequence (continued) MCU GPIO “mute” signal GND XSMT Linear Regulator 110V / 220V SMPS 6V PCM5xxx Audio DAC 3.3V 10 F GND GND Figure 38. Using the XSMT Pin 11.3 External Power Sense Undervoltage Protection Mode NOTE External Power Sense Undervoltage Protection Mode is supported only when DVDD = 3.3 V.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 External Power Sense Undervoltage Protection Mode (continued) System VDD 12V supply 7.25kW XSMT 2.75kW Figure 39. XSMT in External UVP Mode Digital Attenuation Followed by Analog Mute 0.9 * DVDD 2.0 V Analog Mute XSMT 1.2 V 0.1 * DVDD tf Figure 40. XSMT Timing for Undervoltage Protection The trigger voltage values for the soft mute and hard mute are shown in Table 13.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 11.4 Power-On Reset Function Power-On Reset, DVDD 3.3-V Supply The PCM510xA includes a power-on reset function shown in Figure 41. With VDD > 2.8 V, the power-on reset function is enabled. After the initialization period, the PCM510xA is set to its default reset state.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 11.5 PCM510xA Power Modes 11.5.1 Setting Digital Power Supplies and I/O Voltage Rails The internal digital core of the PCM510xA devices run from a 1.8-V supply. This can be generated by the internal LDO, or by an external 1.8-V supply. DVDD is used to set the I/O voltage, and to be used as the input to the onchip LDO that creates the 1.8 V required by the digital core.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 SLAS859C – MAY 2012 – REVISED MAY 2015 www.ti.com 12 Layout 12.1 Layout Guidelines • • • • The PCM510xA family of devices are simple to layout. Most engineers use a shared common ground for an entire device. GND can be consider AGND and DGND connected. Good system partitioning should keep digital clock and interface traces away from the analog outputs for highest analog performance.
PCM5100A, PCM5101A, PCM5102A PCM5100A-Q1, PCM5101A-Q1, PCM5102A-Q1 www.ti.com SLAS859C – MAY 2012 – REVISED MAY 2015 13 Device and Documentation Support 13.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 14.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 7-May-2015 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PCM5100APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCM5100AQPWRQ1 TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 PCM5101APWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 6-May-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM5100APWR TSSOP PW 20 2000 367.0 367.0 38.0 PCM5100AQPWRQ1 TSSOP PW 20 2000 367.0 367.0 38.0 PCM5101APWR TSSOP PW 20 2000 367.0 367.0 38.0 PCM5101AQPWRQ1 TSSOP PW 20 2000 367.0 367.0 38.0 PCM5102APWR TSSOP PW 20 2000 367.0 367.0 38.0 PCM5102AQPWRQ1 TSSOP PW 20 2000 367.0 367.0 38.
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