Service manual

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To contact Mallinckrodt, Inc. representative: in the United States, call 1-800-635-5267:

outside of the United States, call your local Mallinckrodt representative.

Caution: Federal law (U.S.A.) restricts this device to sale by or on the order of a physician.

SERVICE MANUAL

NPB-4000/4000C

Patient Monitor

Summary of content (219 pages)

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SERVICE MANUAL NPB-4000/4000C Patient Monitor To contact Mallinckrodt, Inc. representative: in the United States, call 1-800-635-5267: outside of the United States, call your local Mallinckrodt representative. Caution: Federal law (U.S.A.) restricts this device to sale by or on the order of a physician. ©2000 Mallinckrodt Inc.
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Mallinckrodt Inc. 675 McDonnell Boulevard P.O. Box 5980 St. Louis, MO 63134 Telephone 314.654.2000 Toll Free 1.800.635.5267 Mallinckrodt Europe BV Hambakenwettering 1 5231 DD’s-Hertogenbosch The Netherlands Telephone +31.73.6485200 Nellcor Puritan Bennett Inc. 4280 Hacienda Drive Pleasanton, CA 94588 To obtain information about a warranty, if any, for this product, contact Mallinckrodt Technical Services or your local Mallinckrodt representative. Nellcor Puritan Bennett Inc.
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TABLE OF CONTENTS List of Figures List of Tables List of Figures.............................................................................................. vi List of Tables ............................................................................................... viii Section 1: Introduction ............................................................................... 1-1 1.1 Manual Overview........................................................................ 1-1 1.
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Contents Section 10: Introduction and System Description .................................. 10-1 10.1 System Overview ..................................................................... 10-1 10.2 System Block Diagram............................................................. 10-1 10.3 ECG Processing....................................................................... 10-5 10.4 Respiration Processing ............................................................ 10-6 10.5 NIBP Processing ...............
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Contents 14.11 Knob Interface Control ........................................................... 14-17 14.12 Push Button Control ............................................................... 14-17 14.13 Miscellaneous Control - CS5#................................................ 14-17 14.14 Speaker .................................................................................. 14-20 14.15 NIBP (Non Invasive Blood Pressure) Control......................... 14-20 14.16 Front End Interface..............
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Contents LIST OF FIGURES Figure 6-1: NPB-4000/C Disassembly Sequence Flow Chart, Sheet 1 .............6-3 Figure 6-2: NPB-4000/C Disassembly Sequence Flow Chart, Sheet 2 .............6-4 Figure 7-1: NPB-4000/C Top Assembly Drawing...............................................7-2 Figure 7-2: NPB-4000/C Front Case Assembly Diagram (Sheet 1 of 2)............7-4 Figure 7-3: NPB-4000/C Front Case Assembly Diagram (Sheet 2 of 2)............7-6 Figure 7-4: NPB-4000/C Rear Case Assembly Diagram (Sheet 1 of 2) ...
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Contents Figure 16-1: Figure 16-2: Figure 16-3: Figure 16-4: Figure 16-5: Figure 17-1: Figure 17-2: Figure 17-3: Figure 17-4: Figure 17-5: Figure 17-6: Figure 17-7: Figure 17-8: Figure 17-9: Preamplifier and PGA Outputs ....................................................16-9 Filter Outputs and ADC Input.....................................................16-10 MP-205 with an SRC-2 Filter Output .........................................16-11 MP-205 with an SRC-2 LED Drive Current Test at TP7 ............
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Contents LIST OF TABLES Table 3-1: Table 3-2: Table 3-3: Table 3-4: Table 3-5: Table 3-6: Table 3-7: Required Test Equipment…………………………………. 3-1 Dynamic Operating Range………………………………… 3-7 Serial Port Voltage…………………………………………. 3-16 Earth Leakage Current Values……………………………. 3-18 Enclosure Leakage Current……………………………….. 3-19 Patient Leakage Current Values………………………….. 3-20 Patient Leakage Current Values – Mains Voltage on Applied Part……………………………………………..
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SECTION 1: INTRODUCTION 1.1 1.2 1.3 1.4 Manual Overview Warnings, Cautions, and Notes NPB-4000/C Patient Monitor Description Related Documents 1. INTRODUCTION 1.1 MANUAL OVERVIEW This manual contains information for servicing the model NPB-4000 and NPB-4000C patient monitor, subsequently referred to as NPB-4000/C throughout this manual. Only qualified service personnel should service this product.
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Section 1: Introduction 1.4 RELATED DOCUMENTS To perform test and troubleshooting procedures and to understand the principles of operation and circuit analysis sections of this manual, you must know how to operate the monitor. Refer to the NPB-4000/C operator’s manual. To understand the various Nellcor sensors, ECG leads, blood pressure cuffs, and temperature probes that work with the monitor, refer to the individual directions for use that accompany these accessories.
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SECTION 2: ROUTINE MAINTENANCE 2.1 2.2 2.3 2.4 Cleaning Periodic Safety and Functional Checks Batteries Environmental Protection 2. ROUTINE MAINTENANCE 2.1 CLEANING WARNING: Do not immerse the NPB-4000/C or its accessories in liquid or clean with caustic or abrasive cleaners. Do not spray or pour any liquid on the monitor or its accessories. To clean the NPB-4000/C, dampen a cloth with a commercial, nonabrasive cleaner and wipe the exterior surfaces lightly.
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Section 2: Routine Maintenance 2.3 BATTERIES If the NPB-4000/C has not been used for a long period of time, the battery will need charging. To charge the battery, connect the NPB-4000/C to an AC outlet or external DC supply as described in Paragraph 3.3.1 in this service manual or the Setup and Use section of the operator’s manual. Note: Storing the NBP-4000/C for a long period without charging the battery may degrade the battery capacity. A complete battery recharge requires 8 hours.
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SECTION 3: PERFORMANCE VERIFICATION 3.1 3.2 3.3 3.4 Introduction Equipment Needed Performance Tests Safety Tests 3. PERFORMANCE VERIFICATION 3.1 INTRODUCTION This section discusses the tests used to verify performance following repairs or during routine maintenance. All tests can be performed without removing the NPB-4000/C covers. If the NPB-4000/C fails to perform as specified in any test, repairs must correct the problem before the monitor is returned to the user. 3.
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Section 3: Performance Verification 3.3 PERFORMANCE TESTS The battery charge and battery performance test should be performed before monitor repairs whenever the battery is suspected as being a source of the problems. All other tests may be used following repairs or during routine maintenance (if required by your local institution. Before performing the battery performance test, ensure that the battery is fully charged (Paragraph 3.3.1). This section is written using Nellcor factory-set power-up defaults.
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Section 3: Performance Verification 5. Set NIBP simulator to simulate pressure setting of 120/80 mmHg and heart rate of 80 bpm. 6. Ensure monitor is not connected to AC power. 7. With NPB-4000/C turned off, press On/Standby switch and verify battery icon appears at bottom of display after power-on self-test is completed. Boxes in battery icon should all be filled, indicating battery is charged. 8. Verify monitor is responding to SpO2 simulator signal and audible alarm is sounding.
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Section 3: Performance Verification Note: The upper version number corresponds to the boot software, the lower version number corresponds to the operational software. Note: Power-on self-test takes approximately 10 seconds to complete. d. A beep signals end of power-on self-test e. Upon successful completion of power-on self-test, display will be in normal monitoring screen configuration. Note: No vital signs numeric values or waveforms will be displayed. 3.3.
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Section 3: Performance Verification 2. Set SRC-2 as follows: SWITCH RATE LIGHT MODULATION RCAL/MODE POSITION 38 LOW OFF RCAL 63/LOCAL 3. Press monitor On/Standby switch to turn monitor on. 4. After normal power-up sequence, verify SpO2% display initially indicates zero. Note: The pulse bar may occasionally indicate a step change as the monitor is in the pulse search mode. 5. Move modulation switch on SRC-2 to LOW. 6. Verify following monitor reaction: a.
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Section 3: Performance Verification 6. Verify the following: a. An audible alarm remains silenced. b. “Slashed bell” icon appears in each numeric frame on display. c. SpO2% and HEART RATE displays continue flashing. d. Heart rate tone is audible. e. Audible alarm returns in approximately 60 seconds. 3.3.4.1.2 Heart Rate Tone Volume Control 1. Set up NPB-4000/C monitor and SRC-2 pulse oximeter tester as indicated in paragraph 3.3.4.1.1. 2.
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Section 3: Performance Verification Note: A “*” indicates values that produce an alarm. Press the Alarm Silence switch to temporarily silence the audible alarm.
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Section 3: Performance Verification 3.3.4.2 Operation with an ECG Simulator 1. With monitor off, connect ECG leads to appropriate jacks on ECG tester. 2. Connect leads to CE-10 ECG cable. 3. Connect CE-10 to ECG input port on NPB-4000/C. 4. Set ECG tester as follows: Heart rate: 30 bpm Amplitude: 1 millivolt Lead select: II Normal sinus rhythm Adult mode Note: The accuracy of NPB-4000/C ECG measurements is ±5 bpm.
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Section 3: Performance Verification 14. Disconnect LL lead from ECG simulator. 15. Verify “Leads Off” alarm message appears, three dashes are displayed in HEART RATE display, and low priority audible alarm sounds. 16. Reconnect LL lead to ECG simulator. Verify “Leads Off” alarm message no longer appears and audible alarm is silenced. 17. Repeat steps 14 through 16 for LA and RA leads. 18. Turn monitor off. 3.3.4.3 Operation with a Respiration Simulator 1.
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Section 3: Performance Verification 3.3.4.4 Verification of Pneumatic System Tests in paragraphs 3.3.4.4.1 through 3.3.4.4.5 verify the functionality of the NPB-4000/C pneumatic system. These tests are designed to use the Bio-Tek “BP Pump” noninvasive blood pressure simulator. The internal test volume of the Bio-Tek simulator is 250 cm3 , which is used to calculated the inflation/deflation rate periods. The Bio-Tek simulator or any equivalent NIBP simulator is required to perform these tests.
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Section 3: Performance Verification 6. Press Select button on simulator until simulator displays “Pressure Source Set Test Pressure”. 7. Use Up/Down buttons on simulator to adjust for 250 mmHg. 8. Press Start Pump button on simulator. The simulator will begin to pressurize. Note: The current pressure in mmHg will be displayed on both the simulator and NPB-4000/C displays. 9. Allow 15-20 seconds for pressure to stabilize.
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Section 3: Performance Verification 7. Allow 15-20 seconds for pressure to stabilize. 8. Record pressure displayed on NPB-4000/C. 9. Initiate a 1-minute timer. 10. After 1 minute, record pressure displayed on NPB-4000/C. Note: The test will have been successfully completed if the pressure has dropped by 6 mmHg, or less, during the 1-minute period. 11. Press and hold Heart Rate Tone Volume switch until NPB-4000/C displays a pressure of 0 mmHg. Note: Additional NIBP tests may be performed at this time.
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Section 3: Performance Verification Note: Additional NIBP tests may be performed at this time. If no further NIBP tests are to be conducted, turn the NPB-4000/C off. Normal monitoring operation will return the next time the monitor is turned on. 3.3.4.4.4 Deflation Rate The deflation rate test verifies the deflation rate of the NPB-4000/C. A timer/stop watch is required for this test. 1. Ensure Bio-Tek simulator is in test mode. The simulator should display “Pressure Gauge”. 2.
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Section 3: Performance Verification 3.3.4.4.5 Over-pressure The over-pressure test verifies the functionality of the over-pressure relief system of the NPB-4000/C. 1. Ensure Bio-Tek simulator is in test mode. The simulator should display “Pressure Gauge”. 2. Ensure simulator is set up for internal cuff. 3. Ensure NIBP Test screen is active on NPB-4000/C. 4. Press Heart Rate Tone Volume switch on NPB-4000/C to ensure both valves are closed. 5.
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Section 3: Performance Verification Note: The accuracy of NPB-4000/C temperature measurements is ±0.1ø C (±0.2øF). In the procedure below, add the tolerance of the simulator to the acceptable range of readings. 4. Press On/Standby switch to turn monitor on. 5. After normal power-up sequence, verify temperature reads 37ø ±0.1ø C (98.6øF ±0.2øF if Fahrenheit is selected as temperature units.) 6. Turn monitor off. 3.3.4.
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Section 3: Performance Verification 14. Verify that blood pressure values are reasonable for subject. 3.3.4.6.2 Serial Interface Test Perform the following procedure to test the serial port voltages. The test is qualitative and will only verify that the serial interface port is powered correctly, and that the “nurse call” signal is operational. The serial connector is a male DB-9, located on the monitor’s rear panel, identified with the RS-232 symbol. 1.
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Section 3: Performance Verification 6. Verify monitor is responding to SpO2 simulator signal and audible alarm is sounding. Note: If desired, press the Alarm Silence switch to temporarily silence the audible alarm. 7. Connect DMM positive lead to pin 9 and verify voltage value listed in Table 3-3. (Voltage for pin 9 will be that listed for the “alarm underway” condition.) 3.
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Section 3: Performance Verification 3.4.2.1 Earth Leakage Current This test is in compliance with IEC 601-1 (earth Leakage current) and AAMI Standard ES1 (earth risk current). The applied voltage for AAMI ES1 is 120 Volts AC, 60 Hz, for IEC 601-1 the voltage is 264 Volts AC, 50 to 60 Hz. All measurements shall be made with the power switch in both “On” and “Off” positions. 1. Connect the monitor AC plug to the electrical safety analyzer as recommended by the analyzer operating instructions. 2.
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Section 3: Performance Verification Table 3-5: Enclosure Leakage Current AC Line Cord Closed Closed Closed Open Open Open Neutral Line Wire Closed Closed Open Closed Open Closed Power Line Ground Wire IEC 601-1 AAMI/ANSI ES1 Standard Closed Open Closed Closed Closed Open 100 µA 500 µA 500 µA 500 µA 500 µA 500 µA 100 µA 300 µA 300 µA 100 µA 300 µA 300 µA 3.4.2.
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Section 3: Performance Verification Table 3-6: Patient Leakage Current Values Test Condition Allowable Leakage Current (microamps) Normal polarity 10 Normal polarity; Neutral (L2) open 50 Normal polarity; Earth open 50 Reverse polarity 10 Reverse polarity; Neutral (L2) open 50 Reverse polarity; Earth open 50 3.4.2.4 Patient Leakage Current - (Mains Voltage on the Applied Part) This test measures patient leakage current in accordance with IEC 601-1, clause 19, for Class I, type CF equipment.
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Section 3: Performance Verification Table 3-7: Patient Leakage Current Values— Mains Voltage on Applied Part Test Condition 3.4.2.5 Allowable Leakage Current (microamps) Normal polarity 50 Reverse polarity 50 Patient Auxiliary Current This test measures patient auxiliary current in accordance with IEC 601-1, clause 19, for Class 1, type CF equipment. The applied voltage for AAMI ESI is 120 volts, 60 Hz, and for IEC 601-1 the voltage is 264 volts, 50 to 60 Hz.
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Section 3: Performance Verification Table 3-9: Allowable Leakage Current Polarity 3-22 Neutral Line Wire (L2) Power Line Ground Wire Allowable Leakage Current (microamps) Normal Closed Normal 10 Normal Open Normal 50 Normal Closed Open 50 Reversed Closed Normal 10 Reversed Open Normal 50 Reversed Closed Open 50
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SECTION 4: POWER-UP DEFAULTS MENU AND DIAGNOSTIC MODE 4.1 4.2 4.3 Introduction Power-up Defaults Menu Diagnostic Mode 4. POWER-UP DEFAULTS MENU AND DIAGNOSTIC MODE 4.1 INTRODUCTION This section discusses use of the Power-up Defaults Menu to configure power-on default settings, and the Diagnostic Mode to obtain service-related information about the monitor. 4.
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Section 4: Power-up Defaults Menu and Diagnostic Mode Table 4-1: Power-up Defaults Menu MENU ITEM Accept Current Settings as Power-Up Defaults? CHOICES “Yes” “No” Adult/Neonatal Mode “Make Available” Alarm Suspend “Make Available” “Deny Access” “Deny Access” “Make Available” “Deny Access” 4-2 If “Yes” is chosen, the current NPB-4000/C settings become the power-up defaults.
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Section 4: Power-up Defaults Menu and Diagnostic Mode Table 4-1: Power-up Defaults Menu MENU ITEM Language Enter Diagnostic Mode CHOICES “English” “French” “German” “Spanish” “Italian” “Portuguese” “Japanese” “Russian” “Chinese” The language selected will be used for all the text shown on the display; the selected language will be effective the next time the monitor is powered up. “Yes” If “Yes” is chosen, the Power-up Defaults Menu is exited and the Diagnostic Menu appears.
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Section 4: Power-up Defaults Menu and Diagnostic Mode The Diagnostic Menu lists the test and system-related information screens. Selection of an item in the menu will invoke that test or information screen. The test and information screens that appear in the Diagnostic Menu are as follows: • Error Codes • System Information • System A/D Values • NIBP Test 4.3.1 Error Codes This screen displays the 10 most recent error codes logged by the NPB-4000/C.
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Section 4: Power-up Defaults Menu and Diagnostic Mode • System Software Version: Displays the revision level of the system software. The revision level is also momentarily shown on the LCD as part of the Copyright screen. This value may not be changed by the user. • SpO2 Software Version: Displays the revision level of the software of the MP-205 SpO2 module. This value may not be changed by the user. When in the System Information screen, the knob may be rotated to select any of the “changeable” items.
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Section 4: Power-up Defaults Menu and Diagnostic Mode 4.3.4 NIPB Test An NIBP Test screen is provided to facilitate troubleshooting problems and performing verification testing for the NIBP subsystem. Typically, when these tests are performed, the pneumatic system is connected to an external pressurereading device and a closed reference volume.
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SECTION 5: TROUBLESHOOTING 5.1 5.2 5.3 5.4 5.5 5.6 Introduction How to Use this Section Who Should Perform Repairs Replacement Level Supported Obtaining Replacement Parts Troubleshooting Guide 5. TROUBLESHOOTING 5.1 INTRODUCTION This section explains how to troubleshoot the NPB-4000/C if problems arise. Tables are supplied that list possible monitor difficulties, along with probable causes, and recommended actions to correct the difficulty. 5.
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Section 5: Troubleshooting 5.6 TROUBLESHOOTING GUIDE Problems with the NPB-4000/C are separated into the categories indicated in Table 5-1. Refer to the paragraph indicated for further troubleshooting instructions. Note: Taking the recommended actions discussed in this section will correct the majority of problems you will encounter. However, problems not covered here can be resolved by calling Mallinckrodt Technical Services or your local Mallinckrodt representative.
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Section 5: Troubleshooting 5.6.1 Power Table 5-2 lists recommended actions to address power problems. Table 5-2: Power Problems Condition Recommended Action 1. The NPB-4000/C fails to power-up when the On/Standby switch is pressed. 1. Ensure power cord is plugged into operational AC outlet of appropriate voltage and frequency. Ensure green BATTERY CHARGING/AC SOURCE indicator is lit. If indicator is not lit, replace power supply assembly. 2.
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Section 5: Troubleshooting 5.6.2.1 Serviceable Hardware Error Codes Listed in Error! Reference source not found. are error codes that correspond to hardware problems, and the recommended actions to take should such an error be encountered. Table 5-3: Serviceable Hardware Error Codes Hex Code 1 Explanation Improper shutdown. Recommended Action 1. Cycle power. 2. If error persists, return monitor for service. 2 3 4 5 6 7 8 9 5-4 NIBP Sensor Error. • The two pressure transducers do not agree.
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Section 5: Troubleshooting Table 5-3: Serviceable Hardware Error Codes Hex Code A B C 64 Explanation Recommended Action Measured value of isolated reference supply on front end was low 1. Check power supply. On a NPB-4000 rev 4 PCB or earlier. The measured value of isolated reference supply on front end was high. On a NPB-4000 rev 5 or later, or on NPB-4000C. The measured value of isolated reference supply on front end was high. MP-205 SpO2 module is not sending messages to host CPU. 1.
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Section 5: Troubleshooting 4. If Error Code screen indicates same error has occurred previously, take monitor out of service and contact Mallinckrodt Technical Services or your local Mallinckrodt representative for advice on remedial action. 5. If Error Code screen indicates no previous occurrences of this error, monitor may be returned to service. As a reference, Table 5-4 lists the general categories for other error codes.
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Section 5: Troubleshooting Table 5-5: Switches/Knob Problems Condition Recommended Action 1. NPB-4000/C fails to power-up when On/Standby switch is pressed. 1. Take steps as noted in paragraph 5.6.1. 2. NPB-4000/C powersup, but some or one of the other switches respond. 1. Ensure keypad is plugged into Main PCB. If connection is good, change keypad. 2. If problem persists, change Main PCB. 3. When knob is rotated, 1. Ensure encoder cable is plugged into Main PCB.
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Section 5: Troubleshooting 5.6.4 Display/Audible Tones Table 5-6 lists recommended actions to address problems with the display and audible tones. Table 5-6: Display/Audible Tones Problems Condition 1. System powers-up and… • LCD screen is totally black or white. Or, • LCD screen is illuminated, but no data is visible. Or, • LCD screen has data, but is not illuminated.
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Section 5: Troubleshooting Table 5-6: Display/Audible Tones Problems Condition 3. Audible alarm does not sound. Recommended Action 1. Verify alarm volume setting in Alarm/Limits menu, and test operation of alarm tone by pressing Heart Rate Tone Volume switch while alarm volume setting is displayed. 2. Ensure speaker cable is connected to power supply assembly. 3. If problem persists, replace speaker assembly. 4. If problem persists, replace main PCB. 5.6.
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Section 5: Troubleshooting Table 5-7: Operational Performance Problems Condition 3. 5-10 Printer paper will advance, but paper remains blank when printing should be present. Recommended Action 1. Open printer door and check paper is oriented correctly; paper should exit from bottom of roll. See operator’s manual for an illustration of correct paper orientation. 2. If problem persists, replace printer.
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SECTION 6: DISASSEMBLY GUIDE 6.1 6.2 6.3 6.4 6.5 6.6 Introduction How to Use this Section Disassembly Sequence Flow Charts Closed Case Disassembly Procedures Front Case Disassembly Procedures Rear Case Disassembly Procedures 6. DISASSEMBLY GUIDE WARNING: Performance Verification. Do not place the NPB-4000/C into operation after repair or maintenance has been performed, until all Performance Tests and Safety Tests listed in Section 3 of this service manual have been performed.
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Section 6: Disassembly Guide The ovals on the flow charts contain reference designators that point to specific steps in the Disassembly Procedures. The Disassembly Procedures, paragraphs 6.4, 6.5, and 6.6 contain detailed disassembly instructions, accompanied by illustrations. The rectangular boxes on the flow charts represent the various components or sub-assemblies. The digits appearing in these boxes are the part numbers of the component or subassembly.
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Section 6: Disassembly Guide 6.
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Section 6: Disassembly Guide Figure 6-2: NPB-4000/C Disassembly Sequence Flow Chart, Sheet 2 6.4 CLOSED CASE DISASSEMBLY PROCEDURES This section describes the items that may be removed/replaced without disassembling the main case of the monitor. Step A1 Procedure To remove front panel knob: a) Knob is friction-fit on encoder shaft. Grasp sides of knob firmly and pull straight back from monitor; knob should slip off encoder shaft.
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Section 6: Disassembly Guide Step A2 Procedure To remove carrying handle: a) Use screwdriver to remove two fastening screws and washers. Retain for reassembly. b) Remove handle by sliding it straight back toward rear of monitor. Illustration Step A3 Procedure To remove printer: a) Press Paper Eject button on printer (right side). Door will drop forward. b) Remove paper roll, if installed. Two fastening screws are visible at back panel of printer. c) Use screwdriver to back out captive fastening screws.
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Section 6: Disassembly Guide 6.5 FRONT CASE DISASSEMBLY PROCEDURES This section describes the steps to separate the front and rear case assemblies, and the items that may be removed/replaced on the front case assembly. Step B1 Procedure To separate front and rear case assemblies: a) Remove handle as indicated in step A1. b) Use screwdriver to remove four screws fastening Rear Case Assembly to Front Case Assembly. Retain for reassembly. Illustration Procedure c) Separate two major case assemblies.
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Section 6: Disassembly Guide Procedure d) Disconnect large ribbon-cable connector from main PCB. e) Unscrew NIBP tubing connector from pump to main PCB. Front and rear case assemblies are now completely separable from one another.
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Section 6: Disassembly Guide Step B3 Procedure To remove main PCB: a) Disconnect connectors, from main PCB, for: • • • • • • Switch panel SpO2 ECG/Temp Encoder LCD (display) Backlight Illustration Encoder Tubing Switchpanel NIBP connector connector 6-8 SpO2 cable
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Section 6: Disassembly Guide Procedure b) Use screwdriver to remove six fastening screws around periphery of main PCB. Retain fastening screws for reassembly. c) Lift main PCB slightly and unscrew tubing connector near NIBP front panel fitting. d) Main PCB may now be removed. This allows access to SpO2 front panel connector, NIBP fitting and backlight inverter.
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Section 6: Disassembly Guide 6.6 REAR CASE DISASSEMBLY PROCEDURES This section describes the items that may be removed/replaced on the rear case assembly. First perform the procedure described in step B1 to separate the front and rear case assemblies. Step C1 Procedure To remove battery: a) Use screwdriver to remove three screws holding battery cover plate in place.
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Section 6: Disassembly Guide Procedure b) Grasp strap, accessible through opening in top foam cover, and gently pull battery from its housing. Illustration Procedure c) Remove wire connectors from battery clips. Remember red wire is connected to plus (+) side of battery pack.
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Section 6: Disassembly Guide Step C2 Procedure To remove battery housing: a) Remove battery as described in step C1. Carefully remove two foam battery pads from battery housing. b) If a printer is installed, remove it as described in step A3. c) If a printer is not installed, remove printer blanking cover by slipping small flat-blade screwdriver into one of the slots on the blanking cover. Use screwdriver to gently depress snap-tab on inside of cover, while pulling cover away from monitor.
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Section 6: Disassembly Guide Procedure d) On rear panel of monitor, remove three screws fastening battery housing. e) Carefully slide battery housing from rear case assembly. Illustration Screws fastening battery housing f) Procedure Disconnect speaker twisted-pair-connector from power supply PCB. Speaker is mounted on one side of battery housing. g) If printer had been installed, disconnect ribbon cable from printer PCB.
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Section 6: Disassembly Guide Step C3 Procedure To remove fuses: a) Remove AC power input fuses, as shown, using fuse pullers. Illustration Fuse F1 and F2 Step C4 Procedure To remove power supply assembly: a) On rear panel of monitor, remove eight screws fastening power supply assembly.
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Section 6: Disassembly Guide Procedure b) Carefully lift power supply assembly from rear case.
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SECTION 7: SPARE PARTS 7.1 Introduction 7. SPARE PARTS 7.1 INTRODUCTION Spare parts, along with part numbers, are shown in Table 7-1 through Table 7-7. “Item No.” corresponds to the circled callout numbers in Figure 7-1 through Figure 7-6. The “Step Ref.” corresponds to the disassembly steps described in Section 6.
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Section 7: Spare Parts Figure 7-1: NPB-4000/C Top Assembly Drawing 7-2
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Section 7: Spare Parts Table 7-1: Top Assembly (Figure 7-1) Item No. Description NPB Part No. Step Ref.
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Section 7: Spare Parts Figure 7-2: NPB-4000/C Front Case Assembly Diagram (Sheet 1 of 2) 7-4
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Section 7: Spare Parts Table 7-2: Front Case Assembly (Figure 7-2) Item No. Description NPB Part No. Step Ref. NPB-4000 1 Knob 044727 A1 5 SpO2 module 046085 B2 6 Connector/cable, ECG/temp 047376 B2 7 Encoder 291186 B2 8 PCB, main, Version 3.
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Section 7: Spare Parts Figure 7-3: NPB-4000/C Front Case Assembly Diagram (Sheet 2 of 2) 7-6
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Section 7: Spare Parts Table 7-3: Front Case Assembly (Figure 7-3) Item No. Description NPB Part No. Step Ref.
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Section 7: Spare Parts Figure 7-4: NPB-4000/C Rear Case Assembly Diagram (Sheet 1 of 2) 7-8
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Section 7: Spare Parts Table 7-4: Rear Case Assembly (Figure 7-4) Item No. Description NPB Part No. Step Ref.
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Section 7: Spare Parts Figure 7-5: NPB-4000/C Rear Case Assembly Diagram (Sheet 2 of 2) 7-10
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Section 7: Spare Parts Table 7-5: Rear Case Assembly (Figure 7-5) Item No. Description NPB Part No. Step Ref.
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Section 7: Spare Parts Figure 7-6: NPB-4000/C Power Supply/Heat Sink Assembly Diagram 7-12
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Section 7: Spare Parts Table 7-6: Power Supply Assembly (Figure 7-6) Item No. Description NPB Part No. Step Ref. NPB-4000 22 Fuse, 0.75A, slo-blow, 250V, 5x20 mm 691501 C3 23 PCB, power supply 046074 C4 24 Pump, NIBP 047389 C4 26 Cable, main ribbon 047391 C4 NPB-4000C 22 Fuse, 0.
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SECTION 8: PACKING FOR SHIPMENT 8.1 8.2 8.3 General Instructions Repackaging in Original Carton Repackaging in a Different Carton 8. PACKING FOR SHIPMENT To ship the monitor for any reason, follow the instructions in this section. 8.1 GENERAL INSTRUCTIONS Pack the monitor carefully. Failure to follow the instructions in this section may result in loss or damage not covered by the Mallinckrodt warranty.
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Section 8: Packing for Shipment 8-2 5. Seal the carton with packing tape. 6. Label the carton with the shipping address, return address, and RGA number, if applicable.
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SECTION 9: SPECIFICATIONS 9.1 9.2 9.3 9.4 9.5 9.6 Scope General Electrical Environmental Measuring Parameters Trends 9. SPECIFICATIONS 9.1 SCOPE This section includes specifications for the NPB-4000/C. The instrument is designed to monitor patient vital signs, including: electrocardiogram and heart rate, respiration rate, noninvasive blood pressure, blood oxygen saturation, and temperature.
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Section 9: Specifications Protection Class: Class I, internally powered equipment: per IEC 601-1, clause 2.2.4 Degree of Protection: Type CF: per IEC 601-1, clause 2.2.26 Mode of operation: Continuous Internal Battery: 6V, 8 Ampere-Hours; Type - sealed lead-acid 9.3 ELECTRICAL Battery Operating Time: NPB-4000 4 hours typical @ 25øC, no printing, one NIBP measurement per 15 min. (fully charged battery) NPB-4000C 3 hours typical @ 25øC, no printing, one NIBP measurement per 15 min.
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Section 9: Specifications 9.5 MEASURING PARAMETERS 9.5.1 ECG Measurement/Display Heart Rate Range: 20 BPM - 250 BPM Heart Rate Accuracy: ±5 BPM Bandwidth: Normal Monitoring: 0.5 Hz to 40 Hz Extended Low Frequency Response: 0.05 Hz to 40 Hz Leads: 3 Lead (user selectable) Display Sweep Speeds: 12.5 mm/sec, 25 mm/sec, and 50 mm/sec Pacemaker Detection: Indicator on waveform display, user selectable ECG Size (sensitivity): 0.
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Section 9: Specifications Response to irregular rhythm. 3.1.2.1(e) a) Ventricular bigeminy - 80 BPM b) Slow alternating ventricular bigeminy - 60 BPM c) Rapid alternating ventricular bigeminy 120 BPM d) Bi-directional systoles - 89 to 96 BPM Heart rate meter response time. 3.1.2.1(f) a) Change from 80 to 120 BPM: 4 to 6 sec b) Change from 80 to 40 BPM: 6 to 7 sec Time to alarm for tachycardia. 3.1.2.1(g) Pacemaker pulse rejection. 3.1.4.1, 3.1.4.2 Waveform 4(a) Amplitude 0.5 mV 1 mV 2 mV Avg.
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Section 9: Specifications 9.5.3 NIBP (Noninvasive Blood Pressure) Measurement/Display Note: Systolic and diastolic blood pressure measurements determined with this device are equivalent to those obtained by a trained observer using the cuff/stethoscope auscultation method, within the limits prescribed by the American National Standard, Electronic or automated sphygmomanometers.
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Section 9: Specifications 9.5.5 SpO2 Measurement/Display Range: Pulse Rate: 20 BPM to 250 BPM % Saturation: 0 % to 100% Accuracy: Pulse Rate: ±3 BPM SpO2: 70 % to 100%: ±2 digits 0 % to 69%: Unspecified SpO2 accuracies are expressed as plus or minus “X” digits (saturation percentage points) between saturations of 70–100%. This variation equals plus or minus one standard deviation (1SD), which encompasses 68% of the population.
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SECTION 10: INTRODUCTION AND SYSTEM DESCRIPTION 10.1 10.2 10.3 10.4 10.5 10.6 10.7 System Overview System Block Diagram ECG Processing Respiration Processing NIBP Processing SpO2 Processing Temperature Processing 10. INTRODUCTION AND SYSTEM DESCRIPTION 10.1 SYSTEM OVERVIEW 10.1.1 The Complete NPB-4000/C Patient Monitor System The NPB-4000/C patient monitor is a full-function monitor for use on adult and pediatric patients.
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Section 10: Introduction and System Description Figure 10-1: NPB-4000/C System Block Diagram 10.2.1 Isolated Front End The Isolated Front End section includes all the circuitry to convert ECG, SpO2, and temperature measurements to digital format and to connect this information to the processor. The respiration detection is obtained from two of the three electrodes of the ECG connections.
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Section 10: Introduction and System Description 10.2.4 µP, Memory, and Control The microprocessor (µP), Memory, and Control section contains the system CPU and all digital support circuitry. The latter includes the RAM, nonvolatile memory, and real-time clock. This section also contains the display logic, keypad (switch) interface logic, RS-232 I/O control, defibrillator synchronization control, and printer logic. 10.2.5 Display The display is a cold-cathode, backlighted, fluorescent LCD unit.
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Section 10: Introduction and System Description NPB-4000C. Pressing the Contrast switch changes the background color from white to black or black to white. Operation of the Volume switch accomplishes similar functions for the volume of the heart rate audible tone as the display contrast control switch does for the display. Pressing this switch enables the knob to vary the tone volume. The same timing consideration of 3 seconds is provided, in which to adjust the tone volume or to terminate the action. 10.
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Section 10: Introduction and System Description 10.2.11 Recorder The optional recorder (printer) module is installed in the right panel of the monitor. Refer to the NPB-4000/C monitor operator’s manual for printing procedures. It provides users with the capability to obtain hard-copy records of selected vital signs information. Basic control of the recorder is implemented by two push-switch controls on the recorder front panel.
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Section 10: Introduction and System Description The patient’s respiration is detected by using two of the three leads of the ECG electrodes and cable. A low-level excitation signal is applied to these leads, and the variation of the thoracic impedance caused by the breathing is sensed and processed for display and measurement. 10.5 NIBP PROCESSING The NIBP processing uses an oscillometric technique to provide needed measurements at selected intervals.
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Section 10: Introduction and System Description The NPB-4000/C patient monitor is designed to accept the signals from electrically isolated Series 400 probes manufactured by Yellow Springs Incorporated. Interchangeable probes in this series may be used for esophageal, rectal, skin or surface, or airway temperature measurement. Probes are furnished with a standard 10-feet lead; extension leads are available.
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SECTION 11: ISOLATED FRONT END FUNCTIONS - THEORY OF OPERATION 11.1 Block Diagram 11.2 Overview 11.3 Interface Circuit 11.4 ECG 11.5 Respiratory Circuit 11.6 Temperature Circuit 11.7 Optocouplers 11.8 Controls 11.9 A/D Converter 11.10 Isolated Power Supply 11.11 SpO2 Board 11.12 Isolation 11. ISOLATED FRONT END FUNCTIONS - THEORY OF OPERATION 11.1 BLOCK DIAGRAM See Figure 11-1.
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Section 11: Isolated Front End Functions -- Theory of Operation Figure 11-2: Isolated Front End Block Diagram The NPB-4000/C Front End module is a part of the Main Board. It provides an isolation barrier between a patient’s body and electrical potentials on the rest of the board as well as some high voltage protection of the isolation barrier itself. 11.
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Section 11: Isolated Front End Functions -- Theory of Operation • Isolation is provided by optocouplers. A total of four optocouplers are used for digital signals and a linear optocoupler with a multiplexer is used for all analog signals. The isolated side has its own power supply which generates +5 volts and -5 volts for analog circuitry and +5 volts for digital circuitry. A switching driver and an isolated transformer provide 100 kHz AC-power to the isolated side.
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Section 11: Isolated Front End Functions -- Theory of Operation 11.3 INTERFACE CIRCUIT Figure 11-4: Interface Circuit Block Diagram The interface circuit shown in the highlighted portion of the expanded block diagram, provides physical connection between patient connectors on the unit and preamplifier and other signal conditioning circuitry of the isolated Front End. It also incorporates ESD, defibrillator, and electrosurgery voltage suppression.
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Section 11: Isolated Front End Functions -- Theory of Operation The SpO2 sensor signal is brought through a panel connector and a separate panel cable to the board connectors J101 and J100. The Front End also has an SpO2 output connector J10, into which the SpO2 module (MP-205) is plugged. 11.4 ECG Figure 11-5: ECG Circuit Block Diagram See Figure 11-5.
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Section 11: Isolated Front End Functions -- Theory of Operation The preamplifier is followed by a 0.05 Hz high-pass filter made of capacitor C147 and resistors R248 and R249. The corner frequency can be changed by software to 0.5 Hz, set by resistors R238 and R250 and switch U63B.
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Section 11: Isolated Front End Functions -- Theory of Operation 11.5 RESPIRATORY CIRCUIT Figure 11-6: Respiratory Circuit Block Diagram As shown in the highlighted portion of the expanded block diagram, Figure 11-6, the Respiratory circuitry includes the ECG leads, and some control circuitry. Respiration is detected by measuring modulation of a high frequency AC signal sent to a body. The AC signal is 100 kHz, 4 volts peak square-wave complementary signals are produced by oscillator U81.
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Section 11: Isolated Front End Functions -- Theory of Operation 11.7 OPTOCOUPLERS Figure 11-7: Optocouplers Block Diagram See Figure 11-7. The optical couplers that isolate the Front End signals from the non-isolated digital hardware are of two types: Linear and Digital. 11.7.
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Section 11: Isolated Front End Functions -- Theory of Operation 11.8 CONTROLS Figure 11-8: Controls Block Diagram See Figure 11-8. The isolated control signals are developed and applied in the highlighted blocks as shown in the block diagram. Front end operations are controlled by serial signals on ADCTX line clocked by signals on ADCCLK line. These serial signals from the Main Board CPU are fed to the Front End through opto-isolators U55 and U56 with pull-ups R182 and R173.
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Section 11: Isolated Front End Functions -- Theory of Operation The parity bit is set for odd and is checked in the odd/even parity checker U65. Even parity, if detected, represents an error and the U65 output signal will turn on switch U63A. The switch will drive the output of U60 amplifier beyond the normal range of data signals and will set A/D output at all ones, which will be interpreted as an error.
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Section 11: Isolated Front End Functions -- Theory of Operation bursts. This will provide enough time out for multiplexer control data to be latched. The multiplexer has at least four clock cycles of I/O CLOCK to settle before A/D sampling begins. Data bits are assigned as follows: Input Data Bits Address Bits D7 D6 D5 D4 AIN0 — Isolated data 0 0 0 0 AIN1 — NIBPPSR1 0 0 0 1 AIN2 — NIBPPSR2 0 0 1 0 AIN3 — OSC 0 0 1 1 AIN4 — VBATTAD 0 1 0 0 AIN5 — TEMAD 0 1 0 1 AIN6 — +3.
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Section 11: Isolated Front End Functions -- Theory of Operation 11.10 ISOLATED POWER SUPPLY The isolated power supply consists of high-current switched driver, U54, isolation transformer T1, two full-wave rectifiers with dual diodes D11 and D10, filter capacitors C122 and C127 and three voltage regulators. Regulators U83 and U68 provide +5 volts and -5 volts for analog circuitry and regulator U69 provides +5 volts for digital circuitry on both Front End and SpO2 boards.
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SECTION 12: NIBP - THEORY OF OPERATION 12.1 NIBP System Overview 12.2 The Pneumatic Assembly 12.3 NIBP Hardware 12. NIBP - THEORY OF OPERATION 12.1 NIBP SYSTEM OVERVIEW See Figure 12-1.
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Section 12: NIBP - Theory of Operation Figure 12-2: NIBP System Block Diagram Prior to making blood pressure measurements, the cuff is placed around a limb, typically an upper arm (left or right). The NIBP measurement system is initiated by commands responding to pressing the NIBP Start/Stop switch on the front panel. The cuff is inflated at a rate controlled by the pump excitation current to a pressure above systolic, at which level the artery is effectively occluded.
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Section 12: NIBP - Theory of Operation 12.2 THE PNEUMATIC ASSEMBLY The pneumatic assembly, consisting of the pump, two controlling valves, and tubing to connect the various pneumatic components together are illustrated in the schematic diagram that follows. See Figure 12-4. The pump output is connected to the cuff and to two valves: a two-way proportional control valve (V2) and a three-way valve (V1), as well as to two pressure transducers.
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Section 12: NIBP - Theory of Operation 12.3.1 Pressure Transducers Pressure transducers PS1 and PS2 convert pneumatic pressure levels to voltages in the range from 0.33 volts at 0 mmHg to 4 volts at 300 mmHg. Transducer PS1 is used to sense the main cuff pressure. Transducer PS2 is used as a backup cuff pressure sensor, from which over-pressure warning signals are obtained. Both transducers outputs are smoothed to remove the effects of pumping pulsation.
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Section 12: NIBP - Theory of Operation 12.3.6 NIBP Pump Control Note: The following description is duplicated in the Power Supply section. Reference designations for the two paragraphs that follow are found in power supply schematic drawing, Figure 17-3and Figure 17-4. The power supply mechanical assembly holds the blood pressure pump and shield. The power supply contains circuitry that allows logic level control of the pump power from the processor board.
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SECTION 13: MICROPROCESSOR COMPUTER AND CONTROL – THEORY OF OPERATION 13.1 General 13.2 Power Supply Connections 13.3 NIBP Processing 13.4 Recorder Operation 13.5 Isolated Front End Power Interface 13.6 SpO2 Interface 13.7 Isolated Front End Power Signals 13.8 RS-232 Serial Port Interface 13.9 CPU Connections 13.10 Knob Interface Control 13.11 Push Switch Control 13.12 Digital Schematic Pages 1/2 13.13 Current Drain of Digital Electronics 13. MICROPROCESSOR COMPUTER AND CONTROL –THEORY OF OPERATION 13.
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Section 13: Microprocessor Computer and Control –Theory of Operation The SpO2 unit (MP-205) is connected to an asynchronous serial port via optoisolators. The push switches and rotating knob interface to the 386EX via the FPGA circuit. They are polled by the software at a 200-Hz rate. The speaker is connected to an amplifier circuit, that is connected to a digital potentiometer. The programmable frequency is generated in the FPGA and connects to this programmable digital pot.
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Section 13: Microprocessor Computer and Control –Theory of Operation 13.2.2 Microcontroller Signals The battery and microcontroller have two signals that connect directly with each other, EARLY WARNING and PS OFF. The battery circuits generate an EARLY WARNING signal to the microcontroller that the power is going down within 100 millisecond. This EARLY WARNING signal could be due to the power On/Standby switch being depressed or from the battery voltage getting too low.
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Section 13: Microprocessor Computer and Control –Theory of Operation 13.3 NIBP PROCESSING See Figure 13-2. The NIBP circuits consist of microprocessor control for turning on and off certain signals, control logic generating the pump PWM and valve PWM, and status signals. Figure 13-2: NIBP Processing Circuitry Block Diagram 13.3.
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Section 13: Microprocessor Computer and Control –Theory of Operation of them is buffered by a logic gate that is connected to 5 volts. The inputs to these buffers are TTL-compatible and will switch when the input goes below 0.8 volts or above 2.4 volts. 13.3.5 Analog Power On/Off - Port 1 Bit 1 This signal turns on the power to the NIBP circuits via a regulator run from the battery. To turn on the NIBP circuits, port 1 bit 1 must be set by software to a high state. 13.3.
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Section 13: Microprocessor Computer and Control –Theory of Operation Figure 13-3: Recorder System Block Diagram 13.4.1 Recorder/Microcontroller Interface The recorder is interfaced to the microcontroller via a DUART that has two UARTs programmed by the software. The DUART has a UART0 and a UART1, each with a full UART signal complement. The circuit uses UART1 of the DUART for the recorder interface. This UART has 16-byte fifos on each of the receive and transmit channels.
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Section 13: Microprocessor Computer and Control –Theory of Operation 13.5 ISOLATED FRONT END INTERFACE Figure 13-4: Isolated Front End Block Diagram See Figure 13-4. The interface to the Front End electronics is shown above and consists of using the microprocessor’s synchronous serial unit to interface to the A/D converter. The synchronous serial unit interfaces with the DMA unit, which passes the data to be transmitted to the A/D.
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Section 13: Microprocessor Computer and Control –Theory of Operation 13.5.2 16-Bit Word Transmitted to the A/D Converter and Front End Figure: 13-5: 16 Bit Word 13.5.3 A/D Converter Receiver Control The A/D converter is a pipelined converter and transmits the result of the previous conversion when receiving the next transmission for a conversion. The previous conversion is transmitted to the SSIO unit’s receiver and the SSIO then requests a DMA transfer to memory. 13.5.
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Section 13: Microprocessor Computer and Control –Theory of Operation 13.7 CPU CONNECTIONS The processor in this system is a 386EX. The 386EX contains a 386SX core and integrated peripherals.
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Section 13: Microprocessor Computer and Control –Theory of Operation 13.7.3 Port 3 Bits Port 3 bits used are as follows: 3.2 3.5 3.6 3.7 Defib key input - in PSOFF - out Defib sync pulse - out NIBP PV enable - in 13.7.
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Section 13: Microprocessor Computer and Control –Theory of Operation 13.7.7 Synchronous Serial Port The synchronous serial port is connected to the A/D converter. The signals used are as follows: STXCLK: SRXCLK: SSIOTX: SSIORX: synchronous transmit clock synchronous receive clock synchronous transmit data synchronous receive data The STXCLK signal is generated in the FPGA circuit each time Timer 1 initiates a pulse (1.25 millisecond intervals).
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Section 13: Microprocessor Computer and Control –Theory of Operation 13.7.10 CPU Timing Signals The 386EX runs from a 40 MHz crystal oscillator and the main timing is derived from this clock. It is called CLK2. Inside the CPU, CLK2 is divided by two, generating two new clocks, PH1 and PH2. Each T state is made up of one PH1 and one PH2 clock. There are a minimum of two T states per cycle.
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Section 13: Microprocessor Computer and Control –Theory of Operation 13.8.2 DRAM Timing 25ns 25ns T1 T2W T2 T1 CLK2 RAS# RAS# CASADREN 75ns 50ns 50ns U/LCAS DRAMWR# DRAMOE# 75ns 75ns Figure 13-8: DRAM Timing See Figure 13-8. The DRAM requires 130 nanoseconds total time, read/write and precharge for each cycle. There is one wait state for each DRAM access and a total of three T states, which is 150 nanoseconds.
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Section 13: Microprocessor Computer and Control –Theory of Operation RAS# 70NS ROW/COL ADDR 10NS 10NS VALID ROW 50NS VALID COL 10NS 15NS UCAL/LCAS# 20NS 20NS Figure 13-9: RAS# and CAS# Requirements 13.8.3 DRAM FPGA Circuits The DRAM control circuits in the FPGA must decode the various 386EX control signals and generate the DRAM signals. This is done by using CS6# to set a flip flop when ADS# and PH are true. The flip flop is RAS#.
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Section 13: Microprocessor Computer and Control –Theory of Operation 7FFFF, which is 80000 to FFFFF in bytes. This is the upper portion of the space. The trend flash is assigned to the 32k byte space above the video ram, that is, 84000 to 8FFFF words, or 11000 to 14000 bytes. The software, however, has the ability to overlap the trend flash address with the executable flash address. The design gives priority to the trend flash address over the executable flash.
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Section 13: Microprocessor Computer and Control –Theory of Operation 13.9.2 Flash FPGA Control Circuit The FPGA decodes the boot flash and trend flash select signals and generates the boot flash (FLSH1CE#) signal whenever the trend flash is not being accessed. Since the trend flash address space may overlap the boot flash space, the trend flash has priority. The flash outputs are enabled for a read cycle. During a write cycle, the data bus inputs data to the flash.
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Section 13: Microprocessor Computer and Control –Theory of Operation 13.10.1 LCD Control There are two chip selects assigned to the LCD display chip: one for the control registers inside the chip, and one for the display memory space. The chip itself has a state machine controller inside, and generates the necessary signals to store and retrieve data from the memory when requested. It also takes care of driving the LCD display directly, with the data from the display SRAM.
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Section 13: Microprocessor Computer and Control –Theory of Operation Both read and write transfers between the 386EX and the 1351FLB are defined in the 1351FLB manual, pages 1-33 and 1-34. The timing specifications of the 1351FLB for reading and writing data to and from the control registers or display RAM, allow a direct interface to the 386EX. External control circuits in the FPGA are not necessary, except for one signal, the READY# signal. This is explained in a following section. 13.10.
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Section 13: Microprocessor Computer and Control –Theory of Operation Figure 13-13: Interface Timing 13.12 DUART Control See Figure 13-14. The DUART is a Startech ST16C2550CJ44 which consists of 2 UARTs and fifos for the read and write portions of each UART. Channel 0 is assigned to the RS-232 port, which exits the unit near the AC and DC inputs. Channel 1 is assigned to the recorder. The fifos are 16 bytes deep, and transfer to/from the DUART would save time if done on 8- or 16-byte boundaries.
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Section 13: Microprocessor Computer and Control –Theory of Operation The knob has two channels: channel A and channel B. When clockwise rotation occurs, channel A leads channel B and when counterclockwise rotation occurs, channel B leads channel A. The software monitors the knob flip flop, and when it is set true, the knob has turned. The direction is read by the other bits in the status register, and the software determines the knob direction.
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Section 13: Microprocessor Computer and Control –Theory of Operation The NIBP valve pulse width modulated (NIBPCNTLVLV) signal is generated in the FPGA via this same eight-bit register, which is clocked at 313 kHz. An eight-bit value is loaded into this register, and then the VALVE_PWM_GO bit (bit 1) in the control reg. is set true, and the valve PWM signal begins.
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Section 13: Microprocessor Computer and Control –Theory of Operation Bit 7 resets the A/D converter and is generated when software starts a conversion sequence. 13.15.4 CS5# + A RESET KNOB INT/READ PUSH SWITCHS The I/O address of CS5# + 6 has two functions associated with it. Writing to this register generates a KNOB_INT_RST signal which resets the knob interrupt flip flops. This would be done by software after a knob interrupt occurs.
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Section 13: Microprocessor Computer and Control –Theory of Operation Register CS5# + E has the following bit assignments Bit 0 Not used BIT 1 Not used BIT 2 Not used BIT 3 Not used BIT 4 Not used BIT 5 NURSE CALL BIT 6 PRINTER RESET BIT 7 PRINTER CTS (CLEAR TO SEND) The NURSECALL and PRINTER RESET bits are the flip flop outputs programmed by writing to register CS5# + E as explained above. A 1 (high) indicates that the bit is true, a 0 that the bit is false. 13.
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Section 13: Microprocessor Computer and Control –Theory of Operation Page 2 of the schematics contains the NIBP circuits, the speaker circuits, the LCD contrast circuit, the battery voltage and temperature input circuits, the push-switch interface circuit, and the backlight interface connector circuit. The 50-pin connector connects to the recorder, RS-232 connector, the power supply connector, the defib connector, and the speaker.
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Section 13: Microprocessor Computer and Control –Theory of Operation 13.17 CURRENT DRAIN OF DIGITAL ELECTRONICS The current drain has been determined by using the maximum numbers in the data sheets of the devices. Typically, the devices operate significantly lower. 386EX 130 mA 4M DRAM 95 mA 4M FLASH 30 mA LCD CNTLR 20 mA 256k SRAM 50 mA x2 = 100 mA DUART 3 mA RS232 XCVR 5 mA 256k FLASH 15 mA RTC 15 mA 40MHz osc 9 mA Subtotal = 422 mA misc.
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SECTION 14: MAIN COLOR BOARD DIGITAL THEORY OF OPERATION 14.1 General 14.2 Power Supply Connections 14.3 CPU Connections 14.4 LNA 386EX Connections 14.5 CPU Timing 14.6 Dram Control 14.7 Flash Control 14.8 LCD Display 14.9 Real Time Clock (RTC) 14.10 DUART Control 14.11 Knob Interface Control 14.12 Push Button Control 14.13 Miscellaneous Control - CS5# 14.14 Speaker 14.15 NIBP (Non Invasive Blood Pressure) Control 14.16 Front End Interface 14.17 Digital Schematic 14.18 Block Diagram 14.
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Section 14: Main Color Board Digital Theory of Operation A RTC (real time clock) chip keeps the date and time of day. This unit has 64 bytes of battery backed up ram, 14 bytes are used for the RTC, and 50 bytes are available for the software to use. The recorder (thermal printer) and the external RS-232 port are controlled from software via a DUART (dual serial port chip). These ports are the same as the COM ports used on a PC and the DUART is programmable via software.
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Section 14: Main Color Board Digital Theory of Operation 14.2 POWER SUPPLY CONNECTIONS Figure 14-1: Power Supply Connections The power supply provides the power for the main board and all of the circuitry in the system. It also contains control circuits for turning on and off the power, as well as supplying the battery backup for the system. 14.2.1 Voltages The microprocessor and its associated circuits are powered from the regulated 3.3 volts DC generated on the power supply board. The 3.
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Section 14: Main Color Board Digital Theory of Operation 14.2.2 Microcontroller Signals The power supply circuit and microcontroller have 2 signals which connect directly with each other, EARLY WARNING and PSOFF. The battery circuits generate an EARLY WARNING signal to the microcontroller to warn it that the power is going down within 100 ms. This EARLY WARNING signal is generated if the power On/Standby switch is pressed or the battery voltage gets too low.
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Section 14: Main Color Board Digital Theory of Operation 14.3 CPU CONNECTIONS The CPU (U7) is a 386EX microcontroller, which contains a 386SX core and various integrated peripherals.
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Section 14: Main Color Board Digital Theory of Operation 14.3.4 CHIP SELECT UNIT The chip select unit has 8 chip selects and are defined as follows: CS0: CS1: CS2: CS3: CS4: CS5: CS6: UCS LCD control register select - 8 bit I/O LCD memory select - 16 bit memory Trend flash select - 8 bit memory RTC select - 8 bit I/O DUART select - 8 bit I/O Misc.
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Section 14: Main Color Board Digital Theory of Operation time a new conversion is initiated the previous conversion’s data is transferred to the 386EX via the SSIORX data line. 14.3.8 ASYNCHRONOUS SERIAL PORT There are 2 asynchronous UART ports on the 386EX, but only one is used. It is connected to the opto-isolators that connect to the SPO2 unit. TXD0: asynchronous transmit signal RXD0: asynchronous receive signal 14.3.
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Section 14: Main Color Board Digital Theory of Operation 14.5.1 CPU SIGNALS Various signals change at various times within a cycle, and the generic timing is shown below. Some of the key signals are ADS#, M/IO#, D/C#, W/R#, WR#, RD#, CS0-CS6#, BLE#, and BHE#. Typical control circuits will look at ADS# at the end of PH2 and make decisions at this time. Refer to the 386EX timing diagrams for a more detailed explanation. Figure 14-3: CPU Timing Diagram 14.
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Section 14: Main Color Board Digital Theory of Operation 14.6.1.1 DRAM TIMING Figure 14-4: DRAM Timing The DRAM requires 104 ns total time, read/write and precharge for each cycle. There is 1 wait state for each DRAM access and a total of 3 T states which is 150 ns. Since the DRAM minimum access time is 104 ns, we have 46 ns of margin. We are using the Hitachi HM51W18165LTT or equivalent which has a RAS* time of 60 ns, a precharge time of 40 ns, a CAS* time of 10 ns, and a WE* time of 10 ns.
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Section 14: Main Color Board Digital Theory of Operation 14.6.2 DRAM FPGA CIRCUITS The DRAM control circuits in the FPGA must decode the various 386EX control signals and generate the DRAM signals. This is done by using CS6# to set a flip flop when ADS# and PH2 are true. When this is true, a flip flop is set, which is output as RAS#. The output of this flip flop is RAS# which is 75 ns long. This signal is generated for all DRAM accesses and refresh.
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Section 14: Main Color Board Digital Theory of Operation Figure 14-6: Flash Read Timing In the FPGA control logic, the executable flash chip select is anded with the trend flash chip select such that CS2* must be high, inactive, when addressing the executable flash. This allows the address overlap for the trend flash. The executable flash chip enable FLSH1CE# is generated in the FPGA and then goes to the executable flash.
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Section 14: Main Color Board Digital Theory of Operation Since the boot flash is for booting up and executing the software program, most accesses to the boot flash are reads. Only when a new program is downloaded will a write to the boot flash occur. 14.7.3 TREND FLASH The trend flash is different. Its purpose is to store the patients data. It has both read and write accesses occurring at regular intervals.
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Section 14: Main Color Board Digital Theory of Operation The processor interface consists of the following signals. CS# is the chip select for the SED1354. It connects directly from the FPGA pin 53 to the SED1345. This signal will go low whenever there is an access by the 386EX to CS0# or CS1#. CS0# relates to the internal registers and CS1# relates the display DRAM. M/R# is the signal that distinguishes between a memory or register access. When M/R# is low, the 386EX is accessing a register.
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Section 14: Main Color Board Digital Theory of Operation The above signals are all of the signals used to interface to the 386EX for transferring of data to and from the control registers and the display ram. There are some general purpose I/O ports that are under software control. They can be programmed as inputs or outputs. Two of these ports are being used (GPIO4 and GPIO5) as outputs and the rest are not being used. If GPIO4 is set, information is displayed left to right.
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Section 14: Main Color Board Digital Theory of Operation 14.8.3 LCD AND 386EX INTERFACE The LCD display chip interfaces directly with the 386EX. When the 386EX initiates a transfer to the 1354F0A, the 386EX generates two wait states and terminates the cycle when the WAIT# signal of the 1354 returns high. This is true for transfers to the 1354F0A’s Video Memory or control registers. 14.8.4 LCD CONTRAST CIRCUIT There is no contrast adjustment for this TFT display. The contrast circuitry is not being used.
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Section 14: Main Color Board Digital Theory of Operation Figure 14-9: Interface Timing The timing diagram above shows the signals and their relationship to each other. 14.10 DUART CONTROL The DUART is a Startech ST16C2550CJ44 which consists of 2 UARTs and FIFOS for the read and write portions of each UART. Channel 0 is assigned to the RS-232 port which exits the unit near the AC and DC inputs. Channel 1 is assigned to the recorder.
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Section 14: Main Color Board Digital Theory of Operation 14.11 KNOB INTERFACE CONTROL The knob consists of a rotary knob with a push button switch. The knob is rotated and the cursor on the LCD display moves forward or backward, depending on which way the knob is rotated. When the knob is pushed it must be detected and indicated to the 386EX. The knob has 2 channels, channel A and channel B.
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Section 14: Main Color Board Digital Theory of Operation 14.13.1 CS5# NIBP PUMP PWM 8 BITS The NIBP pump pulse width modulated (PUMP_PWM) signal is generated in the FPGA via an 8 bit register which is clocked at 313 kHz. An 8 bit value is loaded into this register and then the PUMP_PWM_GO bit (bit 0) in the CONTROL REG. is set true and the pump PWM signal begins.
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Section 14: Main Color Board Digital Theory of Operation Bits 0-3 were defined in the above paragraphs. Bit 4, BCK_LITE_ON is a bit that turns on the LCD backlight when set to a 1. When powered on this bit is 0 and the backlight is off. To turn on the backlight this bit must be set to a 1. Bit 5 enables the clock going to the front end transformer, which generates the isolated front end voltages.
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Section 14: Main Color Board Digital Theory of Operation Register CS5# + C has the following bit assignments. BIT 0: BIT 1: BIT 2: BIT 3: BIT 4: BIT 5: BIT 6: BIT 7: Not used Not used Not used WDT (watch dog timer enable) LCD contrast switch Audio volume switch NIBP switch Alarm silence button 14.13.6 CS5# + E WRITE NSCALL/PTRRST/READ PUSH BUTTONS Writing to this register sets or resets the NURSECALL and PRINTER RESET bits. To set NURSECALL write a 1 to bit 7 and to reset NSCALL write a 0 to bit 7.
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Section 14: Main Color Board Digital Theory of Operation 14.15.1 NIBP System Overview The NPB-4000C Non-Invasive Blood Pressure (NIBP) measurement and display operations described in this section include the pneumatics of the inflatable cuff and control valves, the specialized front end NIBP circuitry, some of the µP Memory and Control circuitry, some of the Power System, and specific switches on the Keypad.
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Section 14: Main Color Board Digital Theory of Operation 14.15.1.1 The pneumatic assembly The pneumatic assembly, consisting of the pump, two controlling valves, and tubing to connect the various pneumatic components together are illustrated in the schematic diagram that follows. See Figure 14-12. The pump output is connected to the cuff and to two valves: a two-way and a three-way valve, as well as to two pressure transducers.
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Section 14: Main Color Board Digital Theory of Operation Figure 14-13: NIBP Hardware Block Diagram 14.15.1.2.1 Pressure Transducers Pressure transducers PS1 and PS2 convert pneumatic pressure levels to voltages in the range from 0.33 volts at 0 mmHg to 4 volts at 300 mmHg. Transducer PS1 is used to sense the main cuff pressure. Transducer PS2 is used as a backup cuff pressure sensor, from which over-pressure warning signals are obtained.
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Section 14: Main Color Board Digital Theory of Operation 14.15.1.2.5 Pump and Valve Drivers Three-way valve V1 coil is powered by VPS that is switched in series with the coil through n-channel MOSFET Q10-6. Switching action of Q10-6 is controlled by the input signal NP3WYV, that is gated by the enabling signal NPPVEN at switch U23. VPS is developed from VBATTP through Q11-6 that is also controlled by NPVEN gating transistor Q6. Diode D5 acts to suppress voltage spikes.
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Section 14: Main Color Board Digital Theory of Operation the previous conversion is transferred to the 386EX. The SSIO unit works with the both of the DMA units in the 386EX as well as the timer unit. The functional operation of the DMA, SSIO, A/D Converter, and the front end is as follows. Software sets up DMA CHANNEL 0 to transfer from DRAM a buffer which contains 16 bit control words. The timer is set up to generate a pulse every 1.25 ms (800 Hz rate).
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Section 14: Main Color Board Digital Theory of Operation The control words sent to the A/D converter contain the A/D multiplexer channel to convert, the data length, data format, and whether the conversion is a unipolar or bipolar conversion. The first bit transferred out the SSIO transmit line is the most significant bit, bit 15. The A/D takes bits 15-8 and the front end takes bits 7-0. Bit definitions are as follows.
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Section 14: Main Color Board Digital Theory of Operation The speaker circuit consists of a software programmable digital potentiometer chip, U28, which is a Dallas DS1666s-10. The software sets the tone frequency by setting the high register with a value, the low register with a value, then programming the digital potentiometer up/down according to the timing specified in the requirement specification. 14.17.1 FPGA THEORY OF OPERATION The Actel FPGA is a 3.
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Section 14: Main Color Board Digital Theory of Operation 14.17.3 RAS/ CONTROL CIRCUIT The RAS/ control circuit consists of 5 flip flops called STARTFF, DRAMINFF, RAS1FF, RAS2FF, and RAS3FF. The ADS/ signal from the 386EX is anded with the CLK_PH2 signal and then goes to the IDE/ input of the DRAMINFF. CS6/ (DRAM chip select) goes to the D input. It is clocked into the flip flop on the rising edge of the IOCLOCK signal at the end of the T1 state (which is the same as the beginning of the T2 state).
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Section 14: Main Color Board Digital Theory of Operation 14.17.3.2 DRAMOE/ CONTROL CIRCUIT The DRAMOE/ signal enables the output drivers in the DRAM which is activated on a read of the DRAM memory. DRAMOE/ is generated from RAS1/, BLEORBHE, WRB/, and LCD_MEM_SEL/. The RAS1/ must be low, indicating that a DRAM access is beginning. The BLEORBHE is high (true) and indicates that a valid read is occurring.
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Section 14: Main Color Board Digital Theory of Operation 14.17.4 CONTROL REGISTER DECODE The CONTROL REGISTER decoder is a 1 of 8 decoder which decodes the register addresses for the 8 control registers in the FPGA. The decoder generates a high going pulse coincident with WRB/ on 1 of the 8 output signal lines. The register addresses are as follows: 1. 2. 3. 4. 5. 6. 7. LOAD NIBP PUMP PWM LOAD CONTRAST PWM LOAD SPEAKER HIGH LOAD SPEAKER LOW LOAD CONTROL REG RESET KNOB INTERRUPT ENABLE WATCH DOG TIMER 8.
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Section 14: Main Color Board Digital Theory of Operation 14.17.9 FLASH WRITE STATE MACHINE The FLASH write state machine consists of 5 flip flops and is set into action when CS2/ or UCS/ is low, CLK_PH1 is high ( which indicates the first phase of the T2 state), WRB/ is low, and BLEORBHE is high indicating a byte or word transfer. The FLSHWRFF1 signal is set true at the midpoint of T2, which generates FLASHWRT and WRITE/ on pin 2.
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Section 14: Main Color Board Digital Theory of Operation 14.17.13 RTC/DUART STATE MACHINE Interfacing to the DUART and RTC requires slowing down the signals. A 20 state machine is implemented to interface to these circuits. The state machine always starts up when ADSB/ is low and CLK_PH1 is high. The RTC1AFF is set high on the rising edge of the master clock, CLK2_40MHZ. If the RTC or DUART is not selected, the state machine is reset on the next CLK2_40MHZ.
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Section 14: Main Color Board Digital Theory of Operation 14.17.16 FREQUENCY GENERATOR The master clock in, generates 2 internal signals, CLK_PH1 and CLK_PH2, both of which are 20 MHz clocks 180 degrees out of phase with each other. The CLK_PH1 is divided down into 10 MHz, 5 MHz, 2.5 MHz, 1.25 MHz, 525 kHz, 313 kHz, 156 kHz, and 78 kHz. The 10 MHz is output on pin 139 and goes to the DUART controller as its master clock. 313 kHz is used by the NIBP PWM circuits.
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Section 14: Main Color Board Digital Theory of Operation 14.17.18 READ BACK MULTIPLEXER A read back multiplexer allows the software to read back programmed and status signals from the FPGA. Register assignments are as follows: 1. 2. 3. 4. 5. 6. 7. 8. PUMP/VALVE PWM CONTRAST PWM SPEAKER HIGH VALUE SPEAKER LOW VALUE CONTROL REG PUSH BUTTON STATUS KNOB/MISC STATUS MISC STATUS 300 HEX 302 HEX, not used 304 HEX 306 HEX 308 HEX 30A HEX 30C HEX 30E HEX 14.17.
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Section 14: Main Color Board Digital Theory of Operation 14.17.20 SPEAKER HIGH AND LOW CONTROL The speaker requires tones from about 300 Hz to 1 kHz with a 55 percent duty cycle. In order to give software full control over both the frequency and duty cycle, there are 2 software programmable 8 bit up counters, one for generating the low portion of the TONE_OUT and one for generating the high portion. The TONE_OUT flip flop is jammed reset when the FREQ_GO bit in the control register is low.
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Section 14: Main Color Board Digital Theory of Operation 14.17.21.5 FE_CLK_EN BIT Bit 5 is the FE_CLK_EN which stands for the front end clock enable bit. This bit enables the 200 kHz signal to the front end power supply transformer. The software has control over the front end power supply via this bit. The major reason for having this bit is to reset the front end by turning the power OFF, then ON again via this bit. 14.17.21.
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Section 14: Main Color Board Digital Theory of Operation 14.17.23 SYNC_ALARM CIRCUIT The power supply board requires a 50 kHz signal to generate the various voltages in the system. A 100 kHz, 50 percent duty cycle signal is programmed in the 386EX TIMER 1 unit. It enters the FPGA on pin 119 and is divided by 2 to get 50 kHz. This is anded with the WDT (pin 62) signal from the 386EX. The WDTDETFF is held reset until enabled by WDTEN.
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Section 14: Main Color Board Digital Theory of Operation Figure 14-14: NPB-4000C Color Motherboard Block Diagram 14-38
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Section 14: Main Color Board Digital Theory of Operation 14.19 CURRENT DRAIN OF DIGITAL ELECTRONICS The worst case current drain has been determined by using the maximum numbers in the data sheets of the devices. Typically the devices operate significantly lower. 386EX 16M DRAM 8M FLASH LCD CNTLR DUART RS232 XCVR 256K FLASH RTC 40mhz osc subtotal misc. logic 130 mA 170max2=340 mA 20 mA 30 mA 3 mA 5 mA 15 mA 15 mA 9 mA 567 mA 78 mA grand total 645 mA power = 3.3 volts x 645 mA = 2.
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SECTION 15: POWER SUPPLY - THEORY OF OPERATION 15.1 Overview 15.2 AC Mains Flyback Power Supply 15.3 Battery Charger 15.4 Buck Converter Operation 15.5 Power Devices 15.6 Miscellaneous Control 15.7 System Power Supply 15.8 Mains (AC) LED Operation 15.9 Power Supply Control Logic 15.10 Alarm Section 15.11 NIBP Pump Control 15.12 Safety Devices 15. POWER SUPPLY - THEORY OF OPERATION 15.1 OVERVIEW 15.1.1 Three Power Supplies See Figure 15-1 and Figure 15-2.
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Section 15: Drawings Figure 15-1: Power Supply Block Diagram Control logic on the power supply assembly is responsible for several system functions: • AC and DC charging LED drivers • System ON/OFF control from the front panel membrane switch • Early Warning OFF notification to the processor board • OFF on command from the processor board • Alarm driver based on processor fault (watch dog time-out) • Alarm Silence from front panel • NIBP Pump control from logic levels • Battery Voltage transmittal to the
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Section 15: Drawings 15.2.1 Overview The AC (mains) power supply accepts 90 to 264 volts RMS at 47 to 63 Hz and provides 18 volts DC at a maximum of 2 amps into the battery charger circuit. The 18 volts DC overrides any supplied external DC (10-16 volts DC) and becomes the dominant source to the charger when both external AC and DC are present. Figure 15-3: General Flyback Circuit Concept 15.2.2 Flyback Principles See Figure 15-3.
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Section 15: Drawings volts DC to the flyback circuit. A control IC runs the FET switch, while the transformer (used as an inductor) stores energy and transfers it to the load. 15.2.3 Input filter and Rectifier The input EMI filter consists of an external "canned" EMI filter assembly (common-mode choke plus X capacitors) that is external to the NPB-4000/C power supply PC board, plus an on- board filter consisting of an L1 common-mode choke with C1 and C2 as X capacitors and C7 and C8 as Y capacitors.
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Section 15: Drawings 15.3 BATTERY CHARGER 15.3.1 Overview The NPB-4000/C power supply contains a battery charger circuit that accepts DC input from either the isolated AC mains flyback circuit or an externally supplied DC input (10 to 16 volts DC). The output of the battery charger provides a current limited, voltage regulated, temperature compensated output to charge a 6 volt, 8 AH lead-acid battery. 15.4 BUCK CONVERTER OPERATION Figure 15-5: Buck Converter Circuit See Figure 15-5.
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Section 15: Drawings Switch current information comes from current transformer T2 that provides a current through R29, which is 1/100 of the main switch current. Thus 1 volt across R29 represents 3.4 amps of switch current. The current waveform is fed through an RC filter (R20, C23) to the controller. The controller limits the output current when the ISNS pin reaches about 1.1 volts, or about 3.5 amps average output current. 15.4.
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Section 15: Drawings to the basic buck-converter diagram to prevent back driving of the circuit from the battery when not charging. Diode D20 acts as a lightweight "catch" diode for the small inductance of the current transformer. 15.6 MISCELLANEOUS CONTROL The voltage regulation attenuator R28/R25 loads the battery when the circuit is not powered, so voltage sensing of the output voltage occurs using Q6 as a switch to connect attenuator resistor R28 to the output voltage.
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Section 15: Drawings Controller U4 is a two-loop controller, current and voltage. Input current information is supplied by transformer T4 which with its 100:1 turns ratio produces 1 volt across R31 at 15.4 amps of peak switch current. Current limit is established by U4 at 1.1 volts or 17 amps peak. This peak current equates to about 5 amps maximum average input current. The voltage loop of U4 regulates the +3.3 volt output through attenuator R41 and R40 which provides 2.5 volts at U4, pin 2.
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Section 15: Drawings Neither LED is driven until CVREF is up, indicating that sufficient power is reaching the charger. 15.9 POWER SUPPLY CONTROL LOGIC When the battery is initially attached to the power supply, an R/C circuit produces a single positive pulse (PWRRST) which ensures that the power and alarm circuits are initially OFF. 15.9.1 ON/OFF Control The NPB-4000/C system power supply is turned ON and OFF by alternate pushes of a membrane switch on the front panel.
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Section 15: Drawings 15.10 ALARM SECTION 15.10.1 Alarm Control When the supply is first turned on, R82 tries to charge C54. During the 300-500 milliseconds charge-up time, it is expected that the supply will come into operation, and the processor board will return sync pulses. The sync pulse will drive Q20 to discharge C54. If the sync pulses stop for any reason, C54 will rise, which will activate the alarm sounder and shut off the supply .
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Section 15: Drawings 15.12.1 Watchdog Shutoff Another shutdown path exists for the system supply . When the system supply begins operation, PWRUP goes high, which begins to charge C49 through R65. Eventually (0.5 second), C49 will charge up (through U12) and the system supply will shut off. The way that the supply is kept running is through the receipt of a SYNC/ALARM pulse from the processor board.
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SECTION 16: MP-205 SERVICE MANUAL (NPB P/N: 044540A-0296) 16.1 Overview 16.2 Module Description 16.3 Circuit Description 16.4 Interconnections 16.5 Sensor Interconnect 16.6 Oxichip Circuit 16.7 Preamp 16.8 Programmable Gain Amplifier (PGA), Demodulator and Demultiplexer 16.9 Filters and Level Shifter 16.10 LED Driver 16.11 Reset Schmitt Trigger 16.12 High Resolution A/D Converter 16.13 Input Filter 16.14 Power Decoupling 16.15 Status and Timing 16.16 Analog Power Regulation 16.17 Microcontroller 16.
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Section 16: MP-205 Service Manual; 044540A-0296 16.3 CIRCUIT DESCRIPTION This section provides service personnel with an explanation of the circuit operation for the oximetry module. The text is supported with a schematic diagram, see Figure 17-1. 16.4 Interconnections 16.4.1 Host (Monitor) Interconnect The monitor interface is a 14-pin dual-row header connector, JP5. This connector includes the power supplied by the host monitor, a serial interface port, and two hardware control lines.
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Section 16: MP-205 Service Manual; 044540A-0296 16.7 Preamp The current-to-voltage (I-to-V) converter has a gain of -249 K V/A and a low-pass corner frequency of 30 kHz. The voltage amplifier has a gain of -2 V/V and a low-pass corner frequency of 20 kHz. The voltage amplifier is disconnected from the I-to-V converter during LED switching transients to prevent transmission of the switching spikes into the programmable gain amplifier (PGA).
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Section 16: MP-205 Service Manual; 044540A-0296 The Red filter circuit components consist of U1A6-8, R19–21, R31, R34–37, C22, C29–30, and C37–38. The IR filter circuit components consist of U1A10-12, R22–24, R32–33, R38–40, C23–24, C31–32, and C39. The IR filter is identical to the Red filter except for the component values in the last stage. The level shifter moves the reference for the signal back to ground. The level shifter (U1A9) selects the desired signal and shifts the signal reference from 2.
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Section 16: MP-205 Service Manual; 044540A-0296 16.14 Power Decoupling The power supply decoupling circuit consists of R29, R30, C16 through C18, C28, and C26 and C27. 16.15 Status and Timing The LED drive, ALC, demodulator, and demultiplexer require timing signals to operate properly. All of the proper timing sequences are provided by the state machine, the OXICLK signal, within the Oxichip U1 circuit. The state machine requires a clock from the CPU at 8 times the desired LED strobe frequency. 16.
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Section 16: MP-205 Service Manual; 044540A-0296 Table 16-1: Oxichip Circuit Pin Descriptions 16-6 Pin Name Pin #, type VSSA 13, AP Analog power return. FR3OUT 14, AO Red filter chain, operational amplifier 3 output. FR3NEG 15, AI Red filter chain, operational amplifier 3 inverting input. FR2OUT 16, AO Red filter chain, operational amplifier 2 output. FR2NEG 17, AI Red filter chain, operational amplifier 2 inverting input. FR1OUT 18, AO Red filter chain, operational amplifier 1 output.
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Section 16: MP-205 Service Manual; 044540A-0296 Table 16-1: Oxichip Circuit Pin Descriptions Pin Name Pin #, type Signal Description 49, DI D1 Data bit 1, to AD1 50, DI D0 Data bit 0, to AD0 51, DO LIM Overcurrent limit indicator, high indicates current limit has tripped, to U4P4-6. 52, DI EN* LED enable, high disables LED drive, low enables LED drive, to U4P1-0. 16.18 TROUBLESHOOTING THE MP-205 16.18.1 Introduction The MP-205 is a subsystem intended for use with a host system.
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Section 16: MP-205 Service Manual; 044540A-0296 Table 16-3: Reported Errors Error # E011 E012 E013 E014 E015 E016 E017 E018 E019 E0210 Error Description RAM error occurred (MP-205 stops normal operation) ROM error occurred (MP-205 stops normal operation) Last message sent by host had a checksum error (last message or command was discarded) Write not permitted or command not allowed (command discarded, normal operation continues) Module received a command with a value out of range (command discarded,
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Section 16: MP-205 Service Manual; 044540A-0296 16.18.4 SRC-2 Settings Rate: Light: Modulation: Remote/Local: 112 High2 LOW RCAL 63 Figure 16-1: Preamplifier and PGA Outputs 16.18.
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Section 16: MP-205 Service Manual; 044540A-0296 16.18.6 SRC-2 Settings Rate: Light: Modulation: Remote/Local: 112 High2 HIGH RCAL 63 Figure 16-2: Filter Outputs and ADC Input 16.18.
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Section 16: MP-205 Service Manual; 044540A-0296 16.18.8 SRC-2 Settings Rate: Light: Modulation: Remote/Local: 112 High2 HIGH DC RCAL 63 Figure 16-3: MP-205 with an SRC-2 Filter Output 16.18.
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Section 16: MP-205 Service Manual; 044540A-0296 16.18.
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Section 16: MP-205 Service Manual; 044540A-0296 16.18.11 SRC-2 Settings Rate: Light: Modulation: Remote/Local: 112 High2 HIGH DC RCAL 63 Figure 16-5: MP-205 with SRC-2 Serial Port TXD Signal, U4 Pin 25 16.19 PACKING FOR SHIPMENT Should you need to ship the oximetry module for any reason, follow the instructions in this section. 16.19.1 General Instructions Pack the module carefully.
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Section 16: MP-205 Service Manual; 044540A-0296 16.19.3 Repackaging in a Different Carton If the original carton is not available: 1. Place module in antistatic bag. 2. Locate suitable corrugated cardboard shipping carton. 3. Fill bottom of carton with packing material. 4. Place bagged unit on layer of packing material and fill box completely with packing material. 5. Seal carton with packing tape. 6. Label carton with shipping address, return address, and RGA number. 16.
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Section 16: MP-205 Service Manual; 044540A-0296 16.20.2 Measurement Conditions SpO2 and pulse rate accuracy specifications apply under the following conditions: • • • • • • Electrosurgical apparatus not used Patient free of injected intravascular dyes Insignificant concentration of carboxyhemoglobin and methemoglobin Sensor at a temperature between 28º C and 42ºC External illumination less than 5,000 lumens/square meter (typical office lighting) Response mode set at Mode 1 16.20.3 Sensors 16.20.3.
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SECTION 17: DRAWINGS 17.1 Overview 17.2 List of Figures 17. DRAWINGS 17.1 OVERVIEW This section contains circuit schematics for the NPB-4000/C patient monitor. 17.2 LIST OF FIGURES Figure No.
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Section 17: Drawings Figure 17-1 MP-205 PCB Schematic (Sheet 1 of 2) 17-3
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Section 17: Drawings Figure 17-2 MP-205 PCB Schematic (Sheet 2 of 2) 17-5
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Section 17: Drawings 2 PWRGND TP59 3 C44 U11 0.
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Section 17: Drawings 1 LINE 2 F2 12 DCSRC SURGE LIMITER 34 750MA SLO-BLO P1 2 LINE 1 F1 12 CVREF R16 2KBP08M 22 mHy 4 R1 1MEG 10% 1W C1 10% 0.1UF X CAP 1 L1 3 2 Q3 10% 50 2 C2 0.1UF 10% X CAP TP13 1 D1 C3 3 1 220UF 10% 400VDC R2 30K 5% 2W 4 34 2 C9 0.02UF 10% 500V 2N4401 TP9 EARTH GROUND CHASSIS P1 4 P1 5 P1 3 R14 680K 5% TP1 75K 51 TP7 D3 5T TP2 1K Shield TP6 5% 3 ISNS 4 RT/CT 8 VREF R11 18.2K 1% TP3 R12 2.49K 1% TP4 C13 0.
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Section 17: Drawings PUMPON 93 94 95 1 TO VIA 96 TP404 92 1 89 TO VIA C16 0.1 91 TP389 1 PS_100KHZ 1 118 3 112 117 TO VIA ADCCLK 128 CS5 HCT244 7 U1 13 113 TO VIA TP394 STXCLK 1 98 TP403 ADCTX 3 1 17 U1 TP280 ADCRX 1 77 FETX TP409 TP399 FERX 3 R125 1 17 U17 79 78 1 TP407 P3.5/INT3 A5 INT2/P3.4 INT1/P3.3 A4 A3 P3.2/INT0 A2 A1 BHE TMROUT1/P3.1 TMROUT0/P3.
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Section 17: Drawings +5V R39 10K Q2 3 1 1 2 10K +5VREG RXDATA TXDATA 2N4401 R96 10K DTR GND R50 VBATTP +5VREG 3.92K 3 4 NC 5 VCC PS1 0.1 VD 1.0UF C33 0.1 1 C20 680PF + 1 6 C1 LMC660 3 TP272 1 U16 2 R59 GND TP267 1 12 + U16 332K - 13 665K DMS873 10 1 + 1 EARLYWRNG 8 1 - R62 665K R92 TP427 R140 TP232 U16 9 R56 562K J2 OSC 1 MAINS/LED 6 33.2K R69 R97 R72 R86 1 +3.3V R135 100K 10K 1% +5VREG 20K 1 +3.3V 430 1% C93 0.1 33.
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Section 17: Drawings 2 3 0 1 0 1 0 1 1 RA-LL LA-LL 1.0 0 TP33 R252 WHITE A J11 R279 TP8 R278 1 9 TP27 C164 C162 6 120PF 120PF J11 TP44 R254 2 12 14 33.2K 15 11 40.2K R262 D25 1SMB75C C150 120PF C157 120PF 1 5 100 I/0X I/1X I/2X 4 TP42 TP49 R247 3 33.2K 1K D24 1SMB75C D J11 R121 R257 332K 40.2K TP371 4 R246 TP32 40.
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Section 17: Drawings MAIN J11 6 WIRES TRONOMED 2 PCB 3 4 LC P/N 5021780 SYSTEM 1 RA LA NIC SHIELD TEMP 8 1 AMP 640457-8 (MALE) J3 10 PIN CONN (?) 10 WIRE RIBBON MP 205 J100 1 2 3 4 5 6 7 8 9 10 AMP 102153-1 DAUGHTER BOARD SAMTEC 3 3 4 5 4 5 J10 1 2 CLOCK AGND 3 4 AGND 5 N.C. 6 AGND N.C.
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14 U17 6 EOC 1 BEAD TP289 1TP414 EOCIN DRAMOE CS2 CS1 CS0 CS5 CS4 CS3 A3 A4 CS6 U5-8 A2 BD4 BD3 BD2 BD1 BD0 A1 74LVC541 WRITE PUMPON BD7 BD6 BD5 L3 C9 0.1 EOCIN 560PF L4 BEAD L5 BEAD 1TP415 U5-8 C186 C185 560PF 560PF 560PF L2 C17 0.1 560PF 1 C184 C183 560PF C182 C181 560PF C180 C179 560PF TP449 R152 10K C12 0.1 C8 0.1 Section 17: Drawings 1TP418 U5-37 BEAD 1TP419 U5-58 U5-89 +3.3V +3.