LCD/CRT TECHNICAL & USER MANUAL S1D13505

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S1D13505 Embedded RAMDAC LCD/CRT Controller

S1D13505

TECHNICAL MANUAL

Document Number: X23A-Q-001-12

Information in this document is subject to change without notice. You may download and use this document, but only for your own use in

evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any

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Summary of content (556 pages)

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S1D13505 Embedded RAMDAC LCD/CRT Controller S1D13505 TECHNICAL MANUAL Document Number: X23A-Q-001-12 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-Q-001-12 TECHNICAL MANUAL Issue Date: 01/04/18
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Page 3 Epson Research and Development Vancouver Design Center Customer Support Information Comprehensive Support Tools Seiko Epson Corp. provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems. Evaluation / Demonstration Board • Assembled and fully tested graphics evaluation board with installation guide and schematics. • To borrow an evaluation board, please contact your local Seiko Epson Corp. sales representative.
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Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-Q-001-12 TECHNICAL MANUAL Issue Date: 01/04/18
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ENERGY S AV I N G GRAPHICS EPSON S1D13505 S1D13505 EMBEDDED RAMDAC LCD/CRT CONTROLLER October 2001 ■ DESCRIPTION The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and display devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PCs, and Office Automation.
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GRAPHICS S1D13505 ■ SYSTEM BLOCK DIAGRAM EDO-DRAM FPM-DRAM Analog Out CPU Data and Control Signals S1D13505 CRT Digital Out Flat Panel CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS • S1D13505 Technical • Linux Console Driver Manual • S5U13505 Evaluation Boards • Windows CE Display Driver • CPU Independent Software • VXWorks TornadoTM Display Utilities Driver Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel:
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S1D13505 Embedded RAMDAC LCD/CRT Controller Hardware Functional Specification Document Number: X23A-A-001-14 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-A-001-14 Hardware Functional Specification Issue Date: 01/02/02
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Page 3 Epson Research and Development Vancouver Design Center Table of Contents 1 2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 Memory Interface . . . . . .
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Page 4 7 Epson Research and Development Vancouver Design Center A.C. Characteristics 7.1 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1.1 SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 7.1.2 SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 7.1.3 MC68K Bus 1 Interface Timing (e.g. MC68000) . . . . . . . . . . . . . . . . . . . . . . . .46 7.1.
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Page 5 Epson Research and Development Vancouver Design Center 9 8.2.5 Clock Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.2.6 Power Save Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 8.2.7 Miscellaneous Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 8.2.8 Look-Up Table Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 8.2.
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Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-A-001-14 Hardware Functional Specification Issue Date: 01/02/02
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Page 7 Epson Research and Development Vancouver Design Center List of Tables Table 5-1: Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 5-2: Memory Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 5-2: LCD Interface Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 5-3: CRT Interface Pin Descriptions . . . . . . . . . . . . . . . . .
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Page 8 Epson Research and Development Vancouver Design Center Table 7-27: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . .85 Table 7-28: 16-Bit Single Color Passive LCD Panel A.C. Timing. . . . . . . . . . . . . . . . . . . . . . . . .87 Table 7-29: 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . .89 Table 7-30: 8-Bit Dual Color Passive LCD Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . .
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Page 9 Epson Research and Development Vancouver Design Center List of Figures Figure 3-1: Typical System Diagram (SH-4 Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3-2: Typical System Diagram (SH-3 Bus) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3-3: Typical System Diagram (MC68K Bus 1, 16-Bit 68000) . . . . . . . . . . . . . . . . . . . . . 16 Figure 3-4: Typical System Diagram (MC68K Bus 2, 32-Bit 68030) . . . . . . . . . . . . . . . .
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Page 10 Epson Research and Development Vancouver Design Center Figure 7-30: 8-Bit Single Color Passive LCD Panel Timing (Format 1). . . . . . . . . . . . . . . . . . . . . 82 Figure 7-31: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . 83 Figure 7-32: 8-Bit Single Color Passive LCD Panel Timing (Format 2). . . . . . . . . . . . . . . . . . . . . 84 Figure 7-33: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . .
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Epson Research and Development Vancouver Design Center Page 11 1 Introduction 1.1 Scope This is the Hardware Functional Specification for the S1D13505 Embedded RAMDAC LCD/CRT Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. This specification will be updated as appropriate.
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Page 12 Epson Research and Development Vancouver Design Center 2 Features 2.1 Memory Interface • 16-bit DRAM interface: • EDO-DRAM up to 40MHz data rate (80M bytes/sec.). • FPM-DRAM up to 25MHz data rate (50M bytes/sec.). • Memory size options: • 512K bytes using one 256K×16 device. • 2M bytes using one 1M×16 device. • Performance Enhancement Register to tailor the memory control output timing for the DRAM device. 2.2 CPU Interface • Supports the following interfaces: • 8/16-bit SH-4 bus interface.
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Page 13 Epson Research and Development Vancouver Design Center 2.3 Display Support • 4/8-bit monochrome passive LCD interface. • 4/8/16-bit color passive LCD interface. • Single-panel, single-drive displays. • Dual-panel, dual-drive displays. • Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD is supported up to 64K color depth (16-bit data). • Embedded RAMDAC (DAC)with direct analog CRT drive. • Simultaneous display of CRT and passive or TFT/D-TFD panels. 2.
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Page 14 Epson Research and Development Vancouver Design Center 2.7 Miscellaneous • The memory data bus, MD[15:0], is used to configure the chip at power-on. • Three General Purpose Input/Output pins, GPIO[3:1], are available if the upper Memory Address pins are not required for asymmetric DRAM support. • Suspend power save mode can be initiated by either hardware or software.
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Page 15 Epson Research and Development Vancouver Design Center Power Management Oscillator SUSPEND# CLKI 3 Typical System Implementation Diagrams SH-4 BUS A[21] M/R# CSn# CS# A[20:0] AB[20:0] D[15:0] DB[15:0] FPDAT[15:8] UD[7:0] FPDAT[7:0] LD[7:0] FPSHIFT FPSHIFT 4/8/16-bit FPFRAME FPFRAME LCD Display FPLINE WE1# DRDY WE1# BS# LCDPWR RD/WR# RD# MOD S1D13505F00A BS# RD/WR# FPLINE RD# RAS# LCAS# UCAS# LCAS# UCAS# WE# RAS# BUSCLK RESET# CRT Display VRTC WE# CKIO
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Page 20 Epson Research and Development Vancouver Design Center 4 Internal Description 4.1 Block Diagram Showing Datapaths 16-bit FPM/EDO-DRAM Memory Controller Register CPU R/W Display FIFO Host CPU/MPU LCD I/F LCD I/F LookUp Tables DAC Cursor FIFO Power Save CRT CRTC Clocks 4.2 Block Descriptions 4.2.1 Register The Register block contains all the register latches 4.2.
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Epson Research and Development Vancouver Design Center Page 21 4.2.4 Memory Controller The Memory Controller block arbitrates between CPU accesses and display refresh accesses as well as generates the necessary signals to interface to one of the supported 16-bit memory devices (FPMDRAM or EDO-DRAM). 4.2.5 Display FIFO The Display FIFO block fetches display data from the Memory Controller for display refresh. 4.2.
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Page 22 Epson Research and Development Vancouver Design Center 5 Pins 5.
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Page 23 Epson Research and Development Vancouver Design Center 5.2 Pin Description Key: I = Input O = Output IO = Bi-Directional (Input/Output) A = Analog P = Power pin C = CMOS level input CD = CMOS level input with pull down resistor (typical values of 100KΩ/180ΚΩ at 5V/3.
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Page 24 Epson Research and Development Vancouver Design Center Table 5-1: Host Interface Pin Descriptions (Continued) Pin Name AB[16:13] AB17 AB18 AB19 AB20 Type I I I I I Pin # 115-118 114 113 112 111 Cell C C C C C RESET# State Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Description • For Philips PR31500/31700 Bus, these pins are connected to VDD. • For Toshiba TX3912 Bus, these pins are connected to VDD. • For PowerPC Bus, these pins input the system address bits 15 through 18 (A[15:18]).
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Page 25 Epson Research and Development Vancouver Design Center Table 5-1: Host Interface Pin Descriptions (Continued) Pin Name Type Pin # Cell RESET# State Description These pins are the system data bus. For 8-bit bus modes, unused data pins should be tied to VDD. DB[15:0] IO 16-31 C/TS2 Hi-Z • For SH-3/SH-4 Bus, these pins are connected to D[15:0]. • For MC68K Bus 1, these pins are connected to D[15:0]. • For MC68K Bus 2, these pins are connected to D[31:16] for 32-bit devices (e.g.
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Page 26 Epson Research and Development Vancouver Design Center Table 5-1: Host Interface Pin Descriptions (Continued) Pin Name Type Pin # Cell RESET# State Description This pin inputs the system bus clock. It is possible to apply a 2x clock and divide it by 2 internally - see MD12 in Summary of Configuration Options. BUSCLK I 13 C Hi-Z • • • • • • • • • For SH-3/SH-4 Bus, this pin is connected to CKIO. For MC68K Bus 1, this pin is connected to CLK.
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Page 27 Epson Research and Development Vancouver Design Center Table 5-1: Host Interface Pin Descriptions (Continued) Pin Name Type Pin # Cell RESET# State Description This is a multi-purpose pin: • • • • RD# I 7 CS Hi-Z • • • • • For SH-3/SH-4 Bus, this pin inputs the read signal (RD#). For MC68K Bus 1, this pin is connected to VDD. For MC68K Bus 2, this pin inputs the bus size bit 1 (SIZ1). For Generic Bus, this pin inputs the read command for the lower data byte (RD0#).
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Page 28 Epson Research and Development Vancouver Design Center Table 5-1: Host Interface Pin Descriptions (Continued) Pin Name Type Pin # Cell RESET# State Description The active polarity of the WAIT# output is configurable; the state of MD5 on the rising edge of RESET# defines the active polarity of WAIT# - see “Summary of Configuration Options”.
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Page 29 Epson Research and Development Vancouver Design Center 5.2.2 Memory Interface Table 5-2: Memory Interface Pin Descriptions Pin Name LCAS# Type O Pin # 51 Cell CO1 RESET# State 1 Description • For dual-CAS# DRAM, this is the column address strobe for the lower byte (LCAS#). • For single-CAS# DRAM, this is the column address strobe (CAS#). See “Memory Interface Pin Mapping” for summary. See Memory Interface Timing for detailed functionality.
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Page 30 Epson Research and Development Vancouver Design Center Table 5-2: Memory Interface Pin Descriptions (Continued) Pin Name MA[8:0] Type O Pin # 58, 60, 62, 64, 66, 67, 65, 63, 61 Cell CO1 RESET# State 0utput Description Multiplexed memory address - see Memory Interface Timing for functionality. This is a multi-purpose pin: MA9 IO 56 C/TS 0utput 1 • For 2M byte DRAM, this is memory address bit 9 (MA9). • For asymmetrical 512K byte DRAM, this is memory address bit 9 (MA9).
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Page 31 Epson Research and Development Vancouver Design Center 5.2.3 LCD Interface Table 5-2: LCD Interface Pin Descriptions Pin Name Type Pin # Cell RESET# State Description FPDAT[15:0] O 95-88, 86-79 CN3 0utput Panel data bus. Not all pins are used for some panels - see LCD Interface Pin Mapping for details. Unused pins are driven low.
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Page 32 Epson Research and Development Vancouver Design Center 5.2.
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Page 33 Epson Research and Development Vancouver Design Center 5.
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Page 34 Epson Research and Development Vancouver Design Center 5.
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Page 35 Epson Research and Development Vancouver Design Center Table 5-7: Memory Interface Pin Mapping S1D13505 Pin Names FPM/EDO-DRAM Sym 256Kx16 2-CAS# 2-WE# Asym 256Kx16 2-CAS# Sym 1Mx16 2-WE# 2-CAS# MD[15:0] D[15:0] MA[8:0] A[8:0] MA9 GPIO3 2-WE# Asym 1Mx16 2-CAS# A9 MA10 A9 GPIO1 MA11 A10 GPIO2 UCAS# UCAS# UWE# UCAS# LCAS# WE# LCAS# CAS# WE# LWE# RAS# 2-WE# A11 UWE# UCAS# UWE# UCAS# LCAS# CAS# WE# LWE# UWE# LCAS# CAS# LCAS# CAS# WE# LWE# WE# LWE# RAS#
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Page 36 Epson Research and Development Vancouver Design Center Table 5-8: LCD Interface Pin Mapping Monochrome Passive Panel S1D13505 Pin Names Single 4-bit 8-bit Color Passive Panel Dual Single 8-bit 4-bit Single Single Format 1 Format 2 8-bit 8-bit FPFRAME Color TFT/D-TFD Panel Single 16-Bit Dual 8-bit 16-bit 9-bit 12-bit 18-bit FPFRAME FPLINE FPLINE FPSHIFT FPSHIFT DRDY FPSHIFT 2 MOD MOD DRDY FPDAT0 driven 0 D0 LD0 driven 0 D0 D0 D0 LD0 LD0 R2 R3 R5 FPDAT1
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Page 37 Epson Research and Development Vancouver Design Center 5.5 CRT Interface The following figure shows the external circuitry for the CRT interface. DAC VDD = 3.3V DAC VDD = 2.7V to 5.5V OR 1.5kΩ 1% 4.6 mA IREF 4.6 mA 1µF 4.
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Page 38 Epson Research and Development Vancouver Design Center 6 D.C. Characteristics Table 6-1: Absolute Maximum Ratings Symbol Parameter Rating Units VDD Supply Voltage VSS - 0.3 to 6.0 V DAC VDD Supply Voltage VSS - 0.3 to 6.0 V VIN Input Voltage VSS - 0.3 to VDD + 0.5 V VOUT Output Voltage VSS - 0.3 to VDD + 0.5 V TSTG Storage Temperature -65 to 150 °C TSOL Solder Temperature/Time 260 for 10 sec.
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Page 39 Epson Research and Development Vancouver Design Center Table 6-3: Electrical Characteristics for VDD = 5.
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Page 40 Epson Research and Development Vancouver Design Center Table 6-4: Electrical Characteristics for VDD = 3.
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Page 41 Epson Research and Development Vancouver Design Center Table 6-5: Electrical Characteristics for VDD = 3.0V typical Symbol Parameter IDDS Quiescent Current IIZ Input Leakage Current IOZ Output Leakage Current Condition Min Typ Quiescent Conditions Max Units 260 uA -1 1 µA -1 1 µA High Level Output Voltage VDD = min IOL = -1.8mA (Type1), VDD - 0.3 -3.5mA (Type2) -5mA (Type3) VOL Low Level Output Voltage VDD = min 1.8mA (Type1), IOL = 3.
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Page 42 Epson Research and Development Vancouver Design Center 7 A.C. Characteristics Conditions: VDD = 3.0V ± 10% and VDD = 5.0V ± 10% TA = -40° C to 85° C Trise and Tfall for all inputs must be ≤ 5 nsec (10% ~ 90%) CL = 50pF (CPU Interface), unless noted CL = 100pF (LCD Panel Interface) CL = 10pF (Display Buffer Interface) CL = 10pF (CRT Interface) 7.1 CPU Interface Timing 7.1.
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Page 43 Epson Research and Development Vancouver Design Center Note The SH-4 Wait State Control Register for the area in which the S1D13505 resides must be set to a non-zero value. The SH-4 read-to-write cycle transition must be set to a non-zero value (with reference to BUSCLK). Table 7-1: SH-4 Timing Symbol t1 Parameter 3.0Va Min Max 5.
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Page 44 Epson Research and Development Vancouver Design Center 7.1.2 SH-3 Interface Timing t1 t2 t3 CKIO t4 t5 A[20:0], M/R# RD/WR# t6 t7 BS# t12 t8 CSn# t10 t9 WEn# RD# t12 t11 WAIT# t14 t13 D[15:0](write) t15 t16 D[15:0](read) Figure 7-2: SH-3 Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected. Note The SH-3 Wait State Control Register for the area in which the S1D13505 resides must be set to a non-zero value.
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Page 45 Epson Research and Development Vancouver Design Center Table 7-2: SH-3 Timing Symbol Parameter 3.0Va Min Max 5.0Vb Min Max 15.1 15.
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Page 46 Epson Research and Development Vancouver Design Center 7.1.3 MC68K Bus 1 Interface Timing (e.g. MC68000) t1 t2 t3 CLK t4 t5 A[20:1] M/R# t6 CS# t17 AS# t11 UDS# LDS# t8 t7 R/W# t9 t10 DTACK# t12 t13 D[15:0](write) t14 t15 t16 D[15:0](read) Figure 7-3: MC68000 Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected.
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Page 47 Epson Research and Development Vancouver Design Center Table 7-3: MC68000 Timing 3.0V Symbol t1 t2 Parameter Clock period Min 20 5.
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Page 48 Epson Research and Development Vancouver Design Center 7.1.4 MC68K Bus 2 Interface Timing (e.g. MC68030) t1 t2 t3 CLK t5 t4 A[20:0] SIZ[1:0] M/R# t6 CS# t17 AS# t11 DS# t7 t8 R/W# t9 t10 DSACK1# t12 t13 D[31:16](write) t14 t15 t16 D[31:16](read) Figure 7-4: MC68030 Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected.
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Page 49 Epson Research and Development Vancouver Design Center Table 7-4: MC68030 Timing 3.0V Symbol t1 t2 Parameter Clock period Min 20 5.
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Page 50 Epson Research and Development Vancouver Design Center 7.1.5 PC Card Interface Timing t1 t2 t3 CLK t5 t4 A[20:0] M/R# -CE[1:0] t6 CS# -OE -WE t7 t8 -WAIT t10 t9 D[15:0](write) t11 t12 t13 D[15:0](read) Figure 7-5: PC Card Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected.
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Page 51 Epson Research and Development Vancouver Design Center Table 7-5: PC Card Timing Symbol t1 Parameter Clock period 3.0V Min Max 20 5.
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Page 52 Epson Research and Development Vancouver Design Center 7.1.6 Generic Interface Timing t1 t2 t3 CLK t5 t4 A[20:0] M/R# t6 CS# RD0#,RD1# WE0#,WE1# t7 t8 WAIT# t10 t9 D[15:0](write) t11 t12 t13 D[15:0](read) Figure 7-6: Generic Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected.
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Page 53 Epson Research and Development Vancouver Design Center Table 7-6: Generic Timing Symbol t1 Parameter Clock period 3.0V Min Max 20 5.
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Page 54 Epson Research and Development Vancouver Design Center 7.1.7 MIPS/ISA Interface Timing t1 t2 t3 BUSCLK t5 t4 LatchA20 SA[19:0] M/R#, SBHE# t6 CS# MEMR# MEMW# t7 t8 IOCHRDY t9 t10 SD[15:0](write) t11 t12 t13 SD[15:0](read) Figure 7-7: MIPS/ISA Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected.
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Page 55 Epson Research and Development Vancouver Design Center Table 7-7: MIPS/ISA Timing 3.0V Symbol t1 t2 Parameter Clock period Min 20 5.
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Page 56 Epson Research and Development Vancouver Design Center 7.1.8 Philips Interface Timing (e.g.
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Page 57 Epson Research and Development Vancouver Design Center Table 7-8: Philips Timing 3.0V Symbol t1 t2 Parameter Min 13.3 Clock period 5.0V Max 6 Clock pulse width low Min 13.
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Page 58 Epson Research and Development Vancouver Design Center 7.1.9 Toshiba Interface Timing (e.g.
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Page 59 Epson Research and Development Vancouver Design Center Table 7-10: Toshiba Timing 3.0V Symbol t1 5.0V Clock period Min 13.3 Clock pulse width low 5.4 5.4 t3 Clock pulse width high 5.4 5.4 ns t4 ADDR[12:0] setup to first CLK of cycle 10 10 ns t2 Parameter Max Min 13.
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Page 60 Epson Research and Development Vancouver Design Center 7.1.10 Power PC Interface Timing (e.g. MPC8xx, MC68040, Coldfire) t1 t2 t3 CLKOUT t4 t5 A[11:31], RD/WR# TSIZ[0:1], M/R# t7 t6 CS# t8 t9 TS# t11 t10 t12 t13 t15 t16 TA# t14 BI# t17 t18 D[0:15](write) t19 t20 t21 D[0:15](read) Figure 7-12: Power PC Timing Note The above timing diagram is not applicable if the BUSCLK divided by 2 configuration option is selected.
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Page 61 Epson Research and Development Vancouver Design Center Table 7-12: Power PC Timing 3.0V Symbol t1 t2 Parameter Clock period Clock pulse width low Min 25 5.
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Page 62 Epson Research and Development Vancouver Design Center 7.2 Clock Input Requirements t t PWH PWL 90% V IH VIL 10% t tr T f OSC Figure 7-13: Clock Input Requirement Table 7-13: Clock Input Requirements for CLKI divided down internally (MCLK = CLKI/2) Symbol Parameter Min Max Units TOSC Input Clock Period 12.5 ns tPWH Input Clock Pulse Width High 5.6 ns tPWL Input Clock Pulse Width Low 5.
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Page 63 Epson Research and Development Vancouver Design Center 7.3 Memory Interface Timing 7.3.
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Page 64 Epson Research and Development Vancouver Design Center Memory Clock t1 RAS# t3 t5 t4 t6 t1 t7 CAS# t8 MA t9 t10 t11 C2 C1 R C3 t12 C2 C1 t23 C3 t19 t24 WE# t15 t14 MD(Read) d1 t25 d2 t26 d3 t20 t21 MD(Write) d1 t22 d2 d3 Figure 7-15: EDO-DRAM Read-Write Timing Table 7-15: EDO-DRAM Read/Write/Read-Write Timing Symbol t1 t2 Parameter Min Max Units Internal memory clock period 25 ns Random read cycle REG[22h] bit 6-5 == 00 5t1 ns Random read cycle REG[22h] bit
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Page 65 Epson Research and Development Vancouver Design Center Table 7-15: EDO-DRAM Read/Write/Read-Write Timing Symbol Parameter Min Max Units Read Command Setup (REG[22h] bit 4 = 0 and bits 3-2 = 00) 4.45 t1 - 3 ns Read Command Setup (REG[22h] bit 4 = 0 and bits 3-2 = 10) 3.45 t1 - 3 ns Read Command Setup (REG[22h] bit 4 = 1 and bits 3-2 = 00) 3.45 t1 - 3 ns Read Command Setup (REG[22h] bit 4 = 1 and bits 3-2 = 10) 2.45 t1 - 3 ns Read Command Setup (REG[22h] bits 3-2 = 01) 3.
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Page 66 Epson Research and Development Vancouver Design Center 7.3.2 EDO-DRAM CAS Before RAS Refresh Timing t1 Memory Clock t2 t3 RAS# t4 t5 t6 CAS# Figure 7-16: EDO-DRAM CAS Before RAS Refresh Timing Table 7-16: EDO-DRAM CAS Before RAS Refresh Timing Symbol t1 t2 t3 t4 Parameter Internal memory clock period Min 25 Max Units ns RAS# precharge time (REG[22h] bits 3-2 = 00) 2t1 - 3 ns RAS# precharge time (REG[22h] bits 3-2 = 01) 1.
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Page 67 Epson Research and Development Vancouver Design Center Table 7-16: EDO-DRAM CAS Before RAS Refresh Timing Symbol t6 Parameter Min CAS# Hold to RAS# (REG[22h] bit 6-5 = 00 and bits 3-2 = 00) 2.45 t1 - 3 ns CAS# Hold to RAS# (REG[22h] bit 6-5 = 00 and bits 3-2 = 01) 3 t1 - 3 ns CAS# Hold to RAS# (REG[22h] bit 6-5 = 00 and bits 3-2 = 10) 3.45 t1 - 3 ns CAS# Hold to RAS# (REG[22h] bit 6-5 = 01 and bits 3-2 = 00) 1.
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Page 68 Epson Research and Development Vancouver Design Center 7.3.3 EDO-DRAM Self-Refresh Timing Stopped for suspend mode t1 Restarted for active mode Memory Clock t2 RAS# t3 t4 t5 CAS# Figure 7-17: EDO-DRAM Self-Refresh Timing Table 7-17: EDO-DRAM Self-Refresh Timing Symbol t1 t2 t3 t4 t5 Parameter Min Max Units 25 ns RAS# precharge time (REG[22h] bits 3-2 = 00) 2 t1 - 3 ns RAS# precharge time (REG[22h] bits 3-2 = 01) 1.
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Page 69 Epson Research and Development Vancouver Design Center 7.3.
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Page 70 Epson Research and Development Vancouver Design Center t1 Memory Clock RAS# t5 t4 t3 t6 t1 t7 CAS# t9 t8 MA t10 t11 R C2 C1 C3 C1 t12 t21 C2 C3 t16 t17 t18 t19 t20 WE# t14 MD(read) d1 t15 d2 MD(write) d3 d1 d2 d3 Figure 7-19: FPM-DRAM Read-Write Timing Table 7-18: FPM-DRAM Read/Write/Read-Write Timing Symbol t1 t2 t3 t4 Parameter Min Max Units Internal memory clock period 40 ns Random read cycle REG[22h] bit 6-5 == 00 5t1 ns Random read cycle REG[22h] bit
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Page 71 Epson Research and Development Vancouver Design Center Table 7-18: FPM-DRAM Read/Write/Read-Write Timing Symbol Parameter Row address hold time (REG[22h] bits 3-2 = 00 or 10) Min Max Units t1 - 3 ns Row address hold time (REG[22h] bits 3-2 = 01) 0.45 1t1 - 3 ns t10 Column address setup time 0.45 t1 - 3 ns t11 Column address hold time 0.45 t1 - 3 ns Read Command Setup (REG[22h] bit 4 = 0 and bits 3-2 = 00) 4.
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Page 72 Epson Research and Development Vancouver Design Center 7.3.5 FPM-DRAM CAS Before RAS Refresh Timing t1 Memory Clock t2 t3 RAS# t4 t5 t6 CAS# Figure 7-20: FPM-DRAM CAS Before RAS Refresh Timing Table 7-19: FPM-DRAM CAS Before RAS Refresh Timing Symbol t1 t2 t3 t4 t5 t6 Parameter Internal memory clock period Min Max Units 40 ns RAS# precharge time (REG[22h] bits 3-2 = 00) 2.45 t1 - 3 ns RAS# precharge time (REG[22h] bits 3-2 = 01 or 10) 1.
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Page 73 Epson Research and Development Vancouver Design Center 7.3.6 FPM-DRAM Self-Refresh Timing Stopped for suspend mode t1 Restarted for active mode Memory Clock t2 RAS# t3 t4 CAS# Figure 7-21: FPM-DRAM Self-Refresh Timing Table 7-20: FPM-DRAM CBR Self-Refresh Timing Symbol t1 t2 t3 t4 Parameter Min Max Units 40 ns RAS# precharge time (REG[22h] bits 3-2 = 00) 2.45 t1 - 1 ns RAS# precharge time (REG[22h] bits 3-2 = 01 or 10) 1.
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Page 74 Epson Research and Development Vancouver Design Center 7.4 Power Sequencing 7.4.1 LCD Power Sequencing SUSPEND# or LCD Enable Bit t1 t5 t6 LCDPWR t2 t3 FPFRAME FPLINE FPSHIFT FPDATA DRDY t4 t7 CLKI Figure 7-22: LCD Panel Power Off / Power On Timing.
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Page 75 Epson Research and Development Vancouver Design Center 7.4.2 Power Save Status Power Save t2 t1 Power Save Status Bit t3 Memory Access allowed not allowed allowed Figure 7-23: Power Save Status and Local Bus Memory Access Relative to Power Save Mode Note Power Save can be initiated through either the SUSPEND# pin or Software Suspend Enable Bit.
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Page 76 Epson Research and Development Vancouver Design Center 7.5 Display Interface 7.5.
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Page 77 Epson Research and Development Vancouver Design Center t1 Sync Timing t2 FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t8 t10 t11 t12 FPSHIFT t13 t14 1 UD[3:0] 2 Figure 7-25: 4-Bit Single Monochrome Passive LCD Panel A.C. Timing Table 7-23: 4-Bit Single Monochrome Passive LCD Panel A.C.
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Page 78 Epson Research and Development Vancouver Design Center 7.5.
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Page 79 Epson Research and Development Vancouver Design Center t1 t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t8 t10 t11 t12 FPSHIFT t13 UD[3:0] LD[3:0] t14 1 2 Figure 7-27: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing Table 7-24: 8-Bit Single Monochrome Passive LCD Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6.
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Page 80 Epson Research and Development Vancouver Design Center 7.5.
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Page 81 Epson Research and Development Vancouver Design Center t1 t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t7 t9 t8 t11 t10 t12 FPSHIFT t13 UD[3:0] t14 1 2 Figure 7-29: 4-Bit Single Color Passive LCD Panel A.C. Timing Table 7-25: 4-Bit Single Color Passive LCD Panel A.C. Timing Symbol Parameter t1 FPFRAME setup to FPLINE pulse trailing edge t2 FPFRAME hold from FPLINE pulse trailing edge t3 1. 2. 3. 4. 5. 6.
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Page 82 Epson Research and Development Vancouver Design Center 7.5.
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Page 83 Epson Research and Development Vancouver Design Center t1 t2 Sync Timing FPFRAME t4 t3 FPLINE Data Timing FPLINE t5a t5b t6 t8a t7 t9 t10 t11 FPSHIFT t8b FPSHIFT2 t12 UD[3:0] LD[3:0] t13 1 2 Figure 7-31: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1) Table 7-26: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 1) Symbol t1 1. 2. 3. 4. 5. 6. 7.
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Page 84 Epson Research and Development Vancouver Design Center 7.5.
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Page 85 Epson Research and Development Vancouver Design Center t1 Sync Timing t2 FPFRAME t3 t4 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t11 t10 FPSHIFT t12 UD[3:0] LD[3:0] t13 1 2 Figure 7-33: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2) Table 7-27: 8-Bit Single Color Passive LCD Panel A.C. Timing (Format 2) Symbol t1 1. 2. 3. 4. 5. 6.
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Page 86 Epson Research and Development Vancouver Design Center 7.5.
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Page 87 Epson Research and Development Vancouver Design Center t1 Sync Timing t2 FPFRAME t3 t4 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t10 t11 FPSHIFT t12 UD[7:0] LD[7:0] t13 1 2 Figure 7-35: 16-Bit Single Color Passive LCD Panel A.C. Timing Table 7-28: 16-Bit Single Color Passive LCD Panel A.C. Timing Symbol t1 1. 2. 3. 4. 5. 6.
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Page 88 Epson Research and Development Vancouver Design Center 7.5.
PAGE 95
Page 89 Epson Research and Development Vancouver Design Center t1 Sync Timing t2 FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t10 t11 FPSHIFT t12 UD[3:0] LD[3:0] t13 1 2 Figure 7-37: 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing Table 7-29: 8-Bit Dual Monochrome Passive LCD Panel A.C. Timing Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 1. 2. 3. 4. 5. 6.
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Page 90 Epson Research and Development Vancouver Design Center 7.5.
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Page 91 Epson Research and Development Vancouver Design Center t1 t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t11 t10 FPSHIFT t12 UD[3:0] LD[3:0] t13 1 2 Figure 7-39: 8-Bit Dual Color Passive LCD Panel A.C. Timing Table 7-30: 8-Bit Dual Color Passive LCD Panel A.C. Timing Symbol t1 1. 2. 3. 4. 5. 6.
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Page 92 Epson Research and Development Vancouver Design Center 7.5.
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Page 93 Epson Research and Development Vancouver Design Center t1 t2 Sync Timing FPFRAME t4 t3 FPLINE t5 MOD Data Timing FPLINE t6 t8 t7 t9 t14 t11 t10 FPSHIFT t12 UD[7:0] LD[7:0] t13 1 2 Figure 7-41: 16-Bit Dual Color Passive LCD Panel A.C. Timing Table 7-31: 16-Bit Dual Color Passive LCD Panel A.C. Timing Symbol t1 t2 1. 2. 3. 4. 5. 6.
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Page 94 Epson Research and Development Vancouver Design Center 7.5.
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Page 95 Epson Research and Development Vancouver Design Center t8 t9 FPFRAME t12 FPLINE t6 FPLINE t15 t7 t17 DRDY t14 t1 t2 t3 t11 t13 t16 FPSHIFT t4 R[5:1] G[5:0] B[5:1] t5 1 2 639 640 t10 Note: DRDY is used to indicate the first pixel Figure 7-43: TFT/D-TFD A.C.
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Page 96 Epson Research and Development Vancouver Design Center Table 7-32: TFT/D-TFD A.C. Timing Symbol 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. Parameter Min 1 Typ Max Units Ts (note 1) t1 FPSHIFT period t2 FPSHIFT pulse width high 0.45 Ts t3 FPSHIFT pulse width low 0.45 Ts t4 data setup to FPSHIFT falling edge 0.45 Ts 0.
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Page 97 Epson Research and Development Vancouver Design Center 7.5.
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Page 98 Epson Research and Development Vancouver Design Center t1 t2 VRTC t3 HRTC Figure 7-45: CRT A.C. Timing Symbol 1. 2. 3.
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Page 99 Epson Research and Development Vancouver Design Center 8 Registers 8.1 Register Mapping The S1D13505 registers are memory mapped. The system addresses the registers through the CS#, M/R#, and AB[5:0] input pins. When CS# = 0 and M/R# = 0, the registers are mapped by address bits AB[5:0], e.g. REG[00h] is mapped to AB[5:0] = 000000, REG[01h] is mapped to AB[5:0] = 000001.
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Page 100 Epson Research and Development Vancouver Design Center 8.2.2 Memory Configuration Registers Memory Configuration Register REG[01h] n/a bits 6-4 RW Refresh Rate Bit 2 Refresh Rate Bit 1 Refresh Rate Bit 0 n/a WE# Control n/a Memory Type DRAM Refresh Rate Select Bits [2:0] These bits specify the divisor used to generate the DRAM refresh rate from the input clock (CLKI).
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Page 101 Epson Research and Development Vancouver Design Center 8.2.3 Panel/Monitor Configuration Registers Panel Type Register REG[02h] EL Panel Enable RW Panel Data Width Bit 1 n/a Panel Data Width Bit 0 Panel Data Color/Mono. Format Select Panel Select Dual/Single Panel Select TFT/ Passive LCD Panel Select bit 7 EL Panel Mode Enable When this bit = 1, EL Panel support mode is enabled.
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Page 102 Epson Research and Development Vancouver Design Center Horizontal Display Width Register REG[04h] n/a RW Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal Display Width Display Width Display Width Display Width Display Width Display Width Display Width Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 6-0 Horizontal Display Width Bits [6:0] These bits specify the LCD panel and/or the CRT horizontal display width as follows.
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Page 103 Epson Research and Development Vancouver Design Center HRTC/FPLINE Start Position Register REG[06h] n/a RW n/a bits 4-0 n/a HRTC/ FPLINE Start Position Bit 4 HRTC/ FPLINE Start Position Bit 3 HRTC/ FPLINE Start Position Bit 2 HRTC/ FPLINE Start Position Bit 1 HRTC/ FPLINE Start Position Bit 0 HRTC/FPLINE Start Position Bits [4:0] For CRT and TFT/D-TFD, these bits specify the delay from the start of the horizontal non-display period to the leading edge of the HRTC pulse and FPLINE pulse r
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Page 104 Epson Research and Development Vancouver Design Center Vertical Display Height Register 0 REG[08h] Vertical Display Height Bit 7 RW Vertical Display Height Bit 6 Vertical Display Height Bit 5 Vertical Display Height Bit 4 Vertical Display Height Bit 3 Vertical Display Height Bit 2 Vertical Display Height Bit 1 Vertical Display Height Bit 0 Vertical Display Height Register 1 REG[09h] n/a RW n/a REG[08h] bits 7-0 REG[09h] bits 1-0 n/a n/a n/a n/a Vertical Display Height Bit 9 Vertic
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Page 105 Epson Research and Development Vancouver Design Center VRTC/FPFRAME Start Position Register REG[0Bh] n/a RW VRTC/ FPFRAME Start Position Bit 5 n/a bits 5-0 VRTC/ FPFRAME Start Position Bit 4 VRTC/ FPFRAME Start Position Bit 3 VRTC/ FPFRAME Start Position Bit 2 VRTC/ FPFRAME Start Position Bit 1 VRTC/ FPFRAME Start Position Bit 0 VRTC/FPFRAME Start Position Bits [5:0] For CRT and TFT/D-TFD, these bits specify the delay in lines from the start of the vertical non-display period to the lea
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Page 106 Epson Research and Development Vancouver Design Center 8.2.4 Display Configuration Registers Display Mode Register REG[0Dh] SwivelView Enable RW Simultaneous Display Option Select Bit 1 Simultaneous Display Bit-per-pixel Option Select Select Bit 2 Bit 0 Bit-per-pixel Select Bit 1 Bit-per-pixel Select Bit 0 CRT Enable LCD Enable bit 7 SwivelView Enable When this bit = 1, all CPU accesses to the display buffer are translated to provide clockwise 90° hardware rotation of the display image.
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Page 107 Epson Research and Development Vancouver Design Center bits 4-2 Bit-per-pixel Select Bits [2:0] These bits select the color depth (bpp) for the displayed data. See “Section 10.1 Display Mode Formats” for details of how the pixels are mapped into the image buffer. Table 8-7: Bit-per-pixel Selection Bit-per-pixel Select Bits [2:0] Color Depth (bpp) 000 1 bpp 001 2 bpp 010 4 bpp 011 8 bpp 100 15 bpp 101 16 bpp 110 – 111 Reserved bit 1 CRT Enable This bit enables the CRT monitor.
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Page 108 Epson Research and Development Vancouver Design Center Screen 1 Display Start Address Register 0 REG[10h] RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Screen 1 Display Start Address Register 1 REG[11h] RW Start Address Start Address Start Address Start Address Start Address Start Address Start Address Start Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Screen
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Page 109 Epson Research and Development Vancouver Design Center Memory Address Offset Register 0 REG[16h] Memory Address Offset Bit 7 RW Memory Address Offset Bit 6 Memory Address Offset Bit 5 Memory Address Offset Bit 4 Memory Address Offset Bit 3 Memory Address Offset Bit 2 Memory Address Offset Bit 1 Memory Address Offset Bit 0 Memory Address Offset Register 1 REG[17h] n/a RW n/a REG[16h] bits 7-0 REG[17h] bits 2-0 n/a n/a n/a Memory Address Offset Bit 10 Memory Address Offset Bit 9 Mem
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Page 110 Epson Research and Development Vancouver Design Center 8.2.5 Clock Configuration Register Clock Configuration Register REG[19h] Reserved RW n/a bit 7 n/a n/a MCLK Divide Select n/a PCLK Divide Select Bit 1 PCLK Divide Select Bit 0 Reserved This bit must be set to 0. Note There must always be a source clock at CLKI. bit 2 MCLK Divide Select When this bit = 1 the MCLK frequency is half of its source frequency. When this bit = 0 the MCLK frequency is equal to its source frequency.
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Page 111 Epson Research and Development Vancouver Design Center bit 3 LCD Power Disable This bit is used to override the panel on/off sequencing logic. When this bit = 0 the LCDPWR output is controlled by the panel on/off sequencing logic. When this bit = 1 the LCDPWR output is directly forced to the off state. The LCDPWR “On/Off” polarity is configured by MD10 at the rising edge of RESET# (MD10 = 0 configures LCDPWR = 0 as the Off state; MD10 = 1 configures LCDPWR = 1 as the Off state).
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Page 112 Epson Research and Development Vancouver Design Center MD Configuration Readback Register 0 REG[1Ch] MD[7] Status RO MD[6] Status MD[5] Status MD[4] Status MD[3] Status MD[2] Status MD[1] Status MD[0] Status MD Configuration Readback Register 1 REG[1Dh] MD[15] Status RO MD[14] Status REG[1Ch] bits 7-0 REG[1Dh] bits 7-0 MD[13] Status MD[12] Status MD[11] Status MD[10] Status MD[9] Status MD[8] Status MD[15:0] Configuration Status These are read-only status bits for the MD[15:0] pi
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Page 113 Epson Research and Development Vancouver Design Center General IO Pins Configuration Register 1 REG[1Fh] n/a RW n/a n/a n/a n/a n/a n/a n/a This register position is reserved for future use. General IO Pins Control Register 0 REG[20h] n/a RW n/a n/a n/a GPIO3 Pin IO Status GPIO2 Pin IO Status GPIO1 Pin IO Status n/a bit 3 GPIO3 Pin IO Status When GPIO3 is configured as an output (see REG[1Eh]), a “1” in this bit drives GPIO3 high and a “0” in this bit drives GPIO3 low.
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Page 114 Epson Research and Development Vancouver Design Center Performance Enhancement Register 0 REG[22h] Reserved RW RC Timing Value Bit 1 RC Timing Value Bit 0 RAS# Precharge Timing Value Bit 1 RAS#-toCAS# Delay Value RAS# Precharge Timing Value Bit 0 Reserved Reserved Note Changing this register to non-zero value, or to a different non-zero value, should be done only when there are no read/write DRAM cycles.
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Page 115 Epson Research and Development Vancouver Design Center bit 4 RAS#-to-CAS# Delay Value (NRCD) This bit selects the DRAM RAS#-to-CAS# delay parameter, tRCD. This bit specifies the number (NRCD) of MCLK periods (TM) used to create tRCD. NRCD must be chosen to satisfy the RAS# access time, tRAC. Note, these formulae assume an MCLK duty cycle of 50 +/- 5%. NRCD = Round-Up((tRAC + 5)/TM - 1) =2 = Round-Up(tRAC/TM - 1) = Round-Up(tRAC/TM - 0.45) if EDO and NRP = 1 or 2 if EDO and NRP = 1.
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Page 116 Epson Research and Development Vancouver Design Center bits 1-0 Reserved These bits must be set to 0. Table 8-14: RAS Precharge Timing Select REG[22h] bits [3:2] 00 01 10 11 NRP 2 1.5 1 Reserved RAS# Precharge Width (tRP) 2 1.5 1 Reserved Optimal DRAM Timing The following table contains the optimally programmed values of NRC, NRP, and NRCD for different DRAM types, at maximum MCLK frequencies.
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Page 117 Epson Research and Development Vancouver Design Center bit 6-5 CPU to Memory Wait State Bits [1:0] These bits are used to optimize the handshaking between the host interface and the memory controller. The bits should be set according to the relationship between BCLK and MCLK – see the table below where TB and TM are the BCLK and MCLK periods respectively.
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Page 118 Epson Research and Development Vancouver Design Center Look-Up Table Data Register REG[26h] LUT Data Bit 3 RW LUT Data Bit 2 bits 7-4 LUT Data Bit 1 LUT Data Bit 0 n/a n/a n/a n/a LUT Data This register is used to read/write the RGB Look-Up Tables. This register accesses the entry at the pointer controlled by the Look-Up Table Address Register (REG[24h]) – see above. Accesses to the Look-Up Table Data Register automatically increment the pointer.
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Page 119 Epson Research and Development Vancouver Design Center REG[28] bits 7-0 REG[29] bits 1-0 Cursor X Position Bits [9:0] In Cursor mode, this 10-bit register is used to program the horizontal pixel position of the Cursor’s top left pixel. This register must be set to 0 in Ink mode. Note The Cursor X Position register must be set during VNDP (vertical non-display period). Check the VNDP status bit (REG[0Ah] bit 7) to determine if you are in VNDP, then update the register.
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Page 120 Epson Research and Development Vancouver Design Center Ink/Cursor Color 1 Register 0 REG[2Eh] Cursor Color 1 Bit 7 RW Cursor Color 1 Bit 6 Cursor Color 1 Bit 5 Cursor Color 1 Bit 4 Cursor Color 1 Bit 3 Cursor Color 1 Bit 2 Cursor Color 1 Bit 1 Cursor Color 1 Bit 0 Ink/Cursor Color 1 Register 1 REG[2Fh] Cursor Color 1 Bit 15 RW Cursor Color 1 Bit 14 REG[2E] bits 7:0 REG[2F] bits 7:0 Cursor Color 1 Bit 13 Cursor Color 1 Bit 12 Cursor Color 1 Bit 11 Cursor Color 1 Bit 10 Cursor Color
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Page 121 Epson Research and Development Vancouver Design Center Alternate FRM Register REG[31h] Alternate FRM Bit 7 bits 7-0 RW Alternate FRM Bit 6 Alternate FRM Bit 5 Alternate FRM Bit 4 Alternate FRM Bit 3 Alternate FRM Bit 2 Alternate FRM Bit 1 Alternate FRM Bit 0 Alternate Frame Rate Modulation Select Register that controls the alternate FRM scheme. When all bits are set to zero, the default FRM is selected.
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Page 122 Epson Research and Development Vancouver Design Center 9 Display Buffer The system addresses the display buffer through the CS#, M/R#, and AB[20:0] input pins. When CS# = 0 and M/R# = 1, the display buffer is addressed by bits AB[20:0].
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Page 123 Epson Research and Development Vancouver Design Center 9.1 Image Buffer The image buffer contains the formatted display mode data – see “Display Mode Data Formats”. The displayed image(s) could take up only a portion of this space; the remaining area may be used for multiple images – possibly for animation or general storage. See “Display Configuration” on page 124 for the relationship between the image buffer and the display. 9.
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Page 124 Epson Research and Development Vancouver Design Center 10 Display Configuration 10.1 Display Mode Data Format The following diagrams show the display mode data formats for a little-endian system.
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Page 125 Epson Research and Development Vancouver Design Center 15 bpp: P0 P1 P2 P3 P4 P5 P6 P7 5-5-5 RGB bit 7 bit 0 Byte 0 G02 G01 G00 B04 B03 B02 B01 B00 Byte 1 4 R04 R03 R02 R01 R00 G0 G03 Byte 2 G12 G11 G10 B14 B13 B12 B11 B10 Byte 3 4 R14 R13 R12 R11 R10 G1 G13 Pn = (Rn4-0, Gn 4-0, Bn4-0) Panel Display Display Memory Host Address 16 bpp: 5-6-5 RGB bit 7 P0 P1 P2 P3 P4 P5 P6 P7 bit 0 Byte 0 G02 G01 G00 B04 B03 B02 B01 B00 Byte 1 R04 R03 R02 R01 R00 G05 G04 G03 Byte 2 G12 G11 G1
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Page 126 Epson Research and Development Vancouver Design Center 10.2 Image Manipulation The figure below shows how Screen 1 and 2 images are stored in the image buffer and positioned on the display. Screen 1 and Screen 2 can be parts of a larger virtual image or images.
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Page 127 Epson Research and Development Vancouver Design Center 11 Look-Up Table Architecture The following figures are intended to show the display data output path only. 11.1 Monochrome Modes The green Look-Up Table (LUT) is used for all monochrome modes.
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Page 128 Epson Research and Development Vancouver Design Center 4 Bit-per-pixel Monochrome Mode Green Look-Up Table 256x4 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4-bit Grey Data FC FD FE FF 4 bit-per-pixel data from Image Buffer Figure 11-3: 4 Bit-per-pixel Monochrome Mode Data Output Path S1D13505 X23A-A-001-14 Hardware Functional Specification Issue Date: 01/02/02
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Page 129 Epson Research and Development Vancouver Design Center 11.
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Page 130 Epson Research and Development Vancouver Design Center 2 Bit-per-pixel Color Mode Red Look-Up Table 256x4 00 01 02 03 00 01 10 11 4-bit Red Data 00 01 10 11 4-bit Green Data 00 01 10 11 4-bit Blue Data FC FD FE FF Green Look-Up Table 256x4 00 01 02 03 FC FD FE FF Blue Look-Up Table 256x4 00 01 02 03 FC FD FE FF 2 bit-per-pixel data from Image Buffer Figure 11-5: 2 Bit-per-pixel Color Mode Data Output Path S1D13505 X23A-A-001-14 Hardware Functional Specification Issue Date: 01/02/02
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Page 131 Epson Research and Development Vancouver Design Center 4 Bit-per-pixel Color Mode Red Look-Up Table 256x4 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4-bit Red Data FC FD FE FF Green Look-Up Table 256x4 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4-bit Green Data FC FD FE FF Blue Look-Up Table 256x4 00 01 02 03 04 05 06 07 08
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Page 132 Epson Research and Development Vancouver Design Center 8 Bit-per-pixel Color Mode Red Look-Up Table 256x4 00 01 02 03 04 05 06 07 F8 F9 FA FB FC FD FE FF 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 4-bit Red Data 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 Green Look-Up Table 256x4 00 01 02 03 04 05 06 07 F8 F9 FA FB FC FD FE FF 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 4-bit Green
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Page 133 Epson Research and Development Vancouver Design Center 12 Ink/Cursor Architecture 12.1 Ink/Cursor Buffers The Ink/Cursor buffers contain formatted image data for the Ink Layer or Hardware Cursor. There may be several Ink/Cursor images stored in the display buffer but only one may be active at any given time. The active Ink/Cursor buffer is selected by the Ink/Cursor Start Address register (REG[30h]). This register defines the start address for the active Ink/Cursor buffer.
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Page 134 Epson Research and Development Vancouver Design Center The image data for pixel n, (An,Bn), selects the color for pixel n as follows: Table 12-2: Ink/Cursor Color Select (An,Bn) Color Comments 00 Color 0 Ink/Cursor Color 0 Register, (REG[2Dh],REG[2Ch]) 01 Color 1 Ink/Cursor Color 1 Register, (REG[2Fh],REG[2Eh]) 10 Background 11 Inverted Background Ink/Cursor is transparent – show background Ink/Cursor is transparent – show inverted background 12.3 Ink/Cursor Image Manipulation 12.3.
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Page 135 Epson Research and Development Vancouver Design Center 13 SwivelView™ 13.1 Concept Computer displays are refreshed in landscape – from left to right and top to bottom; computer images are stored in the same manner. When a display is used in SwivelView it becomes necessary to rotate the display buffer image by 90°. SwivelView rotates the image 90° clockwise as it is written to the display buffer.
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Page 136 Epson Research and Development Vancouver Design Center 13.2 Image Manipulation in SwivelView Display Start Address It can be seen from Figure 13-1 that the top left pixel of the display is not at the top left corner of the virtual image, i.e. it is non-zero.
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Epson Research and Development Vancouver Design Center Page 137 13.3 Physical Memory Requirement Because the programmer must now deal with a virtual display, the amount of image buffer required for a particular display mode has increased. The minimum amount of image buffer required is: Minimum Required Image Buffer (bytes) =(1024 × H) × 2 for 16 bpp mode =(1024 × H) for 8 bpp mode For single panel, the required display buffer size is the same as the image buffer required.
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Page 138 Epson Research and Development Vancouver Design Center Table 13-2 Minimum DRAM Size Required for SwivelView Panel Size Panel Type Color Single Mono 320 × 240 Color Dual Mono Color Single Mono 640 × 480 Color Dual Mono Color Single Mono 800 × 600 Color Dual Mono Display Mode 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp 8 bpp 16 bpp Sprite/Ink Display Half-Frame Minimum Layer Buffer Buffer Size Buf
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Page 139 Epson Research and Development Vancouver Design Center 14 Clocking 14.1 Maximum MCLK: PCLK Ratios Table 14-1: Maximum PCLK Frequency with EDO-DRAM Ink off on Display type NRC • Single Panel. • CRT. • Dual Monochrome/Color Panel with Half Frame Buffer Disabled. • Simultaneous CRT + Single Panel. • Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled.
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Page 140 Epson Research and Development Vancouver Design Center Table 14-2: Maximum PCLK Frequency with FPM-DRAM Display type NRC • Single Panel. • CRT. • Dual Monochrome/Color Panel with Half Frame Buffer Disabled. • Simultaneous CRT + Single Panel. • Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. 5, 4, 3 Ink off on Maximum PCLK allowed 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp MCLK • Dual Monochrome with Half Frame Buffer Enabled.
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Page 141 Epson Research and Development Vancouver Design Center 14.
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Page 142 Epson Research and Development Vancouver Design Center Table 14-3: Example Frame Rates with Ink Disabled (Continued) DRAM Type1 (Speed Grade) 60ns EDO-DRAM Display • Single Panel. • CRT. • Dual Mono/Color Panel with Half Frame Buffer Disabled.5 • Simultaneous CRT + Single Panel. • Simultaneous CRT + Dual Mono/Color Panel with Half Frame Buffer Disabled.5 800x6002 640x480 640x240 480x320 MClk = 33MHz NRC = 4 NRP = 1.5 NRCD = 2 320x240 • Dual Color with Half Frame Buffer Enabled.
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Page 143 Epson Research and Development Vancouver Design Center 4. Optimum frame rates for panels range from 60Hz to 150Hz. If the maximum refresh rate is too high for a panel, MCLK should be reduced or PCLK should be divided down. 5. Half Frame Buffer disabled by REG[1Bh] bit 0. 6. When setting a horizontal resolution greater than 767 pixels, with a color depth of 15/16 bpp, the Memory Offset Registers (REG[16h], REG[17h]) must be set to a virtual horizontal pixel resolution of 1024. 14.
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Page 144 Epson Research and Development Vancouver Design Center , Table 14-5: Total # MCLKs taken for Display refresh Display • • • • • Single Panel. CRT. Dual Monochrome/Color Panel with Half Frame Buffer Disabled. Simultaneous CRT + Single Panel. Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. MCLKs for Display Refresh 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp 4 5 7 11 19 • Dual Monochrome Panel with Half Frame Buffer Enabled.
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Page 145 Epson Research and Development Vancouver Design Center Table 14-6: Theoretical Maximum Bandwidth M byte/sec, Cursor/Ink disabled DRAM Type1 (Speed Grade) 640x480 Display • CRT. • Simultaneous CRT + Single Panel. • Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. 50ns • Single Panel. • Dual Monochrome/Color Panel with Half Frame Buffer Disabled. EDO-DRAM MCLK = 40MHz • Dual Monochrome Panel with Half Frame Buffer Enabled.
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Page 146 Epson Research and Development Vancouver Design Center Table 14-6: Theoretical Maximum Bandwidth M byte/sec, Cursor/Ink disabled (Continued) DRAM Type1 (Speed Grade) 640x480 Display • CRT. • Simultaneous CRT + Single Panel. • Simultaneous CRT + Dual Monochrome/Color Panel with Half Frame Buffer Disabled. 60ns • Single Panel. • Dual Monochrome/Color Panel with Half Frame Buffer Disabled. FPM-DRAM MCLK = 25MHz • Dual Monochrome with Half Frame Buffer Enabled.
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Page 147 Epson Research and Development Vancouver Design Center 15 Power Save Modes Three power save modes are incorporated into the S1D13505 to meet the important need for power reduction in the hand-held device market.
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Page 148 Epson Research and Development Vancouver Design Center 16 Mechanical Data Unit: mm 128-pin QFP15 surface mount package 16.0 ± 0.4 14.0 ± 0.1 96 65 16.0 ± 0.4 64 14.0 ± 0.1 97 Index 128 33 32 0.4 0.16 ± 0.1 1.4 ± 0.1 0.125 ± 0.1 1 0.1 0~10° 0.5 ± 0.2 1.
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S1D13505 Embedded RAMDAC LCD/CRT Controller Programming Notes and Examples Document Number: X23A-G-003-07 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-003-07 Programming Notes and Examples Issue Date: 01/02/05
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Page 3 Epson Research and Development Vancouver Design Center Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 Memory Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Display Buffer Location . . . . . . . . . . . . . . . .
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Page 4 Epson Research and Development Vancouver Design Center 7.3.2 Reg[29h] And Reg[2Bh] . . . . . . . . . . . . 7.3.3 Reg [30h] . . . . . . . . . . . . . . . . . . . . 7.3.4 No Top/Left Clipping on Hardware Cursor . . 7.4 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 SwivelView . . . . . . . . . . 8.1 Introduction To SwivelView 8.2 S1D13505 SwivelView . . 8.3 Registers . . . . . . . . 8.4 Limitations . . . . . . . 8.5 Examples . .
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Page 5 Epson Research and Development Vancouver Design Center 12 Sample Code . . . . . . . . . . . . . . . . . . . . . . . 12.1 Introduction . . . . . . . . . . . . . . . . . . 12.1.1 Sample code using the S1D13505 HAL API . . . . 12.1.2 Sample code without using the S1D13505 HAL API 12.1.3 Header Files . . . . . . . . . . . . . . . . . . . . . Appendix A A.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Page 6 S1D13505 X23A-G-003-07 Epson Research and Development Vancouver Design Center Programming Notes and Examples Issue Date: 01/02/05
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Page 7 Epson Research and Development Vancouver Design Center List of Tables Table 2-1: S1D13505 Initialization Sequence . . . . . . . . . . . . . . . . . Table 4-1: Look-Up Table Configurations . . . . . . . . . . . . . . . . . . . Table 4-2: Recommended LUT Values for 1 Bpp Color Mode . . . . . . . . . Table 4-3: Example LUT Values for 2 Bpp Color Mode . . . . . . . . . . . .
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Page 9 Epson Research and Development Vancouver Design Center List of Figures Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 3-6: Figure 5-1: Figure 5-2: Figure 5-3: Figure 5-4: Figure 5-5: Figure 5-6: Figure 5-7: Figure 11-1: Pixel Storage for 1 Bpp (2 Colors/Gray Shades) in One Byte of Display Buffer . . . Pixel Storage for 2 Bpp (4 Colors/Gray Shades) in One Byte of Display Buffer . . . Pixel Storage for 4 Bpp (16 Colors/Gray Shades) in One Byte of Display Buffer . .
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Page 11 Epson Research and Development Vancouver Design Center 1 Introduction This guide describes how to program the S1D13505 Embedded RAMDAC LCD/CRT Controller. The guide presents the basic concepts of the LCD/CRT controller and provides methods to directly program the registers. It explains some of the advanced techniques used and the special features of the S1D13505. The guide also introduces the Hardware Abstraction Layer (HAL), which is designed to simplify the programming of the S1D13505.
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Page 12 Epson Research and Development Vancouver Design Center 2 Initialization This section describes how to initialize the S1D13505. Sample code for performing initialization of the S1D13505 is provided in the file init13505.c which is available on the internet at http://www.eea.epson.com. S1D13505 initialization can be broken into three steps. First, enable the S1D13505 controller (if necessary identify the specific controller). Next, set all the registers to their initial values.
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Page 13 Epson Research and Development Vancouver Design Center Table 2-1: S1D13505 Initialization Sequence (Continued) Register Value Notes [06] 0000 0000 FPLINE start position - only required for CRT or TFT/D-TFD [07] 0000 0000 FPLINE polarity set to active high [08] 1110 1111 [09] 0000 0000 Vertical display size = Reg[09][08] + 1 = 0000 0000 1110 1111 + 1 = 239+1 = 240 lines (total height/2 for dual panels) [0A] 0011 1000 Vertical non-display size = Reg[0A] + 1 = 57 + 1 = 58 lines [0B]
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Page 14 Epson Research and Development Vancouver Design Center Table 2-1: S1D13505 Initialization Sequence (Continued) Register Value [24] 0000 0000 [26] 0000 0000 [27] 0000 0000 [28] 0000 0000 [29] 0000 0000 [2A] 0000 0000 [2B] 0000 0000 [2C] 0000 0000 [2D] 0000 0000 [2E] 0000 0000 [2F] 0000 0000 [30] 0000 0000 [31] 0000 0000 Notes The remaining register control operation of the LUT and hardware cursor/ink layer.
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Epson Research and Development Vancouver Design Center Page 15 2.1 Miscellaneous This section of the notes contains recommendations which can be set at initialization time to improve display image quality. At high color depths the display FIFO introduces two conditions which must be accounted for in software. Simultaneous display while using a dual passive panel introduces another possible register change.
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Page 16 Epson Research and Development Vancouver Design Center 3 Memory Models The S1D13505 is capable of several color depths. The memory model for each color depth is packed pixel. Packed pixel data changes with each color depth from one byte containing eight consecutive pixels up to two bytes being required for one pixel. 3.1 Display Buffer Location The S1D13505 supports either a 512k byte or 2M byte display buffer. The display buffer is memory mapped and can be accessed directly by software.
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Page 17 Epson Research and Development Vancouver Design Center 3.1.2 Memory Organization for Two Bit-Per-Pixel (4 Colors/Gray Shades) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Bit 1 Pixel 0 Bit 0 Pixel 1 Bit 1 Pixel 1 Bit 0 Pixel 2 Bit 1 Pixel 2 Bit 0 Pixel 3 Bit 1 Pixel 3 Bit 0 Figure 3-2: Pixel Storage for 2 Bpp (4 Colors/Gray Shades) in One Byte of Display Buffer In this memory format each byte of display buffer contains four adjacent pixels.
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Page 18 Epson Research and Development Vancouver Design Center 3.1.4 Memory Organization for Eight Bit-Per-Pixel (256 Colors/16 Gray Shades) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 One Pixel Figure 3-4: Pixel Storage for 8 Bpp (256 Colors/16 Gray Shades) in One Byte of Display Buffer In eight bit-per-pixel mode each byte of display buffer represents one pixel on the display. At this color depth the read-modify-write cycles of the lessor pixel depths are eliminated.
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Page 19 Epson Research and Development Vancouver Design Center 3.1.
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Page 20 Epson Research and Development Vancouver Design Center 4 Look-Up Table (LUT) This section is supplemental to the description of the Look-Up Table architecture found in the S1D13505 Hardware Functional Specification. Covered here is a review of the LUT registers, recommendations for the color and gray shade LUT values, and additional programming considerations for the LUT. Refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx for more detail.
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Page 21 Epson Research and Development Vancouver Design Center 4.2 Look-Up Table Organization • The Look-Up Table treats the value of a pixel as an index into an array of colors or gray shades. For example, a pixel value of zero would point to the first LUT entry; a pixel value of 7 would point to the eighth LUT entry. • The value inside each LUT entry represents the intensity of the given color or gray shade. This intensity can range in value between 0 and 0Fh.
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Page 22 Epson Research and Development Vancouver Design Center Color Modes In color display modes, depending on the color depth, 2 through 256 index entries are used. The selection of which entries are used is automatic. 1 bpp color When the S1D13505 is configured for 1 bpp color mode, the LUT is limited to the first two entries. The two LUT entries can be any two RGB values but are typically set to black-andwhite. Each byte in the display buffer contains 8 bits, each pertaining to adjacent pixels.
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Page 23 Epson Research and Development Vancouver Design Center 4 bpp color When the S1D13505 is configured for 4 bpp color mode the first 16 entries in the LUT are used. Each byte in the display buffer contains two adjacent pixels. The upper and lower nibbles of the byte are used as indices into the LUT. The following table shows LUT values that will simulate those of a VGA operating in 16 color mode.
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Page 24 Epson Research and Development Vancouver Design Center 8 bpp color When the S1D13505 is configured for 8 bpp color mode all 256 entries in the LUT are used. Each byte in display buffer corresponds to one pixel and is used as an index value into the LUT. The S1D13505 LUT has four bits (16 intensities) of intensity control per primary color while a standard VGA RAMDAC has six bits (64 intensities).
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Page 25 Epson Research and Development Vancouver Design Center Table 4-5: Suggested LUT Values to Simulate VGA Default 256 Color Palette (Continued) Index 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F R E0 F0 00 40 70 B0 F0 F0 F0 F0 F0 F0 F0 F0 F0 B0 70 40 00 00 00 00 00 00 00 00 70 90 B0 D0 F0 F0 F0 F0 G E0 F0 00 00 00 00 00 00 00 00 00 40 70 B0 F0 F0 F0 F0 F0 F0 F0 F0 F0 B0 70 40 70 70 70 70 70 70 70 70 B E0 F0 F0 F0 F0 F0 F0 B0 70 40 00 00 00 0
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Page 26 Epson Research and Development Vancouver Design Center Gray Shade Modes This discussion of gray shade/monochrome modes only applies to the panel interface. Monochrome mode is selected when register [01] bit 2 = 0. In this mode the output value to the panel is derived solely from the green component of the LUT. The CRT image will continue to be formed from all three (RGB) Look-Up Table components.
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Page 27 Epson Research and Development Vancouver Design Center 4 bpp gray shade The 4 bpp gray shade mode uses the first 16 LUT elements. The remaining indices of the LUT are unused. Table 4-8: Suggested LUT Values for 4 Bpp Gray Shade Index 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 ...
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Page 28 Epson Research and Development Vancouver Design Center 16 bpp gray The Look-Up Table is bypassed at this color depth, hence programming the LUT is not necessary. As with 8 bpp there are limitations to the colors which can be displayed. In this mode the four most significant bits of green are used to set the absolute intensity of the image. Four bits of green resolves to 16 colors. Now however, each pixel requires two bytes.
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Epson Research and Development Vancouver Design Center Page 29 5 Advanced Techniques This section presents information on the following: • virtual display • panning and scrolling • split screen display 5.1 Virtual Display Virtual display refers to the situation where the image to be viewed is larger than the physical display. This can be in the horizontal, the vertical or both dimensions. To view the image, the display is used as a window (or viewport) into the display buffer.
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Page 30 Epson Research and Development Vancouver Design Center Seldom are the maximum sizes used. Figure 5-1: “Viewport Inside a Virtual Display,” depicts a more typical use of a virtual display. The display panel is 320x240 pixels, an image of 640x480 pixels can be viewed by navigating a 320x240 pixel viewport around the image using panning and scrolling. 320x240 Viewport 640x480 “Virtual” Display Figure 5-1: Viewport Inside a Virtual Display 5.1.
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Page 31 Epson Research and Development Vancouver Design Center 5.1.2 Examples Example 1: Determine the offset value required for 800 pixels at a color depth of 8 bpp. At 8 bpp each byte contains one pixel, therefore each word contains two pixels. pixels_per_word = 16 / bpp = 16 / 8 = 2 Using the above formula. offset = pixels_per_line / pixels_per_word = 800 / 2 = 400 = 190h words Register [17h] would be set to 01h and register [16h] would be set to 90h.
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Page 32 Epson Research and Development Vancouver Design Center Both panning and scrolling are performed by modifying the start address register. The start address refers to the word offset in the display buffer where the image will start being displayed from. At color depths less than 15 bpp a second register, the pixel pan register, is required for smooth pixel level panning. Internally, the S1D13505 latches different signals at different times.
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Page 33 Epson Research and Development Vancouver Design Center Table 5-1: Number of Pixels Panned Using Start Address Color Depth (bpp) 1 2 4 8 15 16 Pixels per Word 16 8 4 2 1 1 Number of Pixels Panned 16 8 4 2 1 1 REG[18h] Pixel Panning Register Screen 2 Screen 2 Screen 2 Screen 2 Screen 1 Screen 1 Screen 1 Screen 1 Pixel Pan Bit Pixel Pan Bit Pixel Pan Bit Pixel Pan Bit Pixel Pan Bit Pixel Pan Bit Pixel Pan Bit Pixel Pan Bit 3 2 1 0 3 2 1 0 Figure 5-4: Pixel Panning Register The pixel panning regis
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Page 34 Epson Research and Development Vancouver Design Center The following pans to the right by one pixel in 4 bpp display mode. 1. This is a pan to the right. Increment pan_value. pan_value = pan_value + 1 2. Mask off the values from pan_value for the pixel panning and start address register portions. In this case, 4 bpp, the lower two bits are the pixel panning value and the upper bits are the start address.
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Page 35 Epson Research and Development Vancouver Design Center 5.3 Split Screen Occasionally the need arises to display two distinct images on the display. For example, we may write a game where the main play area will rapidly update and we want a status display at the bottom of the screen. The Split Screen feature of the S1D13505 allows a programmer to setup a display for such an application.
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Page 36 Epson Research and Development Vancouver Design Center These two registers form a value known as the line compare. When the line compare value is equal to or greater than the physical number of lines being displayed there is no visible effect on the display. When the line compare value is less than the number of physically displayed lines, display operation works like this: 1.
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Page 37 Epson Research and Development Vancouver Design Center 5.3.2 Examples Example 6: Display 380 scanlines of image 1 and 100 scanlines of image 2. Image 2 is located immediately after image 1 in the display buffer. Assume a 640x480 display and a color depth of 1 bpp. 1. The value for the line compare is not dependent on any other setting so we can set it immediately (380 = 17Ch). Write the line compare registers [0Fh] with 01h and register [0Eh] with 7Ch. 2.
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Page 38 Epson Research and Development Vancouver Design Center 6 LCD Power Sequencing and Power Save Modes The S1D13505 design includes a pin (LCDPWR) which may be used to control an external LCD bias power supply. If the hardware design makes use of LCDPWR, automatic LCD power sequencing and power save modes are available to the programmer. If LCDPWR is not used to control an external LCD bias power supply, this section is not applicable. 6.
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Page 39 Epson Research and Development Vancouver Design Center Setting the LCD Enable bit to 0 causes the S1D13505 to disable the LCD display. The following sequence of events occurs: 1. Disables the LCD power. 2. Counts 128 frames to wait for the LCD bias power supply to discharge. 3. Disables the LCD signals.
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Page 40 Epson Research and Development Vancouver Design Center Delay Too Long To shorten 128 frame delay on LCDPWR. 1. Set REG[23h] bit 7 to 1 - Blanks screen by disabling the FIFO. 2. Set REG[04h] to 3 (changes display width to 32 pixels) Set REG[08h] to 0 (changes display height to 1 line) - This changes the display resolution to minimum (32x1). 3. Set REG[1Ah] bit 0 to 0 - Enables power save mode. 4.
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Page 41 Epson Research and Development Vancouver Design Center 6.2.1 Registers REG[1Ah] Power Save Configuration Register Power Save Status (RO) n/a n/a n/a LCD Power Disable Suspend Refresh Select Bit 1 Suspend Refresh Select Bit 0 Software Suspend Mode Enable The Software Suspend Mode Enable bit initiates Software suspend when set to 1. Setting the bit back to 0 returns the controller back to normal mode.
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Page 42 Epson Research and Development Vancouver Design Center 6.3 Hardware Power Save The S1D13505 supports a hardware suspend power save mode. This mode is not programmable by software. It is controlled directly by the S1D13505 SUSPEND# pin. While hardware suspend is enabled the following conditions apply.
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Epson Research and Development Vancouver Design Center Page 43 7 Hardware Cursor/Ink Layer 7.1 Introduction The S1D13505 provides hardware support for a cursor or an ink layer. These features are mutually exclusive and therefore only one or the other may be active at any given time. A hardware cursor improves video throughput in graphical operating systems by offloading much of the work typically assigned to software. Take the actions which must be performed when the user moves the mouse.
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Page 44 Epson Research and Development Vancouver Design Center 7.2 Registers There are a total of eleven registers dedicated to the operation of the hardware cursor/ink layer. Many of the registers need only be set once. Others, such as the positional registers, will be updated frequently.
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Page 45 Epson Research and Development Vancouver Design Center REG[2Ah] Cursor Y Position Register 0 Cursor Y Position bit 7 Cursor Y Position bit 6 Cursor Y Position bit 5 Cursor Y Position bit 4 Cursor Y Position bit 3 Cursor Y Position bit 2 Cursor Y Position bit 1 Cursor Y Position bit 0 n/a n/a n/a Cursor Y Position bit 9 Cursor Y Position bit 8 REG[2Bh] Cursor Y Position Register 0 Reserved n/a n/a Registers [2Ah] and [2Bh] control the vertical position of the hardware cursor.
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Page 46 Epson Research and Development Vancouver Design Center Note Bit 7 is write only, when reading back the register this bit reads a '0'. Table 7-2: Cursor/Ink Start Address Encoding Ink/Cursor Start Address Bits [7:0] Start Address (Bytes) 0 Display Buffer Size - 1024 1 - FFh Display Buffer Size - (n * 8192) 7.3 Limitations There are limitations for using the hardware cursor/ink layer which should be noted. 7.3.
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Page 47 Epson Research and Development Vancouver Design Center 8 SwivelView 8.1 Introduction To SwivelView LCD panels are typically designed with row and column drivers mounted such that the panel's horizontal size is larger than the vertical size. These panels are typically referred to as “Landscape” panels. A minority of panels have the row and column drivers mounted such that the vertical size is larger than the horizontal size. These panels are typically referred to as “Portrait” panels.
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Page 48 Epson Research and Development Vancouver Design Center REG[0Dh] Display Mode Register SwivelView Enable Simultaneous Display Option Select Bit 1 Simultaneous Display Bit-Per-Pixel Option Select Select Bit 2 Bit 0 Bit-Per-Pixel Select Bit 1 Bit-Per-Pixel Select Bit 0 CRT Enable LCD Enable Step two involves setting the screen 1 start address registers. Set to 1024 - width for 16 bpp modes and to (1024 - width) / 2 for 8 bpp modes.
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Epson Research and Development Vancouver Design Center Page 49 Note Drawing into the Hardware Cursor/Ink Layer with SwivelView enabled does not work without some form of address manipulation. The easiest way to ensure correct cursor/ink images is to disable SwivelView, draw in the cursor/ink memory, then re-enable SwivelView. While writing the cursor/ink memory each pixel must be transformed to its rotated position. 8.
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Page 50 Epson Research and Development Vancouver Design Center b) Loop waiting for the end of vertical non-display. do register = ReadRegister(0Ah) while (80h == (register & 80h)); c) Write the new start address. SetRegister(REG_SCRN1_DISP_START_ADDR0, (BYTE) (dwAddr & FFh)); SetRegister(REG_SCRN1_DISP_START_ADDR1, (BYTE)((dwAddr >> 8) & FFh)); SetRegister(REG_SCRN1_DISP_START_ADDR2, (BYTE)((dwAddr >> 16) & 0Fh)); do register = ReadRegister(0Ah) while (80h == (register & 80h)); 4.
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Epson Research and Development Vancouver Design Center Page 51 9 CRT Considerations 9.1 Introduction The S1D13505 is capable of driving either an LCD panel, or a CRT display, or both simultaneously. As display devices, panels tend to be lax in their horizontal and vertical timing requirements. CRT displays often cannot vary by more than a very small percentage in their timing requirements before the image is degraded. Central to the following sections are VESA timings.
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Page 52 Epson Research and Development Vancouver Design Center 10 Identifying the S1D13505 The S1D13505 can only be identified once the host interface has been enabled. The steps to identify the S1D13505 are: 1. If using an ISA evaluation board in a PC follow steps a. and b. a. If a reset has occurred, confirm that 16-bit mode is enabled by writing to address F8 0000h. b. If hardware suspend is enabled then disable the suspend by writing to address F0 0000h. 2.
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Epson Research and Development Vancouver Design Center Page 53 11 Hardware Abstraction Layer (HAL) 11.1 Introduction The HAL is a processor independent programming library provided by Epson. The HAL was developed to aid the implementation of internal test programs, and provides an easy, consistent method of programming the S1D13505 on different processor platforms. The HAL also allows for easier porting of programs between S1D1350X products.
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Page 54 Epson Research and Development Vancouver Design Center Within the Regs array in the structure are all the registers defined in the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx. Using the 13505CFG.EXE utility you can adjust the content of the registers contained in HAL_STRUCT to allow for different LCD panel timing values and other default settings used by the HAL.
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Page 55 Epson Research and Development Vancouver Design Center Table 11-1: HAL Functions (Continued) Function Description seGetLastUsableByte Determine the offset of the last unreserved usable byte in the display buffer seGetBytesPerScanline Determine the number of bytes or memory consumed per scan line in current mode seGetScreenSize Determine the height and width of the display surface in pixels seSelectBusWidth Select the bus width on the ISA evaluation card seGetHostBusWidth Determine the b
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Page 56 Epson Research and Development Vancouver Design Center Table 11-1: HAL Functions (Continued) Function Description seCursorOn Enable the cursor seCursorOff Disable the cursor seGetCursorStartAddr Determine the offset of the first byte of cursor memory in the display buffer (landscape mode) seMoveCursor Move the cursor to the (x.
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Page 57 Epson Research and Development Vancouver Design Center Return Value: ERR_OK Example: - operation completed with no problems seRegisterDevice( &HalInfo, &DeviceId); Note No S1D13505 registers are changed by calling seRegisterDevice(). seRegisterDevice() MUST be called before any other HAL functions. int seInitHal(void) Description: This function initializes the variables used by the HAL library. This function or seRegisterDevice() must be called once when an application starts.
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Page 58 Epson Research and Development Vancouver Design Center int seSetDisplayMode(int DevID, int DisplayMode, int flags) Description: This routine sets the S1D13505 registers according to the values contained in the HAL_STRUCT register section. Setting all the registers means that timing, display surface dimensions, and all other aspects of chip operation are set with this call, including loading default values into the color Look-Up Tables (LUTs).
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Page 59 Epson Research and Development Vancouver Design Center For the S1D13505 the return values are currently: ID_S1D13505_REV0 ID_UNKNOWN Other HAL libraries will return their respective controller IDs upon detection of their controller. Return Value: ERR_OK - operation completed with no problems ERR_UNKNOWN_DEVICE - returned when pID returns ID_UNKNOWN. (The HAL was unable to identify the display controller).
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Page 60 Epson Research and Development Vancouver Design Center Parameters: DevID pSize Return Value: ERR_OK - registered device ID - pointer to a DWORD to receive the size - the operation completed successfully Note Memory size is only checked when calling seRegisterDevice(), seSetDisplayMode() or seSetInit(). Afterwards, the memory size is stored and made available through seGetMemSize().
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Page 61 Epson Research and Development Vancouver Design Center When the display is in portrait mode the dimensions will be swapped. (i.e. a 640x480 display in portrait mode will return a width and height of 480 and 640, respectively).
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Page 62 Epson Research and Development Vancouver Design Center To quickly blank the display, use seDisplayFifo() instead of seDisplayEnable(). Enabling and disabling the display FIFO is much faster, allowing full CPU bandwidth to the display buffer.
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Page 63 Epson Research and Development Vancouver Design Center Description: This function prepares the system for split screen operation. In order for split screen to function the starting address in the display buffer for the upper portion (screen 1), and the lower portion (screen 2) must be specified. Screen 1 is always displayed above screen 2 on the display regardless of the location of their respective starting addresses.
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Page 64 Epson Research and Development Vancouver Design Center Return Value: ERR_OK - operation completed with no problems ERR_HAL_BAD_ARG - returned in three situations 1) the virtual width (VirtX) is greater than the largest attainable width The maximum allowable xVirt is 7FFh * (16 / bpp)) 2) the virtual width is less than the physical width, or 3) the maximum number of lines is less than the physical number of lines Note The system must have been properly initialized prior to calling seVirtInit() int
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Page 65 Epson Research and Development Vancouver Design Center Parameters: DevID Index Value Return Value: ERR_OK - registered device ID - register index to set - value to write to the register - operation completed with no problems int seSetDwordReg(int DevID, int Index, DWORD Value) Description: Writes DWORD sized Value to the register specified by Index.
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Page 66 Epson Research and Development Vancouver Design Center Parameters: DevID Offset Value Count - registered device ID - offset from start of the display buffer - BYTE value to write - number of bytes to write Return Value: ERR_OK - operation completed with no problems ERR_HAL_BAD_ARG - if the value for Offset is greater than the amount of installed memory. Note If offset + count > memory size, this function will limit the writes to the end of memory.
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Page 67 Epson Research and Development Vancouver Design Center Parameters: DevID Offset pByte - registered device ID - offset, in bytes, from start of the display buffer - return value of the display buffer location. Return Value: ERR_OK - operation completed with no problems ERR_HAL_BAD_ARG - if the value for Offset is greater than the amount of installed memory.
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Page 68 Epson Research and Development Vancouver Design Center l Count Return Value: ERR_OK lut[x][1] == GREEN component ut[x][2] == BLUE component - the number of LUT entries to write. - operation completed with no problems int seGetLut(int DevID, BYTE *pLUT, int Count) Description: This routine reads one or more LUT entries and puts the result in the byte array pointed to by pLUT. A Look-Up Table entry consists of three bytes, one each for Red, Green, and Blue.
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Page 69 Epson Research and Development Vancouver Design Center registers are changed and the Look-Up Table is set its default value. This call is similar to a mode set call on a standard VGA.
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Page 70 Epson Research and Development Vancouver Design Center Parameters: DevID x y pColor Return Value: ERR_OK - Registered device ID - horizontal coordinate of the pixel (starting from 0) - vertical coordinate of the pixel (starting from 0) - at 1, 2, 4, and 8 bpp pColor points to an index into the LUT. At 15 and 16 bpp pColor points to the color directly (i.e. rrrrrggggggbbbbb for 16 bpp) - operation completed with no problems.
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Page 71 Epson Research and Development Vancouver Design Center Description: This routine draws an ellipse with the center located at (xc,yc). The xr and yr parameters specify the x any y radii, in pixels, respectively. The ellipse will be drawn in the color specified in 'Color'.
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Page 72 Epson Research and Development Vancouver Design Center When this call returns the cursor is enabled, the cursor image is transparent and ready to be drawn. Parameters: DevID Return Value: ERR_OK - a registered device ID - operation completed with no problems int seCursorOn(int DevID) Description: This function enables the cursor after it has been disabled through a call to seCursorOff(). After enabling the cursor will have the same shape and position as it did prior to being disabled.
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Page 73 Epson Research and Development Vancouver Design Center Parameters: DevID Index Color - a registered device ID - the cursor index to set. Valid values are 0 and 1 - a DWORD value which hold the requested color Return Value: ERR_OK - operation completed with no problems ERR_FAILED- returned if Index if other than 0 or 1 int seSetCursorPixel(int DevID, long x, long y, DWORD Color) Description: Draws a single pixel into the hardware cursor.
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Page 74 Epson Research and Development Vancouver Design Center Parameters: DevID (x1,y1) (x2,y2) Color SolidFill Return Value: ERR_OK - a registered device ID - upper left corner of the rectangle (in pixels) - lower right corner of the rectangle (in pixels) - a 0 to 3 value to draw the rectangle with - flag for filling the rectangle interior - if equal to 0 then outline the rectangle; if not equal to 0 then fill the rectangle with Color - operation completed with no problems int seDrawCursorEllipse(in
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Page 75 Epson Research and Development Vancouver Design Center 11.5.7 Ink Layer The functions in this section support the hardware ink layer. Overall these functions are nearly identical to the hardware cursor routines. In fact the same S1D13505 hardware is used for both features which means that only the cursor or the ink layer can be active at any given time.
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Page 76 Epson Research and Development Vancouver Design Center int seSetInkColor(int DevID, int Index, DWORD Color) Description: Sets the color of the specified ink/cursor index to 'Color'. The user definable hardware cursor colors are sixteen bit 5-6-5 RGB colors. The hardware ink layer image is always 2 bpp or four colors. Two of the colors are defined to be transparent and inverse. This leaves two colors which are user definable.
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Page 77 Epson Research and Development Vancouver Design Center The value of 'Color' must be 0 to 3. Values 0 and 1 refer to the two user definable colors. If 'Color' is 2 then the pixel will be transparent and if the value is 3 the pixel will be an inversion of the underlying screen color. Parameters: DevID (x1,y1) (x2.
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Page 78 Epson Research and Development Vancouver Design Center 11.5.8 Power Save This section covers the HAL functions dealing with the Power Save features of the S1D13505. int seSWSuspend(int DevID, BOOL Suspend) Description: Causes the S1D13505 to enter software suspend mode. When software suspend mode is engaged the display is disabled and display buffer is inaccessible. In this mode the registers and the LUT are accessible.
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Epson Research and Development Vancouver Design Center Page 79 For example, when building HELLOAPP.EXE for the x86 16-bit platform, you need the HELLOAPP source files, the 13505HAL library and its include files, and some Standard C library functions (which in this case would be supplied by the compiler as part of its runtime library). As this is a DOS .EXE application, you do not need to supply start-up code that sets up the chip selects or interrupts, etc...
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Page 80 Epson Research and Development Vancouver Design Center 11.6.2 Building the HAL library for the target example Building the HAL for the target example is less complex because the code is written in C and requires little platform specific adjustment. The nmake makefile for our example is makesh3.mk.This makefile contains the rules for building sh3 objects, the files list for the library and the library creation rules. The Gnu compiler tools are pointed to by TOOLDIR.
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Page 81 Epson Research and Development Vancouver Design Center { printf("\r\nERROR: Unable to register device with HAL\r\n"); return -1; } /* ** Init the SED1355 with the defaults stored in the HAL_STRUCT */ if (seSetInit(DevId) != ERR_OK) { printf("\r\nERROR: Unable to initialize the SED1355\r\n"); return -1; } /* ** Determine the screen size */ if (seGetScreenSize(DevId, &width, &height) != ERR_OK) { printf("\r\nERROR: Unable to get screen size\r\n"); return -1; } /* ** Determine the Bpp mode, and set c
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Page 82 Epson Research and Development Vancouver Design Center color_blue = BLUE16BPP; break; } /* ** Draw a Blue line from top left hand corner to bottom right hand corner */ if (seDrawLine(DevId, 0,0, width-1, height-1, color_blue) != ERR_OK) { printf("\r\nERROR: Unable to draw line\r\n"); return -1; } /* ** Delay for 2 seconds and then draw a filled rectangle */ seDelay(DevId, (DWORD)2); /* ** Centre the rectangle at 1/4 x,y and 3/4 x,y */ x1 = width/4; x2 = width/2 + x1; y1 = height/4; y2 = height/2 +
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Epson Research and Development Vancouver Design Center Page 83 /* ** Delay for 2 seconds */ seDelay(DevId, (DWORD)2); /* ** Move the cursor */ seMoveCursor(DevId, width-1-63, 0); return 0; } Programming Notes and Examples Issue Date: 01/02/05 S1D13505 X23A-G-003-07
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Page 84 Epson Research and Development Vancouver Design Center 12 Sample Code 12.1 Introduction There are two included examples of programming the S1D13505 color graphics controller. First is a demonstration using the HAL library and the second without. These code samples are for example purposes only. Lastly, are three header files that may make some of the structures used clearer. 12.1.
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Page 85 Epson Research and Development Vancouver Design Center ** This step sets up the HAL for use but does not access the 1355. */ switch (seRegisterDevice(&HalInfo, &Device)) { case ERR_OK: break; case HAL_DEVICE_ERR: printf("\nERROR: Too many devices registered."); exit(1); default: printf("\nERROR: Could not register SED1355 device."); exit(1); } /* ** Identify that this is indeed an SED1355. */ seGetId( Device, &ChipId); if (ID_SED1355F0A != ChipId) { printf("\nERROR: Did not detect SED1355.
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Page 86 Epson Research and Development Vancouver Design Center ** The background must be set to transparent. */ seInitCursor(Device); seDrawCursorRect(Device, 0, 0, 63, 63, 2, TRUE); /* ** Set the first user definable color to black and ** the second user definable color to white. */ seSetCursorColor(Device, 0, 0); seSetCursorColor(Device, 1, 0xFFFFFFFF); /* ** Draw a hollow rectangle around the cursor and move ** the cursor to 101,101.
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Page 87 Epson Research and Development Vancouver Design Center ** 3) The pointer assignment for the register offset does not work on ** x86 16 bit platforms. ** **--------------------------------------------------------------------------** Copyright (c) 1998 Epson Research and Development, Inc. ** All Rights Reserved. **=========================================================================== */ /* ** Note that only the upper four bits of the LUT are actually used.
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Page 88 0x00, 0xF0, 0x00, 0x10, 0xF0, 0x00, 0x40, 0xF0, 0x00, 0x50, 0xF0, 0x00, 0x80, 0xF0, 0x00, 0x90, 0xF0, 0x00, 0xC0, 0xF0, 0x00, 0xD0, 0xF0, 0x00, /* Yellow (red and green) to red */ 0xF0, 0xF0, 0x00, 0xF0, 0xE0, 0x00, 0xF0, 0xB0, 0x00, 0xF0, 0xA0, 0x00, 0xF0, 0x70, 0x00, 0xF0, 0x60, 0x00, 0xF0, 0x30, 0x00, 0xF0, 0x20, 0x00, /* Red to magenta (blue and red) */ 0xF0, 0x00, 0x00, 0xF0, 0x00, 0x10, 0xF0, 0x00, 0x40, 0xF0, 0x00, 0x50, 0xF0, 0x00, 0x80, 0xF0, 0x00, 0x90, 0xF0, 0x00, 0xC0, 0xF0, 0x00, 0xD0,
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Page 89 Epson Research and Development Vancouver Design Center #define REGISTER_OFFSET ((unsigned char *) 0x14000000) /* ** DISP_MEM_OFFSET points to the starting address of the display buffer memory */ #define DISP_MEM_OFFSET ((unsigned char *) 0x4000000) /* ** DISP_MEMORY_SIZE is the size of display buffer memory */ #define DISP_MEMORY_SIZE 0x200000 /* ** Calculate the value to put in Ink/Cursor Start Address Select Register ** Offset = (DISP_MEM_SIZE - (X * 8192) ** We want the offset to be just past t
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Page 90 Epson Research and Development Vancouver Design Center /* ** Step 4: Set Performance Enhancement 0 register */ *(pRegs + 0x22) = 0x24; /* 0010 0100 */ /* ** Step 5: Set the rest of the registers in order. */ /* ** Register 2: Panel Type - 16-bit, format 1, color, dual, passive.
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Epson Research and Development Vancouver Design Center Page 91 ** Register A: Vertical Non-Display Period (VNDP) ** This register must be programed with register 5 (HNDP) ** to arrive at the frame rate closest to the desired ** frame rate. */ *(pRegs + 0x0A) = 0x01; /* 0000 0001 */ /* ** Register B: VRTC/FPFRAME Start Position - applicable to CRT/TFT only. */ *(pRegs + 0x0B) = 0x00; /* 0000 0000 */ /* ** Register C: VRTC/FPFRAME Pulse Width - applicable to CRT/TFT only.
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Page 92 Epson Research and Development Vancouver Design Center /* ** Register 19: Clock Configuration - In this case we must divide ** PCLK by 2 to arrive at the best frequency to set ** our desired panel frame rate. */ *(pRegs + 0x19) = 0x01; /* 0000 0001 */ /* ** Register 1A: Power Save Configuration - enable LCD power, CBR refresh, ** not suspended.
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Epson Research and Development Vancouver Design Center Page 93 /* ** Registers 28-29: Cursor X Position */ *(pRegs + 0x28) = 0x00; /* 0000 0000 */ *(pRegs + 0x29) = 0x00; /* 0000 0000 */ /* ** Registers 2A-2B: Cursor Y Position */ *(pRegs + 0x2A) = 0x00; /* 0000 0000 */ *(pRegs + 0x2B) = 0x00; /* 0000 0000 */ /* ** Registers 2C-2D: Ink/Cursor Color 0 - blue */ *(pRegs + 0x2C) = 0x1F; /* 0001 1111 */ *(pRegs + 0x2D) = 0x00; /* 0000 0000 */ /* ** Registers 2E-2F: Ink/Cursor Color 1 - green */ *(pRegs + 0x2E
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Page 94 Epson Research and Development Vancouver Design Center ** Draw a 100x100 red rectangle in the upper left corner (0, 0) ** of the display. */ pMem = DISP_MEM_OFFSET; for (y = 0; y < 100; y++) { pTmp = pMem + y * 640L; for (x = 0; x < 100; x++) { *pTmp = 0x0c; pTmp++; } } /* ** Init the HW cursor. In this example the cursor memory will be located ** immediately after display memory. Why here? Because it's an easy ** location to calculate and will not interfere with the half frame buffer.
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Page 95 Epson Research and Development Vancouver Design Center } for (lpCnt = 0; lpCnt < 14; lpCnt++) { *pTmp = 0x6A; pTmp += 15; *pTmp = 0xA9; pTmp++; } for (lpCnt = 0; lpCnt < 16; lpCnt++) { *pTmp = 0x55; pTmp++; } /* ** Move the cursor to 100, 100. */ /* ** First we wait for the next vertical ** period before updating the position */ while (*(pRegs + 0x0A) & 0x80); /* while (!(*(pRegs + 0x0A) & 0x80)); /* /* ** Now update the position registers.
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Page 96 Epson Research and Development Vancouver Design Center /* Include this file ONCE in your primary source file */ /********************************************************************************/ HAL_STRUCT HalInfo = { "1355 HAL EXE", 0x1234, sizeof(HAL_STRUCT), 0, /* /* /* /* ID string */ Detect Endian */ Size */ Default Mode */ { { 0x00, 0xEF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 /* LCD */ 0x16, 0x00, 0x34, 0x00, 0x00, 0x00, 0x02, 0x00, 0x48, 0x00, 0x00, 0x0
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Page 97 Epson Research and Development Vancouver Design Center 50, 84, 30, 50, 16 /* Memory speed in ns */ /* Ras to Cas Delay in ns */ /* Ras Access Charge time in ns */ /* RAS Access Charge time in ns */ /* Host CPU bus width in bits */ }; The following header file defines the S1D13505 HAL registers. /*=========================================================================== ** HAL_REGS.H ** Created 1998, Epson Research & Development ** Vancouver Design Center.
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Page 98 #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define #define Epson Research and Development Vancouver Design Center REG_CLOCK_CONFIG REG_POWER_SAVE_CONFIG REG_MISC REG_MD_CONFIG_READBACK0 REG_MD_CONFIG_READBACK1 REG_GPIO_CONFIG0 REG_GPIO_CONFIG1 REG_GPIO_CONTROL0 REG_GPIO_CONTROL1 REG_PERF_ENHANCEMENT0 REG_PERF_ENHANCEMENT1 REG_LUT_ADDR REG_RESERVED_1 REG_LUT_
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Page 99 Epson Research and Development Vancouver Design Center #pragma warning(disable:4001) // Disable the 'single line comment' warning. #include "hal_regs.
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Page 100 Epson Research and Development Vancouver Design Center #define TRUE #endif #ifndef FALSE #define FALSE #endif 1 0 #define OFF 0 #define ON 1 #ifndef NULL #ifdef __cplusplus #define NULL 0 #else #define NULL ((void *)0) #endif #endif /*-------------------------------------------------------------------------*/ /* ** SIZE_VERSION is the ** SIZE_STATUS is the ** SIZE_REVISION is the */ #define SIZE_VERSION #define SIZE_STATUS #define SIZE_REVISION #ifdef ENABLE_DPF #define #define #define #defin
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Page 101 Epson Research and Development Vancouver Design Center { ERR_OK = 0, ERR_FAILED, /* No error, call was successful. */ /* General purpose failure. */ ERR_UNKNOWN_DEVICE, ERR_INVALID_PARAMETER, ERR_HAL_BAD_ARG, ERR_TOOMANY_DEVS, /* */ /* Function was called with invalid parameter.
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Page 102 Epson Research and Development Vancouver Design Center * Definitions for seSetFont *******************************************/ enum { HAL_STDOUT, HAL_STDIN, HAL_DEVICE_ERR }; #define FONT_NORMAL #define FONT_DOUBLE_WIDTH #define FONT_DOUBLE_HEIGHT 0x00 0x01 0x02 enum { RED, GREEN, BLUE }; /******************************************* * Definitions for seSplitScreen() *******************************************/ enum { SCREEN1 = 1, SCREEN2 }; /******************************************* * Defi
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Page 103 Epson Research and Development Vancouver Design Center MAX_DISP_MODE }; typedef struct tagHalStruct { char szIdString[16]; WORD wDetectEndian; WORD wSize; WORD wDefaultMode; BYTE Regs[MAX_DISP_MODE][MAX_REG + 1]; DWORD DWORD DWORD DWORD WORD dwClkI; dwBusClk; dwRegAddr; dwDispMem; wPanelFrameRate; /* /* /* /* /* Input Clock Frequency (in kHz) */ Bus Clock Frequency (in kHz) */ Starting address of registers */ Starting address of display buffer memory */ Desired panel frame rate */ WORD WORD
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Page 104 Epson Research and Development Vancouver Design Center #define DONT_CLEAR_MEM FALSE int seSetDisplayMode(int device, int DisplayMode, int ClearMem); int seSetInit(int device); int seGetId( int seReserved1, int *pId ); void seGetHalVersion( const char **pVersion, const char **pStatus, const char **pStatusRevision ); /*---------------------------- Chip Access --------------------------------*/ int seGetReg( int seReserved1, int index, BYTE *pValue ); int seSetReg( int seReserved1, int index, BYTE v
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Page 105 Epson Research and Development Vancouver Design Center int seGetInkStartAddr(int seReserved1, DWORD *addr); int seGetPixel( int seReserved1, long x, long y, DWORD *pVal ); int seSetPixel( int seReserved1, long x, long y, DWORD color ); int seDrawLine( int seReserved1, long x1, long y1, long x2, long y2, DWORD color ); int seDrawRect( int seReserved1, long x1, long y1, long x2, long y2, DWORD color, BOOL SolidFill ); int seDrawEllipse(int seReserved1, long xc, long yc, long xr, long yr, DWORD colo
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Page 106 Epson Research and Development Vancouver Design Center int seSetLutEntry( int seReserved1, int index, BYTE *pEntry ); int seGetLutEntry( int seReserved1, int index, BYTE *pEntry ); /*--------------------------- C Like Support ------------------------------*/ int seDrawText( int seReserved1, char *fmt, ...
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Page 107 Epson Research and Development Vancouver Design Center Appendix A Supported Panel Values A.1 Supported Panel Values The following tables show related register data for different panels. All the examples are based on 8 bpp and 2M bytes of 50 ns EDO-DRAM. Note The following settings may not reflect the ideal settings for your system configuration. Power, speed, and cost requirements may dictate different starting parameters for your system (e.g. 320x240@78Hz using 12MHz clock).
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Page 108 Epson Research and Development Vancouver Design Center Table 12-3: Passive Dual Panel @ 640x480 with 40MHz Pixel Clock Mono 4-Bit EL Mono 8-Bit Color 8-Bit Color 16-Bit 640X480@60Hz 640X480@60Hz 640X480@60Hz 640X480@60Hz REG[02h] 1000 0010 0001 0010 0001 0110 0010 0110 REG[03h] 0000 0000 0000 0000 0000 0000 0000 0000 set MOD rate REG[04h] 0100 1111 0100 1111 0100 1111 0100 1111 set horizontal display width Register Notes set panel type REG[05h] 0000 0101 0000 0101 00
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S1D13505F00A Register Summary X23A-R-001-04 REG[00h] REVISION CODE REGISTER 1 (For S1D13505: Product Code=000011b, Revision Code=00b)RO Product Code Bit 5 Bit 4 Bit 3 REG[11h] SCREEN 1 DISPLAY START ADDRESS R EGISTER 1 Bit 2 Bit 1 Bit 0 Bit 1 RW RC Timing Value 9 Bit 0 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG[12h] SCREEN 1 DISPLAY START ADDRESS R EGISTER 2 REG[01h] MEMORY CONFIGURATION REGISTER n/a 1/0 Refresh Rate 3 2 Bit 2 Bit 1 n/a Bit 0 WE# Control n/a RW
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S1D13505F00A Register Summary X23A-R-001-04 3 DRAM Refresh Rate Select 11 RAS Precharge Timing Select DRAM Refresh Rate Select Bits [2:0] CLKI Frequency Divisor Example Refresh Rate for CLKI = 33MHz Example period for 256 refresh cycles at CLKI = 33MHz REG[22h] Bits [3:2] NRP RAS Precharge Width (tRP) 00 2 2 1.5 1.5 000 64 520 kHz 0.
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S1D13505 Embedded RAMDAC LCD/CRT Controller 13505CFG Configuration Program Document Number: X23A-B-001-04 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-B-001-04 13505CFG Configuration Program Issue Date: 01/03/29
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Page 3 Epson Research and Development Vancouver Design Center Table of Contents 13505CFG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 S1D13505 Supported Evaluation Platforms Installation . . . . . . . . . . . . . Usage . . . . . . . . . . . . . . . 13505CFG Configuration Tabs . . . . . General Tab . . . . . . . . . . . . . . Preferences Tab . . . . . . . . . . . . Memory Tab . . . . . . . . . . . . . . Clocks Tab . . . . . . . . . . . . . . .
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Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-B-001-04 13505CFG Configuration Program Issue Date: 01/03/29
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Page 5 Epson Research and Development Vancouver Design Center 13505CFG 13505CFG is an interactive Windows® 9x/ME/NT/2000 program that calculates register values for a user defined S1D13505 configuration. The configuration information can be used to directly alter the operating characteristics of the S1D13505 utilities or any program built with the Hardware Abstraction Layer (HAL) library.
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Page 6 Epson Research and Development Vancouver Design Center Installation Create a directory for 13505cfg.exe and the S1D13505 utilities. Copy the files 13505cfg.exe and panels.def to that directory. Panels.def contains configuration information for a number of panels and must reside in the same directory as 13505cfg.exe. Usage 13505CFG can be started from the Windows desktop or from a Windows command prompt.
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Epson Research and Development Vancouver Design Center Page 7 13505CFG Configuration Tabs 13505CFG provides a series of tabs which can be selected at the top of the main window. Each tab allows the configuration of a specific aspect of S1D13505 operation. The tabs are labeled “General”, “Preference”, “Memory”, “Clocks”, “Panel”, “CRT”, and “Registers”. The following sections describe the purpose and use of each of the tabs.
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Page 8 Epson Research and Development Vancouver Design Center Register Address The physical address of the start of register decode space (in hexadecimal). This field is automatically set according to the Decode Address unless the “User-Defined” decode address is selected. Display Buffer Address The physical address of the start of display buffer decode space (in hexadecimal). This field is automatically set according to the Decode Address unless the “User-Defined” decode address is selected.
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Page 9 Epson Research and Development Vancouver Design Center Preferences Tab Initial Display Panel SwivelView Panel Color Depth CRT Color Depth The Preference tab contains settings pertaining to the initial display state. During runtime the display or color depth may be changed. Initial Display Sets which display device is used for the initial display. Selections made on the CRT tab may cause selections on this tab to be grayed out. The selections “None” and “Panel” are always available.
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Page 10 Epson Research and Development Vancouver Design Center Memory Tab Access Time Refresh Time Memory Type WE# Control Suspend Mode Memory Performance Installed Memory The Memory tab contains settings that control the configuration of the DRAM used for the S1D13505 display buffer. Note The DRAM memory type and access time determines the optimal memory clock (MCLK). See “Clocks Tab” on page 12 for an explanation on how to determine the optimal memory clock.
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Page 11 Epson Research and Development Vancouver Design Center WE# Control Selects the WE# control used for the DRAM. DRAM uses one of two methods of control when writing to memory. These methods are referred to as 2-CAS# and 2-WE#. The S5U13505 evaluation boards use DRAM requiring the 2-CAS# method. Refresh Time Memory Performance This value represents the number of ms required to refresh 256 rows of DRAM. These settings optimize the memory timings for best performance.
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Page 12 Epson Research and Development Vancouver Design Center Clocks Tab LCD PCLK Source LCD PCLK Divide CLKI BUSCLK CRT/TV PCLK Source CRT/TV PCLK Divide MCLK Source MCLK Divide The Clocks tab is intended to simplify the selection of input clock frequencies and the source of internal clocking signals. For further information regarding clocking and clock sources, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.
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Page 13 Epson Research and Development Vancouver Design Center The S1D13505 may use as many as three input clocks or as few as one. The more clocks used the greater the flexibility of choice in display type and memory speed. CLKI This setting determines the frequency of CLKI. CLKI is the source clock for all of the S1D13505 internal clocks. Select “LCD Auto” or “CRT Auto” to have the CLKI frequency determined automatically based on settings made on the Panels or CRT configuration tabs.
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Page 14 Epson Research and Development Vancouver Design Center CRT PCLK These settings select the signal source and input clock divisor for the CRT pixel clock (CRT PCLK). Source The CRT PCLK source is CLKI. Divide Specifies the divide ratio of CLKI to derive the CRT PCLK. Selecting “Auto” for the divisor allows the configuration program to calculate the best clock divisor. Unless a very specific clocking is required, it is best to leave this setting on “Auto”.
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Page 15 Epson Research and Development Vancouver Design Center Panel Tab Panel Data Width Single/Dual Dual Panel Buffer Disable Mono/Color Format 2 Panel Type FPLINE Polarity EL Support FPFRAME Polarity Frame Rate Panel Dimensions Pixel Clock Predefined Panels HRTC/FPLINE Non-Display Period VRTC/FPFRAME The S1D13505 supports many panel types. This tab allows configuration of most panel settings such as panel dimensions, type and timings.
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Page 16 Epson Research and Development Vancouver Design Center Panel Data Width Selects the panel data width. Panel data width is the number of bits of data transferred to the LCD panel on each clock cycle and shouldn’t be confused with color depth which determines the number of displayed colors. When the panel type is STN, the available options are 4 bit, 8 bit, and 16 bit. When the panel type is TFT the available options are 9 bit, 12 bit, and 18 bit.
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Epson Research and Development Vancouver Design Center Panel Dimensions Page 17 These fields specify the panel width and height. A number of common widths and heights are available in the selection boxes. If the width/height of your panel is not listed, enter the actual panel dimensions into the edit field. Manually entered panel widths must be a multiple of 16 pixels for passive (STN) panels and 8 pixels for TFT panels.
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Page 18 Epson Research and Development Vancouver Design Center HRTC/FPLINE (pixels) Start pos Specifies the delay (in pixels) from the start of the horizontal non-display period to the leading edge of the FPLINE pulse. Pulse Width Specifies the pulse width (in pixels) of the FPLINE output signal. VRTC/FPFRAME (lines) These settings allow fine tuning the TFT frame pulse parameters and are only available when the selected panel type is TFT.
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Page 19 Epson Research and Development Vancouver Design Center CRT/TV Tab CRT Display Dimensions Simultaneous Display Options The CRT tab configures settings specific to the CRT display device. CRT Display Dimensions Select the CRT resolution and frame rate from the dropdown list. The available options vary based on selections made in the Clocks tab. If no selections are available, the CRT pixel clock settings on the Clocks tab must be changed.
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Page 20 Epson Research and Development Vancouver Design Center Registers Tab The Registers tab allows viewing and direct editing the S1D13505 register values. Scroll up and down the list of registers and view their configured value. Individual register settings may be changed by double-clicking on the register in the listing. Manual changes to the registers are not checked for errors, so caution is warranted when directly editing these values.
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Page 21 Epson Research and Development Vancouver Design Center 13505CFG Menus The following sections describe each of the options in the File and Help menus. Open... From the Menu Bar, select “File”, then “Open...” to display the Open File Dialog Box. The Open option allows 13505CFG to open files containing HAL configuration information. When 13505CFG opens a file it scans the file for an identification string, and if found, reads the configuration information.
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Page 22 Epson Research and Development Vancouver Design Center Save From the Menu Bar, select “File”, then “Save” to initiate the save action. The Save menu option allows a fast save of the configuration information to a file that was opened with the Open menu option. Note This option is only available once a file has been opened. Note 13505cfg.exe can be configured by making a copy of the file 13505cfg.exe and configuring the copy. It is not possible to configure the original while it is running.
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Epson Research and Development Vancouver Design Center Page 23 Configure Multiple After determining the desired configuration, “Configure Multiple” allows the information to be saved into one or more executable files built with the HAL library. From the Menu Bar, select “File”, then “Configure Multiple” to display the Configure Multiple Dialog Box.This dialog box is also displayed when a file(s) is dragged onto the 13505CFG window.
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Page 24 Epson Research and Development Vancouver Design Center Export After determining the desired configuration, “Export” permits the user to save the register information as a variety of ASCII text file formats. The following is a list and description of the currently supported output formats: • a C header file for use in writing HAL library based applications. • a C header file which lists each register and the value it should be set to.
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Page 25 Epson Research and Development Vancouver Design Center Enable Tooltips Tooltips provide useful information about many of the items on the configuration tabs. Placing the mouse pointer over nearly any item on any tab generates a popup window containing helpful advice and hints. To enable/disable tooltips check/uncheck the “Tooltips” option form the “Help” menu. Note Tooltips are enabled by default.
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Page 26 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-B-001-04 13505CFG Configuration Program Issue Date: 01/03/29
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S1D13505 Embedded RAMDAC LCD/CRT Controller 13505SHOW Demonstration Program Document Number: X23A-B-002-05 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-B-002-05 13505SHOW Demonstration Program Issue Date: 01/02/02
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Page 3 Epson Research and Development Vancouver Design Center 13505SHOW 13505SHOW is designed to demonstrate and test some of the S1D13505 display capabilities. The program can cycle through all the color depths and display a pattern showing all available colors, or the user can specify a color depth and display configuration. The 13505SHOW demonstration program must be configured and/or compiled to work with your hardware platform. The program 13505CFG.EXE can be used to configure 13505SHOW.
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Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13505show [b=??] [/a] [/crt] [/g] [/lcd] [/noinit] [/p] [/read] [/s] [/?]. Embedded platform: execute 13505show and at the prompt, type the command line argument.
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Epson Research and Development Vancouver Design Center 3. Page 5 To show a color pattern for a specific bit-per-pixel mode, type the following: 13505SHOW b=[mode] where mode = 1, 2, 4, 8, 15, or 16. The program will display the requested screen and then exit. 4. To show the color patterns in portrait mode, type the following: 13505SHOW /p The program will display 16 bit-per-pixel mode. Press any key to go to the next screen.
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Page 6 Epson Research and Development Vancouver Design Center Comments • 13505SHOW cannot show a greater color depth than the display allows. • Portrait mode is available only for 8, 15, and 16 bit-per-pixel. • When using a PC with the S5U13505 evaluation board, the PC must not have more than 12M bytes of system memory. • 13505SHOW uses the panel color setup to determine whether to display a mono or color image on both the panel and the CRT.
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Epson Research and Development Vancouver Design Center Page 7 Program Messages ERROR: Could not initialize device. These messages generally mean that the given hardware/software setup violates the timing limitations described in the 13505 Hardware Functional Specification, document number X23A-A-001xx. ERROR: Unknown command line argument. An invalid command line argument was entered. Refer to the help screen or documentation for valid command line arguments. ERROR: Too many devices registered.
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Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-B-002-05 13505SHOW Demonstration Program Issue Date: 01/02/02
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S1D13505 Embedded RAMDAC LCD/CRT Controller 13505SPLT Display Utility Document Number: X23A-B-003-03 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current.
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Page 3 Epson Research and Development Vancouver Design Center 13505SPLT 13505SPLT demonstrates S1D13505 split screen capability by showing two different areas of display memory on the screen simultaneously. Screen 1 shows horizontal bars and Screen 2 shows vertical bars. Screen 1 memory is located at the start of the display buffer. Screen 2 memory is located immediately after Screen 1 in the display buffer.
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Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13505splt [/a] [/?]. Embedded platform: execute 13505splt and at the prompt, type the command line argument. Where: no argument enables manual split screen operation /a enables automatic split screen operation /? displays the help screen The following keyboard commands are for navigation within the program.
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Epson Research and Development Vancouver Design Center Page 5 Program Messages ERROR: Did not find a 13505 device. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL currently supports only one device. ERROR: Could not register S1D13505FOA device.
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S1D13505 Embedded RAMDAC LCD/CRT Controller 13505VIRT Display Utility Document Number: X23A-B-004-04 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-B-004-04 13505VIRT Display Utility Issue Date: 01/02/02
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Page 3 Epson Research and Development Vancouver Design Center 13505VIRT 13505VIRT demonstrates the virtual display capability of the S1D13505. A virtual display is where the image to be displayed is larger than the physical display device (CRT or LCD). 13505VIRT uses panning and scrolling to allow the display device to show a “window” into the entire image. The 13505VIRT display utility must be configured and/or compiled to work with your hardware platform. The program 13505CFG.
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Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13505virt [w=??] [/a] [/?]. Embedded platform: execute 13505virt and at the prompt, type the command line argument.
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Epson Research and Development Vancouver Design Center Page 5 13505VIRT Example 1. Type "13505virt /a" to automatically pan and scroll. 2. Press "b" to change the bit-per-pixel value from 16 to 15 bit-per-pixel. 3. Repeat step 2 for the following bit-per-pixel values: 16, 15, 8, 4, 2, and 1. 4. Press to exit the program. Comments • When using a PC with the S5U13505 evaluation board, the PC must not have more than 12M bytes of system memory.
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Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-B-004-04 13505VIRT Display Utility Issue Date: 01/02/02
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S1D13505 Embedded RAMDAC LCD/CRT Controller 13505PLAY Diagnostic Utility Document Number: X23A-B-005-04 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13550 X23A-B-005-04 13505PLAY Diagnostic Utility Issue Date: 01/02/02
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Page 3 Epson Research and Development Vancouver Design Center 13505PLAY 13505PLAY is a diagnostic utility which allows the user to read/write to all the S1D13505 Registers, Look-Up Tables and Display Buffer. 13505PLAY is similar to the DOS DEBUG program; commands are received from the standard input device, and output is sent to the standard output device (console for Intel, terminal for embedded platforms). This utility requires the target platform to support standard IO (stdio).
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Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13505play [/?]. Embedded platform: execute 13505play and at the prompt, type the command line argument. Where: /? displays program version information. The following commands are valid within the 13505PLAY program. b 8|16 - Sets the ISA bus to 8 or 16 bits. - Only sets up the PAL on the S5U13505 evaluation board. There is no readback capability.
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Page 5 Epson Research and Development Vancouver Design Center p 1|0 - Set power mode (hardware suspend). 1 = set hardware suspend. 0 = reset hardware suspend. - This command is only supported on a S5U13505 evaluation board for the PC platform. q - Quits the 13505PLAY utility. r[w] addr [count] - Reads number of bytes or words [w] from the address specified by “addr”. If “count” is not specified, then 16 bytes/words are read. v - Calculates the frame rate from VNDP count (PC platform only).
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Page 6 Epson Research and Development Vancouver Design Center Scripting 13505PLAY can be driven by a script file. This is useful when: • there is no display output and a current register status is required. • various registers must be quickly changed to view results. A script file is an ASCII text file with one 13505PLAY command per line. All scripts must end with a “q” (quit) command. On a PC platform, a typical script command line might be: “13505PLAY < dumpregs.scr > results.
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Epson Research and Development Vancouver Design Center Page 7 Program Messages WARNING: Did not find a 13505 device. The HAL was unable to read the revision code register on the S1D13505. Ensure that the S1D13505 hardware is installed and that the hardware platform has been set up correctly. ERROR: Failed to change to ?? mode. Could not change to CRT, LCD, or SIMUL mode.
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S1D13505 Embedded RAMDAC LCD/CRT Controller 13505BMP Demonstration Program Document Number: X23A-B-006-04 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 0 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-B-006-04 13505BMP Demonstration Program Issue Date: 01/02/02
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Page 1 Epson Research and Development Vancouver Design Center 13505BMP 13505BMP is a demonstration utility used to show the S1D13505 display capabilities by rendering bitmap images on the display. The program will display any bitmap in Windows BMP file format and then exit. 13505BMP also loads images to demonstrate the hardware cursor and ink layer. 13505BMP is designed to operate on a personal computer (PC) in the DOS environment only.
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Page 2 Epson Research and Development Vancouver Design Center /mouse use mouse to move hardware cursor (press ESC to exit program) /noclear don’t clear display buffer memory /noinit skips register initialization /p portrait mode (not available for hardware cursor or ink layer images) /v verbose mode (provides information about the displayed images) /? displays the Help screen Note 13505BMP will automatically finish execution and return to the prompt.
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Epson Research and Development Vancouver Design Center Page 3 13505BMP Examples To display a bmp image on a CRT, type the following: 13505BMP bmpfile.bmp /crt To display a bmp image on an LCD, type the following: 13505BMP bmpfile.bmp /lcd To display a bmp image on an LCD in portrait mode, type the following: 13505BMP bmpfile.bmp /lcd /p To load a bmp image and a hardware cursor image on an LCD, type the following: 13505BMP /lcd bmpfile.bmp 13505BMP t=cursor /noinit arrow.
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Page 4 Epson Research and Development Vancouver Design Center Program Messages ERROR: Could not initialize device. The given hardware/software setup violates the timing specification as described in the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx. ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL currently supports only one device. ERROR: Could not register S1D13505F00A device.
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Epson Research and Development Vancouver Design Center Page 5 ERROR: Could not initialize ink layer. The HAL library could not initialize the Ink Layer. ERROR: BMP file is ?? bit-per-pixel; ink layer requires 4 bit-perpixel BMP file. The Ink Layer BMP image must always have a color depth of four bit-per-pixel. ERROR: Could not change to ?? bit-per-pixel. The HAL library detected that the requested color depth (bit-per-pixel) will violate the S1D13505 hardware specification for clocks.
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S1D13505 Embedded RAMDAC LCD/CRT Controller 13505PWR Software Suspend Power Sequencing Utility Document Number: X23A-B-007-03 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-B-007-03 13505PWR Software Suspend Power Sequencing Utility Issue Date: 01/02/02
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Page 3 Epson Research and Development Vancouver Design Center 13505PWR 13505PWR is a diagnostic utility used to test some of the power save capabilities of the S1D13505. 13505PWR enables or disables the software suspend mode, hardware suspend mode, and the LCD, allowing testing of the power sequencing in each mode. To measure the timing for power sequencing, GPIO pin 1 is used to trigger an oscilloscope at the point the requested power sequencing function is activated/deactivated.
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Page 4 Epson Research and Development Vancouver Design Center Usage PC platform: at the prompt, type 13505pwr [/software  /hardware | /lcd] [/enable  /disable] [/i] [/0 | /1] [/?]. Embedded platform: execute 13505pwr and at the prompt, type the command line argument.
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Page 5 Epson Research and Development Vancouver Design Center Comments • The /i argument is to be used when the registers have not been previously initialized. • When using a PC with the S5U13505 evaluation board, the PC must not have more than 12M bytes of system memory. • GPIO1 is used to signal when the software suspend mode, hardware suspend mode, or LCD has been enabled or disabled.
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Page 6 Epson Research and Development Vancouver Design Center ERROR: Too many devices registered. There are too many display devices attached to the HAL. The HAL currently supports only one device. ERROR: Could not register S1D13505F00A device. A S1D13505 device was not found at the configured addresses. Check the configuration address using the 13505CFG configuration program.
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S1D13505 Embedded RAMDAC LCD/CRT Controller Windows® CE 2.x Display Drivers Document Number: X23A-E-001-06 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-E-001-06 Windows® CE 2.
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Page 3 Epson Research and Development Vancouver Design Center WINDOWS® CE 2.x DISPLAY DRIVERS The Windows CE display driver is designed to support the S1D13505 Embedded RAMDAC LCD/CRT Controller running under the Microsoft Windows CE 2.x operating system. The driver is capable of: 4, 8 and 16 bit-per-pixel landscape modes (no rotation), and 8 and 16 bit-per-pixel SwivelView™ 90 degree mode. This document and the source code for the Windows CE drivers are updated as appropriate.
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Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds The following sections describe how to build the Windows CE display driver for: 1. Windows CE 2.0 using a command-line interface. 2. Windows CE Platform Builder 2.1x using a command-line interface. In all examples “x:” refers to the drive letter where Platform Builder is installed. Build for CEPC (X86) on Windows CE 2.0 using a Command-Line Interface To build a Windows CE v2.
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Page 5 Epson Research and Development Vancouver Design Center 7. Edit the file x:\wince\platform\cepc\drivers\display\dirs and add S1D13505 into the list of directories. 8. Edit the file PLATFORM.BIB (located in x:\wince\platform\cepc\files) to set the default display driver to the file EPSON.DLL (EPSON.DLL will be created during the build in step 13). Replace or comment out the following lines in PLATFORM.BIB: IF CEPC_DDI_VGA2BPP ddi.dll $(_FLATRELEASEDIR)\ddi_vga2.
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Page 6 Epson Research and Development Vancouver Design Center For example, the display driver section of PLATFORM.
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Page 7 Epson Research and Development Vancouver Design Center e. Choose “Copy Here”. f. Rename the icon “Build Minshell for x86” to “Build Epson for x86” by right clicking on the icon and choosing “rename”. g. Right click on the icon “Build Epson for x86” and click on “Properties” to bring up the “Build Epson for x86 Properties” window. h. Click on “Shortcut” and replace the string “Minshell” under the entry “Target” with “Epson”. i. Click on “OK” to finish. 5. Create an EPSON project. a.
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Page 8 Epson Research and Development Vancouver Design Center ddi.dll $(_FLATRELEASEDIR)\ddi_s364.dll NK SH ENDIF ENDIF ENDIF ENDIF Insert this line 9. The file MODE0.H (located in x:\wince\platform\cepc\drivers\display\S1D13505) contains the register values required to set the screen resolution, color depth (bpp), display type, active display (LCD/CRT/TV), display rotation, etc. Before building the display driver, refer to the descriptions in the file MODE0.H for the default settings of the driver.
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Epson Research and Development Vancouver Design Center Page 9 12. Generate the proper building environment by double-clicking on the Epson project icon --”Build Epson for x86”. 13. Type BLDDEMO at the command prompt of the “Build Epson for x86” window to generate a Windows CE image file (NK.BIN). Windows® CE 2.
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Page 10 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once the NK.BIN file is built, the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system. The two methods are described below. 1. To start CEPC after booting from a floppy drive: a. Create a bootable floppy disk. b. Edit CONFIG.SYS on the floppy disk to contain only the following line: device=a:\himem.sys c. Edit AUTOEXEC.
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Epson Research and Development Vancouver Design Center Page 11 Configuration There are several issues to consider when configuring the display driver. The issues cover debugging support, register initialization values and memory allocation. Each of these issues is discussed in the following sections. Compile Switches There are several switches, specific to the S1D13505 display driver, which affect the display driver. The switches are added or removed from the compile options in the file SOURCES.
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Page 12 Epson Research and Development Vancouver Design Center Mode File A second variable which will affect the finished display driver is the register configurations contained in the mode file. The MODE tables (contained in files MODE0.H, MODE1.H, MODE2.H . . .) contain register information to control the desired display mode. The MODE tables must be generated by the configuration program 13505CFG.EXE. The display driver comes with example MODE tables. By default, only MODE0.
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Epson Research and Development Vancouver Design Center Page 13 Comments • The display driver is CPU independent, allowing use of the driver for several Windows CE Platform Builder supported platforms. • When using 13505CFG.EXE to produce multiple MODE tables, make sure you change the Mode Number in the WinCE tab for each mode table you generate. The display driver supports multiple mode tables, but only if each mode table has a unique mode number.
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Page 14 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-E-001-06 Windows® CE 2.
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S1D13505 Embedded RAMDAC LCD/CRT Controller Wind River WindML v2.0 Display Drivers Document Number: X23A-E-002-03 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-E-002-03 Wind River WindML v2.
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Page 3 Epson Research and Development Vancouver Design Center Wind River WindML v2.0 DISPLAY DRIVERS The Wind River WindML v2.0 display drivers for the S1D13505 Embedded RAMDAC LCD/CRT Controller are intended as “reference” source code for OEMs developing for Wind River’s WindML v2.0. The driver package provides support for both 8 and 16 bitper-pixel color depths. The source code is written for portability and contains functionality for most features of the S1D13505.
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Page 4 Epson Research and Development Vancouver Design Center Building a WindML v2.0 Display Driver The following instructions produce a bootable disk that automatically starts the UGL demo program. These instructions assume that Wind River’s Tornado platform is already installed. Note For the example steps where the drive letter is given as “x:”. Substitute “x” with the drive letter that your development environment is on. 1. Create a working directory and unzip the WindML display driver into it.
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Page 5 Epson Research and Development Vancouver Design Center Note Mode0.h should be created using the configuration utility 13505CFG. For more information on 13505CFG, see the 13505CFG Configuration Program User Manual, document number X23A-B-001-xx available at www.erd.epson.com. 6. Build the WindML v2.0 library. From a command prompt change to the directory “x:\Tornado\host\x86-win32\bin” and run the batch file torvars.bat.
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S1D13505 Embedded RAMDAC LCD/CRT Controller Wind River UGL v1.2 Display Drivers Document Number: X23A-E-003-02 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 3 Epson Research and Development Vancouver Design Center Wind River UGL v1.2 Display Drivers The Wind River UGL v1.2 display drivers for the S1D13505 Embedded RAMDAC LCD/CRT Controller are intended as “reference” source code for OEMs developing for Wind River’s UGL v1.2. The drivers provide support for both 8 and 16 bit-per-pixel color depths. The source code is written for portability and contains functionality for most features of the S1D13505.
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Page 4 Epson Research and Development Vancouver Design Center Building a UGL v1.2 Display Driver The following instructions produce a bootable disk that automatically starts the UGL demo software. These instructions assume that the Wind River Tornado platform is correctly installed. Note For the example steps where the drive letter is given as “x:”. Substitute “x” with the drive letter your development environment is on. 1. Create a working directory and unzip the UGL display driver into it.
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Page 5 Epson Research and Development Vancouver Design Center Note Mode0.h should be created using the configuration utility 13505CFG. For more information on 13505CFG, see the 13505CFG Configuration Program User Manual, document number X23A-B-001-xx available at www.erd.epson.com. 6. Open the S1D13505 workspace. From the Tornado tool bar, select File->Open Workspace...->Existing->Browse... and select the file “x:\13505\8bpp\13505.wsp” (or “x:\13505\16bpp\13505.wsp”). 7.
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Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-E-003-02 Wind River UGL v1.
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S1D13505 Embedded RAMDAC LCD/CRT Controller Windows® CE 3.x Display Drivers Document Number: X23A-E-006-01 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-E-006-01 Windows® CE 3.
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Page 3 Epson Research and Development Vancouver Design Center WINDOWS® CE 3.x DISPLAY DRIVERS The Windows CE 3.x display driver is designed to support the S1D13505 Embedded RAMDAC LCD/CRT Controller running the Microsoft Windows CE operating system, version 3.0. The driver is capable of: 4, 8 and 16 bit-per-pixel landscape modes (no rotation), and 8 and 16 bit-per-pixel SwivelView™ 90 degree mode. This document and the source code for the Windows CE drivers are updated as appropriate.
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Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds The following sections describe how to build the Windows CE display driver for: 1. Windows CE Platform Builder 3.00 using the GUI interface. 2. Windows CE Platform Builder 3.00 using the command-line interface. In all examples “x:” refers to the drive letter where Platform Builder is installed. Build for CEPC (X86) on Windows CE Platform Builder 3.00 using the GUI Interface 1.
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Page 5 Epson Research and Development Vancouver Design Center d. In the Value box, type “1”. e. Click the Set button. f. Click the OK button. 7. Create a new directory S1D13505, under x:\wince300\platform\cepc\drivers\display, and copy the S1D13505 driver source code into this new directory. 8. Add the S1D13505 driver component. a. From the Platform menu, select “Insert | User Component”. b. Set “Files of type:” to “All Files (*.*)”. c.
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Page 6 Epson Research and Development Vancouver Design Center ddi.dll $(_FLATRELEASEDIR)\ddi_flat.dll NK SH ENDIF ENDIF ENDIF ENDIF ENDIF ENDIF ;Insert this line ENDIF 11. Modify MODE0.H. The file MODE0.H (located in x:\wince300\platform\cepc\drivers\display\S1D13505) contains the register values required to set the screen resolution, color depth (bpp), display type, active display (LCD/CRT/TV), display rotation, etc. Before building the display driver, refer to the descriptions in the file MODE0.
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Page 7 Epson Research and Development Vancouver Design Center “ActiveDisp”=dword:1 “Rotation”=dword:0 13. From the Build menu, select “Rebuild Platform” to generate a Windows CE image file (NK.BIN) in the project directory x:\myproject\myplatform\reldir\x86_release\nk.bin. Build for CEPC (X86) on Windows CE Platform Builder 3.00 using the Command-Line Interface 1. Install Microsoft Windows 2000 Professional, or Windows NT Workstation version 4.0 with Service Pack 5 or later. 2.
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Page 8 Epson Research and Development Vancouver Design Center ddi.dll $(_FLATRELEASEDIR)\ddi_flat.dll NK SH ENDIF ENDIF ENDIF ENDIF ENDIF ENDIF ;Insert this line ENDIF 8. Modify MODE0.H. The file MODE0.H (located in x:\wince300\platform\cepc\drivers\display\S1D13505) contains the register values required to set the screen resolution, color depth (bpp), display type, active display (LCD/CRT/TV), display rotation, etc. Before building the display driver, refer to the descriptions in the file MODE0.
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Epson Research and Development Vancouver Design Center Page 9 10. Delete all the files in the x:\wince300\release directory and delete the file x:\wince300\platform\cepc\*.bif 11. Type BLDDEMO at the command prompt to generate a Windows CE image file. The file generated will be x:\wince300\release\nk.bin. Windows® CE 3.
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Page 10 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once the NK.BIN file is built, the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system. The two methods are described below. 1. To start CEPC after booting from a floppy drive: a. Create a bootable floppy disk. b. Edit CONFIG.SYS on the floppy disk to contain only the following line: device=a:\himem.sys c. Edit AUTOEXEC.
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Epson Research and Development Vancouver Design Center Page 11 Configuration There are several issues to consider when configuring the display driver. The issues cover debugging support, register initialization values and memory allocation. Each of these issues is discussed in the following sections. Compile Switches There are several switches, specific to the S1D13505 display driver, which affect the display driver. The switches are added or removed from the compile options in the file SOURCES.
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Page 12 Epson Research and Development Vancouver Design Center DEBUG_MONITOR This option enables the use of the debug monitor. The debug monitor can be invoked when the display driver is first loaded and can be used to view registers, and perform a few debugging tasks. The debug monitor is still under development and is UNTESTED. This option should remain disabled unless you are performing specific debugging tasks that require the debug monitor.
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Page 13 Epson Research and Development Vancouver Design Center Note that all dword values are in hexadecimal, therefore 280h = 640, 1E0h = 480, and 3Ch = 60. The value for “Flags” should be 1 (LCD), 2 (CRT), or 3 (both LCD and CRT). When the display driver starts, it will read these values in the registry and attempt to match a mode table against them. All values must be present and valid for a match to occur, otherwise the display driver will default to the first mode table in your list.
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Page 14 Epson Research and Development Vancouver Design Center 2. Using off-screen display memory significantly improves display performance. For example, slider bars appear more smooth when using off-screen memory. To enable or disable the use of off-screen memory, edit the file: x:\wince300\platform\cepc\drivers\display\S1D13505\sources.
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Page 15 Epson Research and Development Vancouver Design Center c. PORepaint=2 • This mode tells WinCE to not save the main display data on suspend, and causes WinCE to REPAINT the main display on resume. • This mode is used if display memory power is going to be turned off when the system is suspended, and there is not enough system memory to save the image.
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Page 16 Epson Research and Development Vancouver Design Center Comments • The display driver is CPU independent, allowing use of the driver for several Windows CE Platform Builder supported platforms. • If you are running 13505CFG.EXE to produce multiple MODE tables, make sure you change the Mode Number in the WinCE tab for each mode table you generate. The display driver supports multiple mode tables, but only if each mode table has a unique mode number.
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S1D13505 Embedded RAMDAC LCD/CRT Controller SDU1355B0C Rev. 1.0 ISA Bus Evaluation Board User Manual Document Number: X23A-G-004-05 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 3 Epson Research and Development Vancouver Design Center Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Installation and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 LCD Interface Pin Mapping 4 CPU/Bus Interface Connector Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Page 5 Epson Research and Development Vancouver Design Center List of Tables Table 2-1: Configuration DIP Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2-2: Host Bus Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2-3: Jumper Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Epson Research and Development Vancouver Design Center Page 7 1 Introduction This manual describes the setup and operation of the S5U13505B00C Rev. 1.0 Evaluation Board. Implemented using the S1D13505 Embedded RAMDAC LCD/CRT Controller, the S5U13505B00C is designed for the ISA bus environment. It also provides CPU/Bus interface connectors for non-ISA bus support. For more information regarding the S1D13505, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx. 1.
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Page 8 Epson Research and Development Vancouver Design Center 2 Installation and Configuration The S1D13505 has 16 configuration inputs MD[15:0] which are read on the rising edge of RESET#. Inputs MD[5:1] are fully configurable on this evaluation board for different host bus selections; one eight-position DIP switch is provided for this purpose. All remaining configuration inputs are hardwired. See the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx for more information.
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Page 9 Epson Research and Development Vancouver Design Center 3 LCD Interface Pin Mapping Table 3-1: LCD Signal Connector (J6) Color TFT/D-TFD Color Passive S1D13505 Pin Names Connector Pin No.
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Page 10 Epson Research and Development Vancouver Design Center 4 CPU/Bus Interface Connector Pinouts Table 4-1: CPU/BUS Connector (H1) Pinout Connector Pin No.
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Page 11 Epson Research and Development Vancouver Design Center Table 4-2: CPU/BUS Connector (H2) Pinout Connector Pin No.
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Page 12 Epson Research and Development Vancouver Design Center 5 Host Bus Interface Pin Mapping Table 5-1: CPU Interface Pin Mapping S1D13505 Pin Names SH-3 SH-4 MC68K Bus 1 MC68K Bus 2 Generic MIPS/ISA PowerPC PCMCIA AB20 A20 A20 A20 A20 A20 LatchA20 A11 A20 AB[16:13] A[19:13] A[19:13] A[19:13] A[19:13] A[19:13] SA[19:13] A[12:18] A[19:13] AB[12:1] A[12:1] A[12:1] A[12:1] A[12:1] A[12:1] SA[12:1] A[19:30] A[12:1] AB0 A0 A0 LDS# A0 A0 SA0 A31 A0 DB[15:0] D[15:
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Epson Research and Development Vancouver Design Center Page 13 6 Technical Description 6.1 ISA Bus Support The S5U13505B00C directly supports the 16-bit ISA bus environment. All the configuration options [MD15:0] are either hard-wired or selectable through the eight-position DIP Switch S1. Refer to Table 2-1 “Configuration DIP Switch Settings” on page 8 for details. Note 1. This evaluation board supports a 16-bit ISA bus only. 2.
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Page 14 Epson Research and Development Vancouver Design Center When using the header strips to provide the bus interface observe the following: • All I/O signals on the ISA bus card edge must be isolated from the ISA bus (do not plug the card into a computer). Voltage lines are provided on the header strips. • For the ISA bus, a 22V10 PAL (U4, socketed) is currently used to provide the S1D13505 CS# (pin 4), M/R# (pin 5) and other decode logic signals. This functionality must now be provided externally.
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Page 15 Epson Research and Development Vancouver Design Center 6.3 DRAM Support The S1D13505 supports 256K x 16 as well as 1M x 16 FPM/EDO-DRAM in symmetrical and asymmetrical formats. The S5U13505B00C board supports a 5.0V 1M x 16 symmetrical EDO-DRAM (42-pin SOJ package). This provides a 2M byte display buffer. 6.4 Decode Logic This board utilizes the MIPS/ISA Interface of the S1D13505 (see the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx).
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Page 16 Epson Research and Development Vancouver Design Center 6.8 Color TFT/D-TFD LCD Panel Support The S1D13505 supports 9, 12 and 18-bit active matrix color TFT/D-TFD panels. All the necessary signals can also be found on the 40-pin LCD connector J6. The interface signals on the cable are alternated with grounds to reduce crosstalk and noise. When supporting an 18-bit TFT/D-TFD panel, the S1D13505 can display 64K of a possible 256K colors.
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Epson Research and Development Vancouver Design Center Page 17 6.13 CPU/Bus Interface Header Strips All of the CPU/Bus interface pins of the S1D13505 are connected to the header strips H1 and H2 for easy interface to a CPU, or bus other than ISA. Refer to Table 4-1 “CPU/BUS Connector (H1) Pinout” on page 10 and Table 4-2 “CPU/BUS Connector (H2) Pinout” on page 11 for specific settings. Note These headers only provide the CPU/Bus interface signals from the S1D13505.
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Page 18 Epson Research and Development Vancouver Design Center 7 Parts List Item # Qty/board Designation C1,C2,C3,C4,C5,C6,C7,C10,C11, C12,C13,C18,C25,C27,C28,C29 Part Value Description 0.1uF 0805 ceramic capacitor 1 16 2 1 C8 0.01uF 0805 ceramic capacitor 3 2 C9,C30 1uF 6V Tantalum capacitor size A 4 2 C14,C19 47uF 6V Tantalum capacitor size D 5 3 C15,C16,C17 4.7uF 50V Tantalum capacitor size D 6 1 C20 56uF 35V Low-ESR electrolytic 7 4 C21,C22,C23,C24 4.
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Page 19 Epson Research and Development Vancouver Design Center Item # Qty/board Designation Part Value Description 38 1 U3 MT4C1M16E5DJS-5 39 1 U4 PAL22V10-15 40 1 U5 RD-0412 Xentek RD-0412 41 1 U6 EPN001 Xentek EPN001 42 3 U7,U8,U9 43 1 U10 S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual Issue Date: 01/02/05 50ns self-refresh EDO DRAM 74AHC244 LT1117CM-3.3 “5V to 3.
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D C VCC VCC 1 0.1uF C1 FERRITE BEAD L5 C10 0.1uF + VCC 40MHz GND VCC U2 C2 0.1uF FERRITE BEAD L4 VCC 4 8 NC C9 1uF 6V AVCC C3 0.1uF OUT 2 VCC 5 1 C4 0.1uF AVCC VCC C7 0.1uF C5 0.1uF BUSCLK WAIT# CS# M/R# RESET# RD/WR# WE1# WE0# RD# BS# D[0..15] AVCC VCC A[0..19] C8 0.01uF C6 0.1uF VCC D[0..15] A[0..
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D C B A LCDPWR# WE# RAS# UCAS# LCAS# MA[0..9] 1 VCC PSVCC + C18 0.1uF FERRITE BEAD L7 C14 47uF 6V U5 RD-0412 MA[0..9] DC_IN 2 REMOTE 3 GND GND GND GND GND GND GND PSVCC 2 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 PSVCC 4 5 6 7 8 10 11 NC 9 MD[0..15] 29 11 12 32 13 14 30 31 17 18 19 20 23 24 25 26 27 28 16 15 2 VOUT_ADJ 1 2 DC_OUT 12 3 + 1 MD[0..15] C19 47uF 6V R24 14K R23 200K Pot.
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S1D13505 X23A-G-004-05 D C B A 1 RD# WE0# WE1# LA[17..23] A[0..19] WAIT# D[0..15] 1 + VCC + VCC VCC VCC R34 10K C21 4.7uF 16V VCC D[0..15] 2 A[0..19] + VCC C23 4.7uF 16V VCC LA[17..23] C22 4.7uF 16V R35 10K R31 10K 2 10K R33 + 3 C24 4.
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D C B D[0..15] VCC 1 C29 0.1uF VIN D[0..15] 3 U10 LT1117CM- 3.3 ADJ S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual Issue Date: 01/02/05 1 A 1 D12 D14 D8 D10 D4 D6 D0 D2 2 2 +12V WE0# CS# WE1# RESET# VOUT FPDAT[0..15] + 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 HEADER 17X2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 H1 C30 1uF 6V 3.3V FPDAT[0..
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Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-004-05 S5U13505B00C Rev. 1.
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S5U13505-D9000 Evaluation Board User Manual Document Number: X23A-G-002-04 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13505-D9000 X23A-G-002-04 Evaluation Board User Manual Issue Date: 01/02/05
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Page 3 Epson Research and Development Vancouver Design Center Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 3 S1D13505 Embedded RAMDAC LCD/CRT Controller . . . . . . . . . . . . . . . . . . .8 2.1.1 Display Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1.
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Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13505-D9000 X23A-G-002-04 Evaluation Board User Manual Issue Date: 01/02/05
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Page 5 Epson Research and Development Vancouver Design Center List of Tables Table 2-1: LCD Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 2-2: Touchscreen Header (TS1) Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 2-3: Touchscreen Header Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3-1: Connectors Pinout for Channel A7 . . . . . . . . . . . . . . . . . . .
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Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13505-D9000 X23A-G-002-04 Evaluation Board User Manual Issue Date: 01/02/05
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Page 7 Epson Research and Development Vancouver Design Center 1 Introduction The Hitachi D9000 Development System/Microsoft Windows® CE ODO Reference Platform uses expansion boards to interface peripherals to the FPGA/processor combination. This manual describes how the S5U13505-D9000 Evaluation Board is used to provide a color LCD/CRT solution for the Windows CE environment. Reference S1D13505 Hardware Functional Specification, document number X23A-A-001-xx.
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Page 8 Epson Research and Development Vancouver Design Center 2 Features • S1D13505 Embedded RAMDAC LCD/CRT controller. • 4/8-bit monochrome or 4/8/16-bit color LCD interface for single-panel, single-drive displays. • 8-bit monochrome or 8/16-bit color LCD interface for dual-panel, dual-drive displays. • Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD is supported to 64K colors (16-bit data). • Direct CRT support to 64K colors using the S1D13505 embedded RAMDAC.
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Epson Research and Development Vancouver Design Center Page 9 2.1.2 LCD Display Support The S1D13505 provides a wide range of flexibility for display type and resolution. Display types include: • 4/8-bit monochrome passive. • 4/8/16-bit color passive. • 9/12/18-bit Active matrix TFT/D-TFD. • other (EL, REC, etc.). Display resolutions range from 4x1 to 800x600, with color depths from black-and-white to 64K colors. The LCD connector is a 2 x 20 pin, 0.100", straight header.
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Page 10 Epson Research and Development Vancouver Design Center Table 2-1: LCD Connector Pinout Pin # S1D13505F00A Pin Names Color TFT/D-TFD Color STN 9-bit 12-bit 18-bit 8-bit 16-bit 1 FPDAT[0] R2 R3 R5 LD0 LD0 LD0 3 FPDAT[1] R1 R2 R4 LD1 LD1 LD1 5 FPDAT[2] R0 R1 R3 LD2 LD2 LD2 4-bit Mono STN 7 FPDAT[3] G2 G3 G5 9 FPDAT[4] G1 G2 G4 11 FPDAT[5] G0 G1 G3 UD1 13 FPDAT[6] B2 B3 B5 UD2 15 FPDAT[7] B1 B2 B4 UD3 UD3 17 FPDAT[8] B0 B1 B3 LD4 R0
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Page 11 Epson Research and Development Vancouver Design Center 2.1.3 Touchscreen Support If the LCD panel being used has an integrated Touchscreen, the touchscreen interface signals are connected to header strip TS1. These signals are then routed through JP3 and into the standard "Platform II Audio/Touch" peripheral board. Pinout assignment is described in the table below. Table 2-2: Touchscreen Header (TS1) Pinout Pin # Signal 1 XR 2 XL 3 YU 4 YL 5 XY 6 GND 2.1.
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Page 12 Epson Research and Development Vancouver Design Center LCDPWR is an output signal which follows a pre-defined power-up/power-down sequence designed to protect the LCD panel from damage caused by the power supply being enabled in the absence of control signals. Determine the panel’s specific power requirements and set the potentiometer accordingly before connecting the panel.
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Page 13 Epson Research and Development Vancouver Design Center 3 D9000 Specifics 3.1 Interface Signals The S5U13505-D9000 is designed to support the standard Register Interface of the Windows CE development platform together with the FPGA code that comes with the board. 3.1.
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Page 14 Epson Research and Development Vancouver Design Center Table 3-1: Connectors Pinout for Channel A7 (Continued) Channel A7 Pin # FPGA Signal S1D13505 Signal Pin # FPGA Signal S1D13505 Signal 1 chA7p11 N/C 21 GND GND 2 chA7p12 N/C 22 GND GND 3 chA7p13 4 chA7p14 A20 23 chA7p34 A19 A18 24 GND GND 5 chA7p15 A17 25 GND GND 6 chA7p16 A16 26 GND GND 7 8 chA7p17 N/C 27 chA7p33 A15 chA7p18 A14 28 GND GND 9 chA7p19 A13 29 GND GND 10 chA7p20 A12 30
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Page 15 Epson Research and Development Vancouver Design Center Table 3-2: Connectors Pinout for Channel A6 Channel A6 Pin # FPGA Signal S1D13505 Signal Pin # FPGA Signal S1D13505 Signal SmXY 1 chA6p1 CS# 21 dc5v DC5V 2 chA6p2 BS# 22 GND GND 3 chA6p3 WE0# 23 dc3v DC3V 4 chA6p4 RD/WR# 24 GND GND 5 chA6p5 WAIT# 25 dc3v DC3V 6 chA6p6 N/C 26 GND GND 7 chA6p7 N/C 27 dc3vs N/C 8 chA6p8 N/C 28 GND GND 9 chA6p9 N/C 29 dc12v DC12V 10 chA6p10 N/C 30 GND
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Page 16 Epson Research and Development Vancouver Design Center Table 3-2: Connectors Pinout for Channel A6 (Continued) Channel A6 Pin # FPGA Signal S1D13505 Signal Pin # FPGA Signal S1D13505 Signal 1 chA6p11 M/R# 21 GND GND 2 chA6p12 RD# 22 GND GND 3 chA6p13 4 chA6p14 WE1# 23 chA6p34 N/C RESET# 24 GND GND 5 chA6p15 N/C 25 GND GND 6 chA6p16 N/C 26 GND GND 7 chA6p17 8 chA6p18 N/C 27 chA6p33 D15 D14 28 GND GND 9 chA6p19 D13 29 GND GND 10 chA6p20 D
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Epson Research and Development Vancouver Design Center Page 17 3.1.2 Memory Address (CS#, M/R#) Decoding The S1D13505 is a memory-mapped device for both the registers and the display buffer access. The specific memory address is solely controlled by the CS# and M/R# decode logic. The memory space requirements are: • A 2M byte linear address range for the display buffer. • 47 bytes for the registers.
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Page 18 Epson Research and Development Vancouver Design Center 4 Parts List Item # Qty Reference Part 1 20 C1,C2,C3,C4,C5,C6,C7, C8,C9,C11,C21,C26,C27,C29, C34,C35,C37,C38, C39,C40 0.1uF 0.1uF ceramic capacitor 2 5 C10,C24,C25,C32,C33 10uF 10uF tantalum capacitor 3 1 C17 47uF/10V 47uF/10V tantalum capacitor 4 1 C18 22uF/63V 22uF/63V electrolytic, aluminum can capacitor 5 1 C20 10uF/63V 10uF/63V electrolytic, aluminum can capacitor 6 2 C22,C30 4.7uF 4.
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A B C DC3V DC5V DC3V 1 C4 0.1uF 0.1uF C21 L1 C11 0.1uF L2 C5 0.1uF NC OUT 33.333MHz SMT GND VCC 4 8 OUT NC C6 0.1uF + 1 5 1 5 C10 10uF 2 AVCC C38 0.1uF 33.333MHz TH GND VCC U5 (Dual PCB footprint) 4 8 U6 AVCC C39 0.1uF C40 0.1uF BCLK WAIT# CS# M/R# RESET# RD/WR# WE1# WE0# RD# BS# D[0..15] A[0..20] C1 0.1uF R27 10K 3 C2 0.1uF DC3V D[0..15] A[0..20] 3 C3 0.
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A B C D 1 FPDAT[0..15] FPSHIFT2 FPLINE FPFRAME FPSHIFT FPDAT[0..15] WE# RAS# UCAS# LCAS# MA[0..9] 2 FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 MA[0..9] MD[0..
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Evaluation Board User Manual Issue Date: 01/02/05 A B C D 1 1 A[0..20] M/R# RD# WE1# RESET# D[0..15] A[0..20] D[0..
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Page 22 Epson Research and Development Vancouver Design Center 6 Component Placement Figure 6-1: Component Placement S5U13505-D9000 X23A-G-002-04 Evaluation Board User Manual Issue Date: 01/02/05
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S1D13505 Embedded RAMDAC LCD/CRT Controller Power Consumption Document Number: X23A-G-006-03 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-006-03 Power Consumption Issue Date: 01/02/05
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Page 3 Epson Research and Development Vancouver Design Center 1 S1D13505 Power Consumption S1D13505 power consumption is affected by many system design variables. • Input clock frequency (CLKI): the CLKI frequency determines the LCD frame-rate, CPU performance to memory, and other functions – the higher the input clock frequency, the higher the frame-rate, performance and power consumption.
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Page 4 Epson Research and Development Vancouver Design Center 1.1 Conditions Table 1-1: “S1D13505 Total Power Consumption” below gives an example of a specific environment and its effects on power consumption. Table 1-1: S1D13505 Total Power Consumption Test Condition VDD = 3.3V ISA Bus (8MHz) Total Power Consumption Gray Shades / Colors Power Save Mode Active Software Hardware Input Clock = 6MHz Black-and-White LCD Panel = 320x240 4-bit Single Monochrome 4 Gray Shades 16 Gray Shades 18.6mW 20.
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S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the Philips MIPS PR31500/PR31700 Processor Document Number: X23A-G-001-07 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-001-07 Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 01/02/05
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Page 3 Epson Research and Development Vancouver Design Center Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfacing to the PR31500/PR31700 . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 S1D13505 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 PR31500/PR31700 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . 9 3.2 PR31500/PR31700 Host Bus Interface Signals . . . . . . .
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Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-001-07 Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 01/02/05
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Page 5 Epson Research and Development Vancouver Design Center List of Tables Table 3-1: PR31500/PR31700 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . 9 Table 4-1: S1D13505 Configuration for Direct Connection. . . . . . . . . . . . . . . . . . . . . . 12 Table 4-2: PR31500/PR31700 to PC Card Slots Address Remapping for Direct Connection . . . . 13 List of Figures Figure 4-1: Typical Implementation of Direct Connection . . . . . . . . . . . . . . . . . . . . . . .
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Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-001-07 Interfacing to the Philips MIPS PR31500/PR31700 Processor Issue Date: 01/02/05
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Page 7 Epson Research and Development Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the Philips MIPS PR31500/PR31700 Processor. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate.
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Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PR31500/PR31700 The Philips MIPS PR31500/PR31700 processor supports up to two PC Card (PCMCIA) slots. It is through this host bus interface that the S1D13505 connects to the PR31500/PR31700 processor. The S1D13505 can be successfully interfaced using one of the following configurations: • Direct connection to the PR31500/PR31700 (see Section 4, “Direct Connection to the Philips PR31500/PR31700” on page 11).
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Page 9 Epson Research and Development Vancouver Design Center 3 S1D13505 Host Bus Interface The S1D13505 implements a 16-bit host bus interface specifically for interfacing to the PR31500/PR31700 microprocessor. The PR31500/PR31700 host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset, the bus interface signals assume their selected configuration. For details on S1D13505 configuration, see Section 4.2, “S1D13505 Configuration” on page 12.
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Page 10 Epson Research and Development Vancouver Design Center 3.2 PR31500/PR31700 Host Bus Interface Signals When the S1D13505 is configured to operate with the PR31500/PR31700, the host interface requires the following signals: • BUSCLK is a clock input required by the S1D13505 host bus interface. It is separate from the input clock (CLKI) and should be driven by the PR31500/PR31700 bus clock output DCLKOUT.
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Page 11 Epson Research and Development Vancouver Design Center 4 Direct Connection to the Philips PR31500/PR31700 The S1D13505 was specifically designed to support the Philips MIPS PR31500/PR31700 processor. When configured, the S1D13505 will utilize one of the PC Card slots supported by the processor. 4.1 Hardware Description In this example implementation, the S1D13505 occupies one PC Card slot and resides in the Attribute and IO address range.
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Page 12 Epson Research and Development Vancouver Design Center The host interface control signals of the S1D13505 are asynchronous with respect to the S1D13505 bus clock. This gives the system designer full flexibility to choose the appropriate source (or sources) for CLKI and BUSCLK. The choice of whether both clocks should be the same, whether to use DCLKOUT as clock source, and whether an external or internal clock divider is needed, should be based on the desired: • pixel and frame rates.
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Page 13 Epson Research and Development Vancouver Design Center 4.3 Memory Mapping and Aliasing The PR31500/PR31700 uses a portion of the PC Card Attribute and IO space to access the S1D13505. The S1D13505 responds to both PC Card Attribute and IO bus accesses, thus freeing the programmer from having to set the PR31500/PR31700 Memory Configuration Register 3 bit CARD1IOEN (or CARD2IOEN if slot 2 is used).
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Page 14 Epson Research and Development Vancouver Design Center 5 System Design Using the IT8368E PC Card Buffer In a system design using one or two ITE IT8368E PC Card and multiple-function IO buffers, the S1D13505 can be interfaced so as to share one of the PC Card slots. 5.
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Epson Research and Development Vancouver Design Center Page 15 5.2 IT8368E Configuration The ITE IT8368E has been specifically designed to support EPSON LCD/CRT controllers. Older EPSON Controllers not supporting a direct interface to the Philips processor can utilize the IT8368E MFIO pins to provide the necessary control signals, however when using the S1D13505 this is not necessary as the Direct Connection described in Section 4, “Direct Connection to the Philips PR31500/PR31700” on page 11 can be used.
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Page 16 Epson Research and Development Vancouver Design Center 6 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source. The Windows CE v2.
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Epson Research and Development Vancouver Design Center Page 17 7 References 7.1 Documents • Philips Electronics, PR31500/PR31700 Preliminary Specifications. • Epson Research and Development, Inc., S1D13505 Hardware Functional Specification, Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X23A-G-004-xx. • Epson Research and Development, Inc.
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Page 18 Epson Research and Development Vancouver Design Center 8 Technical Support 8.1 EPSON LCD/CRT Controllers (S1D13505) Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd.
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S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the PC Card Bus Document Number: X23A-G-005-06 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-005-06 Interfacing to the PC Card Bus Issue Date: 01/02/05
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Page 3 Epson Research and Development Vancouver Design Center Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfacing to the PC Card Bus 2.1 The PC Card System Bus . . 2.1.1 PC Card Overview . . 2.1.2 Memory Access Cycles 3 S1D13505 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 PC Card Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . 11 3.
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Page 5 Epson Research and Development Vancouver Design Center List of Tables Table 3-1: PC Card Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 4-2: Register/Memory Mapping for Typical Implementation . . . . . . . . . . . . . . . . . 16 List of Figures Figure 2-1: PC Card Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-005-06 Interfacing to the PC Card Bus Issue Date: 01/02/05
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Page 7 Epson Research and Development Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the PC Card (PCMCIA) bus. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate. Please check the Epson Electronics America website at http://www.eea.epson.
PAGE 450
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PC Card Bus 2.1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness. This section is an overview of the operation of the 16-bit PC Card interface conforming to the PCMCIA 2.0/JEIDA 4.1 Standard (or later). 2.1.
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Page 9 Epson Research and Development Vancouver Design Center During a read cycle, OE# (output enable) is driven low. A write cycle is specified by driving OE# high and driving the write enable signal (WE#) low. The cycle can be lengthened by driving WAIT# low for the time needed to complete the cycle. Figure 2-1: illustrates a typical memory access read cycle on the PC Card bus.
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Page 10 Epson Research and Development Vancouver Design Center Figure 2-2: illustrates a typical memory access write cycle on the PC Card bus.
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Page 11 Epson Research and Development Vancouver Design Center 3 S1D13505 Host Bus Interface The S1D13505 implements a 16-bit PC Card (PCMCIA) host bus interface which is used to interface to the PC Card bus. The PC Card host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration. For details on S1D13505 configuration, see Section 4.2, “S1D13505 Hardware Configuration” on page 15.
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Page 12 Epson Research and Development Vancouver Design Center 3.2 PC Card Host Bus Interface Signals The S1D13505 PC Card host bus interface is designed to support processors which interface the S1D13505 through the PC Card bus. The S1D13505 PC Card host bus interface requires the following signals from the PC Card bus. • BUSCLK is a clock input which is required by the S1D13505 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.
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Epson Research and Development Vancouver Design Center Page 13 4 PC Card to S1D13505 Interface 4.1 Hardware Description The S1D13505 is designed to directly support a variety of CPUs, providing an interface to each processor’s unique “local bus”. However, in order to provide support for processors not having an appropriate local bus, the S1D13505 supports a specific PC Card interface. The S1D13505 provides a “glueless” interface to the PC Card bus except for the following.
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Page 14 Epson Research and Development Vancouver Design Center The following diagram shows a typical implementation of the PC Card to S1D13505 interface. S1D13505 PC Card socket -OE -WE RD# WE0# -CE1 -CE2 RD/WR# WE1# RESET VDD RESET# BS# CS# A21 M/R# A[20:0] A[21:0] D[15:0] AB[20:0] DB[15:0] 15K WAIT# WAIT# BUSCLK Oscillator CLKI Note: When connecting the S1D13505 RESET# pin, the system designer should be aware of all conditions that may reset the S1D13505 (e.g.
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Page 15 Epson Research and Development Vancouver Design Center 4.2 S1D13505 Hardware Configuration The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx. The table below shows only those configuration settings important to the PC Card host bus interface.
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Page 16 Epson Research and Development Vancouver Design Center 4.4 Register/Memory Mapping The S1D13505 is a memory mapped device. The internal registers require 47 bytes and are mapped in the lower PC Card memory address space starting at zero.The display buffer requires 2M bytes and is mapped in the third and fourth megabytes of the PC Card address space (ranging from 200000h to 3FFFFFh).
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Epson Research and Development Vancouver Design Center Page 17 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source. The Windows CE v2.
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Page 18 Epson Research and Development Vancouver Design Center 6 References 6.1 Documents • PC Card (PCMCIA) Standard, March 1997 • Epson Research and Development, Inc., S1D13505 Hardware Functional Specification, Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S1D13505 Programming Notes and Examples, Document Number X23A-G-003-xx. • Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X23A-G-004-xx. 6.
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Page 19 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 Epson LCD/CRT Controllers (S1D13505) Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc.
PAGE 462
Page 20 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-005-06 Interfacing to the PC Card Bus Issue Date: 01/02/05
PAGE 463
S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the NEC VR4102/VR4111™ Microprocessors Document Number: X23A-G-007-06 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
PAGE 464
Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-007-06 Interfacing to the NEC VR4102/VR4111™ Microprocessors Issue Date: 01/02/05
PAGE 465
Page 3 Epson Research and Development Vancouver Design Center Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfacing to the VR4102/VR4111 . . . . . . . . . 2.1 The NEC VR4102/VR4111 System Bus . . . . . 2.1.1 Overview . . . . . . . . . . . . . . . . . . . 2.1.2 LCD Memory Access Cycles . . . . . . . . . 3 S1D13505 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.
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Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-007-06 Interfacing to the NEC VR4102/VR4111™ Microprocessors Issue Date: 01/02/05
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Page 5 Epson Research and Development Vancouver Design Center List of Tables Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4-1: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 List of Figures Figure 2-1: NEC VR4102/VR4111 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4-1: NEC VR4102/VR4111 to S1D13505 Configuration Schematic . . . . . . . . . . . . . .
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Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-007-06 Interfacing to the NEC VR4102/VR4111™ Microprocessors Issue Date: 01/02/05
PAGE 469
Page 7 Epson Research and Development Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the NEC VR4102TM (µPD30102) or VR4111TM (µPD30111) Microprocessors. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate.
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Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the VR4102/VR4111 2.1 The NEC VR4102/VR4111 System Bus The VR-Series family of microprocessors features a high-speed synchronous system bus typical of modern microprocessors. Designed with external LCD controller support and Windows CE based embedded consumer applications in mind, the VR4102/VR4111 offers a highly integrated solution for portable systems.
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Page 9 Epson Research and Development Vancouver Design Center 2.1.2 LCD Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus (ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle. The high byte enable (SHB#) in conjunction with address bit 0 allows for byte steering.
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Page 10 Epson Research and Development Vancouver Design Center 3 S1D13505 Host Bus Interface The S1D13505 directly supports multiple processors. The S1D13505 implements a 16-bit MIPS/ISA Host Bus Interface which is most suitable for direct connection to the VR4102/VR4111 microprocessor. The MIPS/ISA host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
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Epson Research and Development Vancouver Design Center Page 11 3.2 Host Bus Interface Signals Descriptions The S1D13505 MIPS/ISA Host Bus Interface requires the following signals. • BUSCLK is a clock input which is required by the S1D13505 Host Bus Interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock.
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Page 12 Epson Research and Development Vancouver Design Center 4 VR4102/VR4111 to S1D13505 Interface 4.1 Hardware Description The NEC VR4102/VR4111 Microprocessors are specifically designed to support an external LCD controller. They provide the necessary internal address decoding and control signals. The diagram below shows a typical implementation utilizing the S1D13505.
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Page 13 Epson Research and Development Vancouver Design Center 4.2 S1D13505 Hardware Configuration The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx. The table below shows those configuration settings important to the NEC VR4102/VR4111 CPU interface.
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Page 14 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source. The Windows CE v2.
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Page 15 Epson Research and Development Vancouver Design Center 6 References 6.1 Documents • NEC Electronics Inc., VR4102 Preliminary Users Manual, Document Number U12739EJ2V0UM00. • NEC Electronics Inc., VR4111 Preliminary Users Manual, Document Number U13137EJ2V0UM00. • Epson Research and Development, Inc., S1D13505 Hardware Functional Specification, Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S5U13505B00C Rev. 1.
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Page 16 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13505) Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc.
PAGE 479
S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the Motorola MPC821 Microprocessor Document Number: X23A-G-008-05 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-008-05 Interfacing to the Motorola MPC821 Microprocessor Issue Date: 01/02/05
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Page 3 Epson Research and Development Vancouver Design Center Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfacing to the MPC821 . . . . . . . . . . . . . . . . 2.1 The MPC8xx System Bus . . . . . . . . . . . . . 2.2 MPC821 Bus Overview . . . . . . . . . . . . . 2.2.1 Normal (Non-Burst) Bus Transactions . . . . . . . 2.2.2 Burst Cycles . . . . . . . . . . . . . . . . . . . . . 2.3 Memory Controller Module . . . . . . . . . . .
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Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-008-05 Interfacing to the Motorola MPC821 Microprocessor Issue Date: 01/02/05
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Page 5 Epson Research and Development Vancouver Design Center List of Tables Table 3-1: PowerPC Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 4-1: List of Connections from MPC821ADS to S1D13505 . . . . . . . . . . . . . . . . . . 16 Table 4-2: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . 18 List of Figures Figure 2-1: Power PC Memory Read Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-008-05 Interfacing to the Motorola MPC821 Microprocessor Issue Date: 01/02/05
PAGE 485
Page 7 Epson Research and Development Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the Motorola MPC821 processor. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate. Please check the Epson Electronics America Website at http://www.eea.
PAGE 486
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MPC821 2.1 The MPC8xx System Bus The MPC8xx family of processors feature a high-speed synchronous system bus typical of modern RISC microprocessors. This section provides an overview of the operation of the CPU bus in order to establish interface requirements. 2.2 MPC821 Bus Overview The MPC8xx microprocessor family uses a synchronous address and data bus.
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Page 9 Epson Research and Development Vancouver Design Center 2.2.1 Normal (Non-Burst) Bus Transactions A data transfer is initiated by the bus master by placing the memory address on address lines A0 through A31 and driving TS (Transfer Start) low for one clock cycle. Several control signals are also provided with the memory address: • TSIZ[0:1] (Transfer Size) -- indicates whether the bus cycle is 8, 16, or 32-bit. • RD/WR -- set high for read cycles and low for write cycles.
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Page 10 Epson Research and Development Vancouver Design Center Figure 2-2: “Power PC Memory Write Cycle” on page 10 illustrates a typical memory write cycle on the Power PC system bus. SYSCLK TS TA A[0:31] RD/WR TSIZ[0:1], AT[0:3] D[0:31] Transfer Start Valid Wait States Transfer Complete Next Transfer Starts Figure 2-2: Power PC Memory Write Cycle If an error occurs, TEA (Transfer Error Acknowledge) is asserted and the bus cycle is aborted.
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Page 11 Epson Research and Development Vancouver Design Center If a peripheral is not capable of supporting burst cycles, it can assert Burst Inhibit (BI) simultaneously with TA, and the processor will revert to normal bus cycles for the remaining data transfers. Burst cycles are mainly intended to facilitate cache line fills from program or data memory.
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Page 12 Epson Research and Development Vancouver Design Center 2.3.2 User-Programmable Machine (UPM) The UPM is typically used to control memory types, such as Dynamic RAMs, which have complex control or address multiplexing requirements. The UPM is a general purpose RAM-based pattern generator which can control address multiplexing, wait state generation, and five general-purpose output lines on the MPC821. Up to 64 pattern locations are available, each 32 bits wide.
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Page 13 Epson Research and Development Vancouver Design Center 3 S1D13505 Host Bus Interface The S1D13505 implements a 16-bit native PowerPC host bus interface which is used to interface to the MPC821 microprocessor. The PowerPC host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration. For details on S1D13505 configuration, see Section 4.3, “S1D13505 Hardware Configuration” on page 18.
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Page 14 Epson Research and Development Vancouver Design Center 3.2 PowerPC Host Bus Interface Signals The interface requires the following signals: • BUSCLK is a clock input which is required by the S1D13505 host bus interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock. • The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the PowerPC bus address (A[11:31]) and data bus (D[0:15]), respectively.
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Page 15 Epson Research and Development Vancouver Design Center 4 MPC821 to S1D13505 Interface 4.1 Hardware Description The S1D13505 provides native Power PC bus support making it very simple to interface the two devices. This application note describes both the environment necessary to connect the S1D13505 to the MPC821 native system bus and the connection between the S5U13505B00B Evaluation Board and the Motorola MPC821 Application Development System (ADS).
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Page 16 Epson Research and Development Vancouver Design Center Table 4-1:,“List of Connections from MPC821ADS to S1D13505” on page 16 shows the connections between the pins and signals of the MPC821 and the S1D13505. Note The interface was designed using a Motorola MPC821 Application Development System (ADS). The ADS board has 5 volt logic connected to the data bus, so the interface included two 74F245 octal buffers on D[0:15] between the ADS and the S1D13505.
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Page 17 Epson Research and Development Vancouver Design Center Table 4-1: List of Connections from MPC821ADS to S1D13505 (Continued) MPC821 Signal Name D8 D9 D10 D11 D12 D13 D14 D15 SRESET SYSCLK CS4 TS TA R/W TSIZ0 TSIZ1 BI Gnd MPC821ADS Connector and Pin Name P12-A15 P12-C15 P12-D15 P12-A14 P12-B14 P12-D14 P12-B13 P12-C13 P9-D15 P9-C2 P6-D13 P6-B7 P6-B6 P6-D8 P6-B18 P6-C18 P6-B9 P12-A1, P12-B1, P12-A2, P12-B2, P12-A3, P12-B3, P12-A4, P12-B4, P12-A5, P12-B5, P12-A6, P12-B6, P12-A7 S1D13505 Signal Name
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Page 18 Epson Research and Development Vancouver Design Center 4.3 S1D13505 Hardware Configuration The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx. The following table shows those configuration settings important to the MPC821 host bus interface.
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Page 19 Epson Research and Development Vancouver Design Center 4.5 MPC821 Chip Select Configuration Chip select 4 is used to control the S1D13505. The following options are selected in the base address register (BR4): • BA[0:16] = 0000 0000 0100 0000 0 – set starting address of S1D13505 to 40 0000h. • AT[0:2] = 0 – ignore address type bits. • PS[0:1] = 1:0 – memory port size is 16-bit. • PARE = 0 – disable parity checking. • WP = 0 – disable write protect.
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Page 20 Epson Research and Development Vancouver Design Center 4.6 Test Software The test software is very simple. It configures chip select 4 (CS4) on the MPC821 to map the S1D13505 to an unused 4M byte block of address space. Next, it loads the appropriate values into the option register for CS4 and writes the value 0 to the S1D13505 register REG[1Bh] to enable the S1D13505 host interface. Lastly, the software runs a tight loop that reads the S1D13505 Revision Code Register REG[00h].
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Epson Research and Development Vancouver Design Center Page 21 5 Software Test utilities and Windows® CE display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source. The Windows CE display drivers can be customized by the OEM for different panel types, resolutions and color depths only by modifying the source.
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Page 22 Epson Research and Development Vancouver Design Center 6 References 6.1 Documents • Motorola Inc., Power PC MPC821 Portable Systems Microprocessor User’s Manual; Motorola Publication no. MPC821UM/AD. • Epson Research and Development, Inc., S1D13505 Hardware Functional Specification, Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S5U13505B00B Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X19A-G-001-xx. 6.
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Page 23 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 EPSON LCD/CRT Controllers (S1D13505) Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc.
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Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-008-05 Interfacing to the Motorola MPC821 Microprocessor Issue Date: 01/02/05
PAGE 503
S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the Toshiba MIPS TX3912 Processor Document Number: X23A-G-010-04 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
PAGE 504
Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-010-04 Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 01/02/05
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Page 3 Epson Research and Development Vancouver Design Center Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfacing to the TX3912 3 S1D13505 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 TX3912 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . 9 3.2 TX3912 Host Bus Interface Signals . . . . . . . . . . . . . . . . . . . . . .
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Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-010-04 Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 01/02/05
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Page 5 Epson Research and Development Vancouver Design Center List of Tables Table 3-1: TX3912 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4-1: S1D13505 Configuration for Direct Connection. . . . . . . . . . . . . . . . . . . . . . 12 Table 4-2: TX3912 to PC Card Slots Address Remapping for Direct Connection . . . . . . . . . . 13 List of Figures Figure 4-1: Typical Implementation of Direct Connection . . . . . . . . . . . . . . . . . . . . . . .
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Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-010-04 Interfacing to the Toshiba MIPS TX3912 Processor Issue Date: 01/02/05
PAGE 509
Page 7 Epson Research and Development Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the Toshiba MIPS TX3912 Processor. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate. Please check the Epson Electronics America website at http://www.
PAGE 510
Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the TX3912 The Toshiba MIPS TX3912 processor supports up to two PC Card (PCMCIA) slots. It is through this host bus interface that the S1D13505 connects to the TX3912 processor. The S1D13505 can be successfully interfaced using one of the following configurations: • Direct connection to the TX3912 (see Section 4, “Direct Connection to the Toshiba TX3912” on page 11).
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Page 9 Epson Research and Development Vancouver Design Center 3 S1D13505 Host Bus Interface The S1D13505 implements a 16-bit host bus interface specifically for interfacing to the TX3912 microprocessor. The TX3912 host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset, the bus interface signals assume their selected configuration. For details on S1D13505 configuration, see Section 4.2, “S1D13505 Configuration” on page 12.
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Page 10 Epson Research and Development Vancouver Design Center 3.2 TX3912 Host Bus Interface Signals When the S1D13505 is configured to operate with the TX3912, the host interface requires the following signals: • BUSCLK is a clock input required by the S1D13505 host bus interface. It is separate from the input clock (CLKI) and should be driven by the TX3912 bus clock output DCLKOUT.
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Page 11 Epson Research and Development Vancouver Design Center 4 Direct Connection to the Toshiba TX3912 The S1D13505 was specifically designed to support the Toshiba MIPS TX3912 processor. When configured, the S1D13505 will utilize one of the PC Card slots supported by the processor. 4.1 Hardware Description In this example implementation, the S1D13505 occupies one PC Card slot and resides in the Attribute and IO address range.
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Page 12 Epson Research and Development Vancouver Design Center The host interface control signals of the S1D13505 are asynchronous with respect to the S1D13505 bus clock. This gives the system designer full flexibility to choose the appropriate source (or sources) for CLKI and BUSCLK. The choice of whether both clocks should be the same, whether to use DCLKOUT as clock source, and whether an external or internal clock divider is needed, should be based on the desired: • pixel and frame rates.
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Page 13 Epson Research and Development Vancouver Design Center 4.3 Memory Mapping and Aliasing The TX3912 uses a portion of the PC Card Attribute and IO space to access the S1D13505. The S1D13505 responds to both PC Card Attribute and IO bus accesses, thus freeing the programmer from having to set the TX3912 Memory Configuration Register 3 bit CARD1IOEN (or CARD2IOEN if slot 2 is used). As a result, the TX3912 sees the S1D13505 on its PC Card slot as described in the table below.
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Page 14 Epson Research and Development Vancouver Design Center 5 System Design Using the IT8368E PC Card Buffer In a system design using one or two ITE IT8368E PC Card and multiple-function IO buffers, the S1D13505 can be interfaced so as to share one of the PC Card slots. 5.
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Epson Research and Development Vancouver Design Center Page 15 5.2 IT8368E Configuration The ITE IT8368E has been specifically designed to support EPSON LCD/CRT controllers. Older EPSON Controllers not supporting a direct interface to the Toshiba processor can utilize the IT8368E MFIO pins to provide the necessary control signals, however when using the S1D13505 this is not necessary as the Direct Connection described in Section 4, “Direct Connection to the Toshiba TX3912” on page 11 can be used.
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Page 16 Epson Research and Development Vancouver Design Center 6 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source. The Windows CE v2.
PAGE 519
Page 17 Epson Research and Development Vancouver Design Center 7 References 7.1 Documents • Toshiba America Electrical Components, Inc., TX3905/12 Specification. • Epson Research and Development, Inc., S1D13505 Hardware Functional Specification, Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X23A-G-004-xx. • Epson Research and Development, Inc.
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Page 18 Epson Research and Development Vancouver Design Center 8 Technical Support 8.1 EPSON LCD/CRT Controllers (S1D13505) Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com Taiwan, R.O.C. Epson Taiwan Technology & Trading Ltd.
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S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the NEC VR4121™ Microprocessor Document Number: X23A-G-011-04 Copyright © 1998, 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-011-04 Interfacing to the NEC VR4121™ Microprocessor Issue Date: 01/02/05
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Page 3 Epson Research and Development Vancouver Design Center Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfacing to the NEC VR4121 . . 2.1 The NEC VR4121 System Bus . . 2.1.1 Overview . . . . . . . . . . 2.1.2 LCD Memory Access Cycles 3 S1D13505 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 10 3.
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Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-011-04 Interfacing to the NEC VR4121™ Microprocessor Issue Date: 01/02/05
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Page 5 Epson Research and Development Vancouver Design Center List of Tables Table 3-1: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 4-1: Summary of Power-On-Reset Options . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 List of Figures Figure 2-1: NEC VR4121 Read/Write Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 4-1: NEC VR4121 to S1D13505 Configuration Schematic . . . . . . . . . . . . . . . . . . .
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Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-011-04 Interfacing to the NEC VR4121™ Microprocessor Issue Date: 01/02/05
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Page 7 Epson Research and Development Vancouver Design Center 1 Introduction This application note describes the hardware and software environment necessary to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the NEC VR4121TM (µPD30121) microprocessor. The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate.
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Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC V R 4121 2.1 The NEC VR4121 System Bus The VR-Series family of microprocessors features a high-speed synchronous system bus typical of modern microprocessors. Designed with external LCD controller support and Windows CE based embedded consumer applications in mind, the VR4121 offers a highly integrated solution for portable systems.
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Page 9 Epson Research and Development Vancouver Design Center 2.1.2 LCD Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus (ADD[25:0]), the LCD chip select (LCDCS#) is driven low. The read or write enable signals (RD# or WR#) are driven low for the appropriate cycle and LCDRDY is driven low to insert wait states into the cycle. The high byte enable (SHB#) in conjunction with address bit 0 allows for byte steering.
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Page 10 Epson Research and Development Vancouver Design Center 3 S1D13505 Host Bus Interface The S1D13505 directly supports multiple processors. The S1D13505 implements a 16-bit MIPS/ISA Host Bus Interface which is most suitable for direct connection to the VR4121 microprocessor. The MIPS/ISA host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration. For details on S1D13505 configuration, see Section 4.
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Epson Research and Development Vancouver Design Center Page 11 3.2 Host Bus Interface Signal Descriptions The S1D13505 MIPS/ISA Host Bus Interface requires the following signals. • BUSCLK is a clock input which is required by the S1D13505 Host Bus Interface. It is separate from the input clock (CLKI) and is typically driven by the host CPU system clock. • The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the VR4121 address (ADD[20:0]) and data bus (DAT[15:0]), respectively.
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Page 12 Epson Research and Development Vancouver Design Center 4 V R 4121 to S1D13505 Interface 4.1 Hardware Description The NEC VR4121 microprocessor is specifically designed to support an external LCD controller. It provides all the necessary internal address decoding and control signals required by the S1D13505. The diagram below shows a typical implementation utilizing the S1D13505.
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Page 13 Epson Research and Development Vancouver Design Center 4.2 S1D13505 Configuration The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx. The table below shows those configuration settings relevant to the MIPS/ISA host bus interface used by the NEC VR4121 microprocessor.
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Page 14 Epson Research and Development Vancouver Design Center 4.4 Memory Mapping and Aliasing The NEC VR4121 provides the internal address decoding required by an external LCD controller. The physical address range from 0A00 0000h to 0AFF FFFFh (16M bytes) is reserved for use by an external LCD controller (e.g. S1D13505). The S1D13505 supports up to 2M bytes of display buffer.
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Epson Research and Development Vancouver Design Center Page 15 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source. The Windows CE v2.
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Page 16 Epson Research and Development Vancouver Design Center 6 References 6.1 Documents • NEC Electronics Inc., VR4121 Preliminary Users Manual, Document Number U13569EJ1V0UM00. • Epson Research and Development, Inc., S1D13505 Hardware Functional Specification, Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X23A-G-004-xx. • Epson Research and Development, Inc.
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Page 17 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 Epson LCD/CRT Controllers (S1D13505) Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc.
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Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-011-04 Interfacing to the NEC VR4121™ Microprocessor Issue Date: 01/02/05
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S1D13505 Embedded RAMDAC LCD/CRT Controller Interfacing to the NEC V832™ Microprocessor Document Number: X23A-G-012-02 Copyright © 2001 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc.
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Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-012-02 Interfacing to the NEC V832™ Microprocessor Issue Date: 01/02/05
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Page 3 Epson Research and Development Vancouver Design Center Table of Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Interfacing to the NEC V832 . . . . 2.1 The NEC V832 System Bus . . . 2.1.1 Overview . . . . . . . . . . 2.1.2 Access Cycles . . . . . . . . 3 S1D13505 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . . 10 3.
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Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-012-02 Interfacing to the NEC V832™ Microprocessor Issue Date: 01/02/05
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Page 5 Epson Research and Development Vancouver Design Center List of Tables Table 3-1: Table 4-1: Table 4-2: Table 4-3: Host Bus Interface Pin Mapping . . . . . . . . . . Summary of Power-On/Reset Options . . . . . . . NEC V832 Wait States vs. Bus Clock Frequency . NEC V832 IO Address Range For Each CSn Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13505 X23A-G-012-02 Interfacing to the NEC V832™ Microprocessor Issue Date: 01/02/05
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Page 7 Epson Research and Development Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to provide an interface between the S1D13505 Embedded RAMDAC LCD/CRT Controller and the NEC V832TM microprocessor (µPD705102). The designs described in this document are presented only as examples of how such interfaces might be implemented. This application note will be updated as appropriate.
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Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC V832 2.1 The NEC V832 System Bus This section provides an overview of the operation of the CPU bus in order to establish interface requirements. 2.1.1 Overview The NEC V832 is designed around the RISC architecture developed by MIPS. This microprocessor is based on the 32-bit V830 CPU core. The CPU communicates with external devices via the Bus Control Unit (BCU).
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Page 9 Epson Research and Development Vancouver Design Center 2.1.2 Access Cycles Once an address in the appropriate range is placed on the external address bus (A[23:1]), the corresponding chip select (CSn) is driven low. The read or write enable signals (IORD or IOWR) are driven low and READY is driven low by the S1D13505 to insert wait states into the cycle. The byte enable signals (LLBEN and LUBEN) allow byte steering. The following figure illustrates typical NEC V832 memory-mapped IO access cycles.
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Page 10 Epson Research and Development Vancouver Design Center 3 S1D13505 Host Bus Interface The S1D13505 directly supports multiple processors. The S1D13505 implements a 16-bit PC Card (PCMCIA) Host Bus Interface which is most suitable for direct connection to the V832 microprocessor. The PC Card host bus interface is selected by the S1D13505 on the rising edge of RESET#. After releasing reset the bus interface signals assume their selected configuration.
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Epson Research and Development Vancouver Design Center Page 11 3.2 Host Bus Interface Signal Descriptions The S1D13505 PC Card Host Bus Interface requires the following signals. • BUSCLK is a clock input which is required by the S1D13505 Host Bus Interface. It is driven by the V832 signal SDCLKOUT. • The address inputs AB[20:0], and the data bus DB[15:0], connect directly to the V832 address (A[20:0]) and data bus (D[15:0]), respectively. MD4 must be set to select little endian mode upon reset.
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Page 12 Epson Research and Development Vancouver Design Center 4 V832 to S1D13505 Interface 4.1 Hardware Description The NEC V832 microprocessor features configurable chip select lines which can easily be used for an external LCD controller. It provides all the necessary internal address decoding and control signals required by the S1D13505. The diagram below shows a typical implementation utilizing the S1D13505.
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Page 13 Epson Research and Development Vancouver Design Center 4.2 S1D13505 Hardware Configuration The S1D13505 latches MD15 through MD0 to allow selection of the bus mode and other configuration data on the rising edge of RESET#. For details on configuration, refer to the S1D13505 Hardware Functional Specification, document number X23A-A-001-xx. The table below shows those configuration settings relevant to the PC Card host bus interface used by the NEC V832 microprocessor.
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Page 14 Epson Research and Development Vancouver Design Center 4.3 NEC V832 Configuration The NEC V832 should access the S1D13505 in non-burst mode only. This is ensured by using any one of the CS3 to CS6 lines to control the S1D13505 and setting that line to respond to IO operations using the NEC V832 BCTC register. For example, if line CS5 is designated to control the S1D13505, then bit 5 (CT5) of the BCTC register should be set to 1 (IO cycle).
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Page 15 Epson Research and Development Vancouver Design Center 4.4 Memory Mapping and Aliasing The CSn line selected determines the address range to be reserved for the S1D13505. The table below summarizes the S1D13505 address mapping.
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Page 16 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows® CE v2.0 display drivers are available for the S1D13505. Full source code is available for both the test utilities and the drivers. The test utilities are configurable for different panel types using a program called 13505CFG, or by directly modifying the source. The Windows CE v2.
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Page 17 Epson Research and Development Vancouver Design Center 6 References 6.1 Documents • NEC Electronics Inc., V832 Preliminary Users Manual, Document Number U13577EJ1V0UM00. • Epson Research and Development, Inc., S1D13505 Hardware Functional Specification, Document Number X23A-A-001-xx. • Epson Research and Development, Inc., S5U13505B00C Rev. 1.0 ISA Bus Evaluation Board User Manual, Document Number X23A-G-004-xx. • Epson Research and Development, Inc.
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Page 18 Epson Research and Development Vancouver Design Center 7 Technical Support 7.1 Epson LCD/CRT Controllers (S1D13505) Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 North America Epson Electronics America, Inc.