Specifications

IC Data Sheets
EN 61Q552.2L LA 8.
2011-Jul-15
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8.8 Diagram Ethernet & Service B04C, LAN8710A-EZKH (IC 7E10)
Figure 8-8 Internal block diagram and pin configuration
18770_302_100217.eps
100217
Block diagram
Pinning information
10M Rx
Logic
100M Rx
Logic
DSP System:
Clock
Data Recovery
Equalizer
Analog-to-
Digital
100M PLL
Squelch &
Filters
10M PLL
Receive Section
Central
Bias
HP Auto-MDIX
Management
Control
SMI
RMII / MII Logic
TXP / TXN
TXD[0:3]
TXEN
TXER
TXCLK
RXD[0:3]
RXDV
RXER
RXCLK
CRS
COL/CRS_DV
MDC
MDIO
LED1
LED2
LED Circuitry
MODE Control
nINT
nRST
RXP / RXN
10M Tx
Logic
10M
Transmitter
100M Tx
Logic
100M
Transmitter
Transmit Section
PLL
XTAL1/CLKIN
XTAL2
MODE0
MODE1
MODE2
PHY
Address
Latches
PHYAD[0:2]
Auto-
Negotiation
Interrupt
Generator
RMIISEL
MDIX
Control
Reset
Control
RBIAS
VDD2A
LED2/nINTSEL
LED1/REGOFF
XTAL2
XTAL1/CLKIN
VDDCR
RXD3/PHYAD2
RXCLK/PHYAD1
RXD2/RMIISEL
RXD1/MODE1
RXD0/MDE0
VDDIO
RXER/RXD4/PHYAD0
CRS
MDIO
COL/CRS_DV/MODE2
TXD2
MDC
nRST
nINT/TXER/TXD4
TXD0
TXEN
TXCLK
TXD1
RBIAS
TXD3
TXN
RXDV RXN
VDD1A TXP
RXP
1
2
3
4
5
6
7
8
SMSC
LAN8710/LAN8710i
32 PIN QFN
(Top View)
9
10
11
12
13
14
15
22
21
20
19
18
17
28
27
26
2516
24
23
32
31
30 29
VSS