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65213 2.3 2 4-1 Wire Dressing Dressing 4.3 Mechanics 4 Assembly Removal 3139 123 xxxxx 4.3.7 7 7.4.1 back to div. table 7.2 Descriptions You can download this information from the following websites: http://www.philips.com/support http://www.p4c.philips.com Directions for Use Blockbuster 11-2 40PFL6606D/78 2011-Apr-22 2.
2.3.2 2.3.1 2.3 6 7 7 jq jq jq 4 - AV IN: Cinch: Video CVBS - In, Audio - In Rd - Audio R 0.5 VRMS / 10 kohm Wh - Audio L 0.5 VRMS / 10 kohm Ye - Video CVBS 1 VPP / 75 ohm 12345678 Figure 2-2 Ethernet connector 10000_025_090121.eps 090121 5 - RJ45: Ethernet Rear Connections - Bottom jq jq H k j jq jq jq jq jq 3 - Cinch: Audio - In (VGA/DVI) Rd - Audio R 0.5 VRMS / 10 kohm Wh - Audio L 0.
Q552.2L LA - D2+ - Shield - D2- D1+ - Shield - D1- D0+ - Shield - D0- CLK+ - Shield - CLK- Easylink/CEC - ARC - DDC_SCL - DDC_SDA - Ground - +5V - HPD - Ground 10 15 j j j H H H H j H j j j j Gnd Gnd Gnd Gnd +5 V Gnd DDC data 0-5V 0-5V DDC clock D j H j j H j j H j j H j jk k j jk H j j H 0.7 VPP / 75 ohm 0.7 VPP / 75 ohm 0.7 VPP / 75 ohm Refer to chapter Block Diagrams for PWB/CBA locations. Chassis Overview - Video Red - Video Green - Video Blue - n.c.
• Measure the voltages and waveforms with regard to the chassis (= tuner) ground (H), or hot ground (I), depending on the tested area of circuitry. The voltages and waveforms shown in the diagrams are indicative. Measure them in the Service Default Mode with a colour bar signal and stereo sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and picture carrier at 475.25 MHz for PAL, or 61.25 MHz for NTSC (channel 3). General 3.3.
Q552.2L LA • • It makes sense to avoid exposure to electrical shock. While some sources are expected to have a possible dangerous impact, others of quite high potential are of limited current and are sometimes held in less regard. Always respect voltages. While some may not be dangerous in themselves, they can cause unexpected reactions that are best avoided. Before reaching into a powered TV set, it is best to test the high voltage insulation. It is easy to do, and is a good service precaution.
I 2C I2D I2S IF IR IRQ ITU-656 HDMI HP I FPGA FTV Gb/s G-TXT H HD HDD HDCP FDS FDW FLASH FM EMI EPG EPLD EU EXT EEPROM EDID DVB-C DVB-T DVD DVI(-d) E-DDC DTCP DRAM DRM DSP DST DFU DMR DMSD DNM DNR Directions For Use: owner's manual Digital Media Reader: card reader Digital Multi Standard Decoding Digital Natural Motion Digital Noise Reduction: noise reduction feature of the set Dynamic RAM Digital Rights Management Digital Signal Processing Dealer Service Tool: special remote control designed for
3. 2011-Apr-22 STB STBY S/PDIF SRAM SRP SSB SSC SIF SMPS SoC SOG SOPS SPI SCL SCL-F SD SDA SDA-F SDI SDRAM SECAM R-TXT SAM S/C SCART RESET ROM RSDS RC RC5 / RC6 PWB PWM QRC QTNR QVCP RAM RGB PTC PSLS PSL POR PSDL POD PIP PLL PCB PCM PDP PFC EN 8 back to div. table YUV YPbPr WXGA XTAL XGA Y Y/C WYSIWYR VSB VGA VL TS TXT TXT-DW UI uP UXGA V VESA SXGA TFT THD TMDS SVGA SVHS SW SWAN Precautions, Notes, and Abbreviation List PAL M = 3.575612 MHz and PAL N = 3.
4.2 4.1 Q552.2L LA For easy servicing of a TV set, the set should be put face down on a soft flat surface, foam buffers or other specific workshop tools. Ensure that a stable situation is created to perform measurements and alignments. When using foam bars take care that these always support the cabinet and never only the display. Caution: Failure to follow these guidelines can seriously damage the display! Ensure that ESD safe measures are taken. Service Positions back to div. table 4.3.1 4.
4. Q552.2L LA 19100_048_110216.eps 110216 1 19100_049_110216.eps 110216 Refer to Figure 4-4 for details. Mains Switch Subwoofer The central subwoofer is located in the centre of the set and is secured by two bosses. When defective, replace the whole unit. Tweeters Each tweeter unit is mounted with two screws. When defective, replace the whole unit. Speakers 2011-Apr-22 4.3.3 4.3.2 It is advised to lay the set with front facing down before executing this operation. 1.
4.3.6 Figure 4-6 SSB 1 1 2 3 3 2 19101_006_110407.eps 110407 2 2 1. Remove the stand [1]. 2. Remove the stand subframe [2]. Figure 4-8 Keyboard control, IR & LED board [2/2] 2 2 Figure 4-7 Keyboard control, IR & LED board [1/2] 19101_009_110407.eps 110407 1 1 Refer to Figure 4-7 and Figure 4-8 for details. Keyboard Control, IR & LED Board 1. Unplug all connectors [1]. 2. Remove the fixation screws [2]. 3. Take the board out.
2011-Apr-22 EN 12 4. Figure 4-10 LCD panel [2/3] 3 2 Q552.2L LA 1 19101_004_110407.eps 110407 back to div. table Figure 4-9 LCD panel [1/3] Mechanical Instructions Figure 4-11 LCD panel [3/3] 4 19101_003_110407.eps 110407 19101_005_110407.
4.4 Notes: • While re-assembling, make sure that all cables are placed and connected in their original position. • Pay special attention not to damage the EMC foams in the set. Ensure that EMC foams are mounted correctly. To re-assemble the whole set, execute all processes in reverse order. Set Re-assembly back to div. table Mechanical Instructions Q552.2L LA 4.
5. Q552.2L LA Service Modes, Error Codes, and Fault Finding • • Europe, AP DVB-T All picture settings at 50% (brightness, color, contrast). Sound volume at 25%. PAL B/G 475.25 546.00 PID DVB-T Video: 0B 06 PID PCR: 0B 06 PID Audio: 0B 07 Europe, AP(PAL/Multi) Default system Freq. (MHz) Region Table 5-1 SDM default settings Specifications Purpose • To create a pre-defined setting, to get the same measurement results as given in this manual.
Note: When the NVM is corrupted, or replaced, there is a high possibility that no picture appears because the display code is not correct. So, before initializing the NVM via the SAM, a picture is necessary and therefore the correct display option has to be entered. Refer to Chapter 6. Alignments for details. To adapt this option, it’s advised to use ComPair (the correct values for the options can be found in Chapter 6. Alignments) or a method via a standard RC (described below).
Q552.2L LA Key in the code “123654” via the standard RC transmitter. Note: Activation of the CSM is only possible if there is no (user) menu on the screen! How to Activate CSM Also when CSM is activated, the LAYER 1 error is displayed via blinking LED. Only the latest error is displayed (see also section 5.5 Error Codes). To have fast feedback from the field, a flashdump can be requested by development.
5.3 Hibernate St by back to div. table 5. EN 17 GoToProtection 2011-Apr-22 18770_250_100216.eps 100402 GoToProtection Active Protection WakeUp requested (SDM) - St by requested - tact SW pushed WakeUp requested The abbreviations “SP” and “MP” in the figures stand for: • SP: protection or error detected by the Stand-by Processor. • MP: protection or error detected by the MIPS Main Processor. Semi St by Mains on Q552.
2011-Apr-22 EN 18 No 5. No No back to div. table Stand by or Protection Release AVC system reset Feed initializing boot script disable alive mechanism Yes An EJTAG probe (e.g. WindPower ICE probe) can be connected for Linux Kernel debugging purposes. Enter protection 12V error: Layer1: 3 Layer2: 16 18770_251_100216.eps 100216 - Switch Audio-Reset high. It is low in the standby mode if the standby mode lasted longer than 10s.
No Initialize video processing IC’s Initialize source selection initialize tuner and channel decoders Initialize audio Startup screen visible 85500 starts up the display. 85500 sends out startup screen No 200Hz set? yes Startup screen cfg file present? yes Wake up reason coldboot & not semistandby? MIPS reads the wake up reason from standby μP. Enable Alive check mechanism Yes SW initialization succeeded within 20s? Semi-Standby Initialize Ambilight with Lights off. back to div.
11-Apr-22 EN 20 5. Service Modes, Error Codes, and Fault Finding Yes Yes Active Prepare Start screen Display config file and copy to Flash No Display cfg file present and up to date, according correct display option? Yes Startup screen Option and Installation setting Photoscreen ON? Switch on the Ambilight functionality according the last status settings. Restore dimming backlight feature, PWM and BOOST output and unblank the video.
No Backlight already on? (splash screen) Release audio mute and wait 100ms before any other audio handling is done (e.g. volume change) Switch Audio-Reset low and wait 5ms Yes Active Prepare Start screen Display config file and copy to Flash No Display cfg file present and up to date, according correct display option? Yes Startup screen Option and Installation setting Photoscreen ON? Switch on the Ambilight functionality according the last status settings. unblank the video. back to div.
2011-Apr-22 EN 22 5. Instruct 200Hz Tcon to turn off the display Yes Q552.2L LA back to div.
Also here, the standby state has to be maintained for at least 4s before starting another state transition. release reset audio 10 sec after entering standby to save power Important remarks: back to div.
ComPair 5.4.1 Q552.2L LA RC out TO TV PC Multi function RS232 /UART TO UART SERVICE CONNECTOR Optional power 5V DC 10000_036_090121.eps 091118 ComPair II Developed by Philips Brugge I2C TO I2C SERVICE CONNECTOR 2011-Apr-22 Note: When you encounter problems, contact your local support desk. How to Order ComPair II order codes: • ComPair II interface: 3122 785 91020. • Software is available via the Philips Service web portal. • ComPair UART interface cable for Q55x.x. (using 3.
5.5.4 5.5.3 Via the blinking LED procedure. See section 5.5.3 How to Clear the Error Buffer. Via ComPair. 53 64 PNX doesn’t boot (SW cause) 2 Display MIPS Stby μP MIPS MIPS MIPS MIPS MIPS MIPS MIPS MIPS MIPS MIPS MIPS Stby μP Stby μP MIPS MIPS Extra Info • Rebooting. When a TV is constantly rebooting due to internal problems, most of the time no errors will be logged or blinked.
Q552.2L LA Introduction 5.6.1 2011-Apr-22 Example: Error 12 8 6 0 0. After activation of the SDM, the front LED will show: 1. One long blink of 750 ms (which is an indication of the decimal digit) followed by a pause of 1.5 s When one of the blinking LED procedures is activated, the front LED will show (blink) the contents of the error buffer. Error codes greater then 10 are shown as follows: 1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit 2. A pause of 1.5 s 3.
5.8.5 5.8.4 5.8.3 5.8.2 5.8.1 5.8 The linear stabilizers are providing: • +1V2 supply voltage (1.2V nominal), stabilized close to PNX855xx device, for various other internal blocks of PNX855xx; SENSE+1V2 signal provides the needed feedback to achieve this. • +2V5 supply voltage (2.5V nominal) for LVDS interface and various other internal blocks of PNX855xx; for 5000 series SSB diversities the stabilizer is 7UD2 while for the other diversities 7UC0 is used.
Q552.2L LA No Uart logging at all: • In case there is no Uart logging coming out, check if the startup script can be send over the I2C bus (3 trials to startup) + power supplies are switched on and stable. • No startup will end up in a blinking LED status : error LAYER 1 = “2”, error LAYER 2 = “53” (startup with SDM solder paths short). • Error LAYER 2 = “15” (hardware cause) is more related to a supply issue while error LAYER 2 = “53” (software cause) refers more to boot issues.
End Final check of all menus in CSM. Special attention for HDMI Keys and Mac address. Check if E - D F U is present. Check and perform alignments in SAM according to the Service Manual. Option codes, colour temperature, etc. If not already done: Check latest software on Service website. Update main and Stand-by software via USB. Go to SAM and reload settings via “Download from USB” function.
5. Q552.2L LA 2011-Apr-22 back to div. table Figure 5-12 SSB replacement flowchart - Factory mode R estart the set After entering “display option” code, the set is going in stand-by mode (= validation of code) Program display option code via “062598 MENU”, followed by the 3 digits code of the display (this code can be found on a sticker on - or inside - the set). Unplug the mains cord to verify the correct disabling of the Factory mode.
5.9.1 5.9 Important: When the NAND-Flash must be replaced, a new SSB must be ordered, due to the presence of the security keys! (CI +, MAC address, ...). Perform the following actions after SSB replacement: 1. Set the correct option codes (see sticker inside the TV). 2. Update the TV software => see the eUM (electronic User Manual) for instructions. 3. Perform the alignments as described in chapter 6 (section 6.5 Reset of Repaired SSB). 4. Check in CSM if the CI + key, MAC address.. are valid.
Q552.2L LA UART logging 2K10 (see section “5.8 Fault Finding and Repair Tips, 5.8.7 Logging) Below the content of the One-Zip file is explained, and instructions on how and when to use it. • AmbiCpld_Q55XX_x.x.x.x_prod.zip. Contains the program instruction and software content, needed to upgrade the ambilight CPLD on the TV550 platform. • BalanceFPGA_Q555X_x.x.x.x_prod.zip. Contains the BalanceFPGA software in “upg” format. • FUS_Q555X_x.x.x.x_prod.zip. Contains the “autorun.
6.3 6.2 6.1.1 6.1 First, set the correct options: – In SAM, select “Option numbers”. – Fill in the option settings for “Group 1” and “Group 2” according to the set sticker (see also paragraph 6.4 Option Settings). – Press OK on the remote control before the cursor is moved to the left. – In submenu “Option numbers” select “Store” and press OK on the RC. OR: – In main menu, select “Store” again and press OK on the RC. – Switch the set to Stand-by. Warming up (>15 minutes).
6. Q552.2L LA Warm B t.b.d. t.b.d. t.b.d. 2 8192 4096 2048 1024 512 256 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Tuner Type Perfect Pixel Multi App 16384 Bit 14 Option Name Video Store Streaming Dec. Value Option 1 (prescribed value 327761)) Bit 15 (MSB) 32768 Option & Bit Table 6-4 Option codes at bit level (Option 1 - Option 8) From 2011 onwards, it is not longer possible to change individual option settings in SAM.
Option Name 256 128 64 32 16 8 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 AV3 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) HDMI 2 HDMI 3 HDMI Side ViewPort 21_9/PQL Seamless System Headphone Sound in Stand 3D Prepared AV1 AV2 Side IO Light Sensor Light Sensor LUT Super Resolution Smart Bit Enhancement (SBE) 3D Passive AL Select FPGA3Dact/1Ddimm Ambient Light Sunset Option 3 (
6. Dec.
6.5 1 Dec.
6. Q552.2L LA Alignments A. SW version Hardware Info e.g. “Q5551_0.9.1.0 Sub-menu 2 Off/On None E-sticker Auto store mode Hardware events Display Software maintenance Clear Display Test application crash Test cold reboot Test reboot Display information is for development purposes Display information is for development purposes In case the display must be swapped for repair, you can reset the “”Display operation hours” to “0”.
NVM editor Download from USB Upload to USB Development file versions see type plate see type plate AG code back to div. table Temp com file version none Flash units software NVM version Q55x1_0.4.5.0 Initial main software 12NC one zip software Ambilight parameters PRFAM 5.0.5.2 PQU - User styles PQF - Fixed settings PQS- Profile set PQ - TV550 1.0.27.22 Acoustics parameters ACSTS 5.0.6.20 Display parameters DISPT5.0.9.
7. Q552.2L LA 7.1.2 7.1.1 removal of TCON from the SSB (comes with the display) changed power architecture new USB hub (where applicable). back to div. table 19110_053_110421.eps 110421 For details about the chassis block diagrams refer to chapter 9. Block Diagrams. An overview of the TV550 2011 architecture can be found in Figure 7-1.
7.1.3 SSB Cell Layout back to div. table Figure 7-2 SSB layout cells (top view) Circuit Descriptions Q552.2L LA EN 41 2011-Apr-22 19110_052_110421.eps 110421 7.
- 2 3 - 12 13 14 15 GND1 n.c. pin 11 n.c. pin 13 n.c. A1 n.c. OCD n.c. pin 3 n.c. pin 5 n.c. A2 CN2 to display 1316 - 10 11 12 13 14 15 - 5 - - 4 9 - 3 8 L 2 - N 1 - CN1 Pin 7 Mains Descr. 6 1308 no. - Anode_L n.c. L5 Cathode L4 Cathode L3 Cathode L2 Cathode L1 Cathode R1 Cathode R2 Cathode R3 Cathode R4 Cathode R5 Cathode n.c.
+ 1V 1 + 1V 8 + 3V 3 5100 m A 2450 m A 2371 m A + 1V 8 + 3V 3 + 5V 5-TUN + 1V 2 + 2V 5 + 5V -TUN Hybrid Tuner with integrated SAW filter and amplifier External ISDB-T channel decoder covering the Brazilian digital terrestrial TV standard Bandpass filter Amplifier PNX85500 SoC TV with integrated analogue demodulator.
• • • TS input AUDIO DEMOD AND DECODE AUDIO IN HDMI RECEIVER SSIF, LR SPDIF HDMI I2C IR ADC SPI 560 MHz MIPS32 24KEf CPU MPEG/H.264 VIDEO DECODER 3D COMB MPEG SYSTEM PROCESSOR UART I2C MEMORY CONTROLLER back to div. table AUDIO OUT AUDIO DACS VIDEO ENCODER LVDS GPIO Flash USB 2.
TT #1 Serial Interface Engine Regulator Port #1 OC Sense Switch Driver/ LED Drivers ... Port Controller OC Sense Switch Driver/ LED Drivers Port #x TT #x Controller Serial Interface SDA SCL To EEPROM or SMBus Master USB Data OC Port Downstream Sense Power Switch/ LED Drivers PHY#x ...
8. Q552.2L LA IC Data Sheets A1 A0 A1 A2 6 5 3 4 OS GND back to div. table Figure 8-2 Pin configuration A0 7 2 SCL OS 18770_300_100217.
8.3 AUDIO IN HDMI RECEIVER SPDIF HDMI A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF ball A1 index area PWM Px_x ADC SPI I2C AUDIO OUT AUDIO DACS VIDEO ENCODER LVDS GPIO Flash USB 2.
8. Q552.2L LA 1 F 1 F 1 F GAIN1 GAIN0 VCLAMP PVCCR PVCCL BSL LOUT PGNDL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 PWP (TSSOP) PACKAGE (TOP VIEW) MUTE SD AVCC AGND BYPASS ROUT RIN PGNDR BSR LIN back to div. table 22 H PGNDL PGNDL LOUT BSL AVCC AVCC GAIN0 GAIN1 BSR ROUT PGNDR PGNDR 1 F 0.22 F 22 H 0.68 F 0.68 F 0.
8.5 DRVL2 LL2 DRVH2 17 16 15 9 10 11 12 13 14 NC VFB2 VO2 EN2 NC VBST2 18 19 20 21 PGND2 TRIP2 TEST2 V5FILT VREG5 8 22 7 GND TEST1 TRIP1 VIN 23 6 24 NC PGND1 25 5 LL1 DRVL1 26 4 3 EN1 DRVH1 27 28 VO1 2 NC VFB1 1 VBST1 Q552.2L LA back to div. table Figure 8-5 Internal block diagram and pin configuration Pinning information Block diagram Diagram DC/DC B03B, TPS53126PW (IC7U03) IC Data Sheets TPS53124 EN 49 2011-Apr-22 18310_300_090319.eps 100416 8.
8. Q552.2L LA IC Data Sheets PowerSO-8 back to div. table Figure 8-6 Internal block diagram and pin configuration DFN8 (4 × 4) Pinning information Block diagram Diagram DC/DC B03E, ST1S10PH (IC 7UD0) 2011-Apr-22 8.6 EN 50 I_18010_083.
8.7 DPAK LD1117DT Q552.2L LA back to div. table Figure 8-7 Internal block diagram and pin configuration Pinning information Block diagram Diagram DC/DC B03E, LD1117DT25 (IC 7UD2) IC Data Sheets 8. 2011-Apr-22 F_15710_166.
Q552.2L LA IC Data Sheets 2011-Apr-22 SMI 10M Rx Logic 2 3 4 5 6 7 8 LED1/REGOFF XTAL2 XTAL1/CLKIN VDDCR RXCLK/PHYAD1 RXD3/PHYAD2 Squelch & Filters 100M PLL Analog-toDigital 100M Transmitter VSS SMSC LAN8710/LAN8710i 32 PIN QFN (Top View) TXD2 TXD1 TXD0 TXEN TXCLK nRST nINT/TXER/TXD4 MDC 23 22 21 20 19 18 17 back to div. table PHYAD[0:2] PHY Address Latches 18770_302_100217.
8.9 Q552.2L LA back to div. table Figure 8-9 Internal block diagram and pin configuration Pinning information Block diagram Diagram HDMI B04D, SII9x87B (IC 7EC1) IC Data Sheets EN 53 2011-Apr-22 18770_303_100217.eps 100217 8.
8. Q552.2L LA IC Data Sheets 2011-Apr-22 BYPASS IN 2− SHUTDOWN 3 6 5 VDD/2 − + − + Bias Control 8 7 6 5 1 2 3 4 VDD VO2 IN2− SHUTDOWN 4 VO2 7 VO1 1 VDD 8 back to div. table Figure 8-10 Internal block diagram and pin configuration VO1 IN1− BYPASS GND D OR DGN PACKAGE (TOP VIEW) IN 1− 2 Pinning information Block diagram 8.10 Diagram Headphone B04E, TPA6111A2DGN (IC 7EE1) EN 54 18770_309_100217.
(5216) 18P *AMBILIGHT MODULE 1M86 (1162) AL (1005) 1M95 (PSU) 1. +3V3STDBY 2. STANDBY 3. GND 4. GND 5. +12V 6. +12V 7. +VSND 8. GND_SND 9. BL-ON-OFF 10. BL-DIM1 11. BL-I-CTRL 12. POK 13. +24V 14. GND1 1316 (PSU) 1. ANODE 1 2. NC 3. CATHODE 1 4. GND 5. ANODE 2 6. NC 7. CATHODE 2 8. NC 9. ANODE 3 10. NC 11. CATHODE 3 12. NC 13. ANODE 4 14. NC 15. CATHODE 4 1. N 2.
1308 (PSU) LEADING EDGE LCD DISPLAY (1004) J1 C1 41P TO DISPLAY 14P 1M95 (B03C) 8G50 1D38 (B03A) ETHER NET 1M99 1308 2P B HDMI HDMI HDMI 3139 123 6521.x (1150) SSB 14P 1M95 VGA 1M95 (PSU) 1. +3V3STDBY 2. STANDBY 3. GND 4. GND 5. +12V 6. +12V 7. +VSND 8. GND_SND 9. BL-ON-OFF 10. BL-DIM1 11. BL-I-CTRL 12. POK 13. +24V 14. GND1 1316 (PSU) 1. ANODE 1 2. NC 3. CATHODE 1 4. GND 5. ANODE 2 6. NC 7. CATHODE 2 8. NC 9. ANODE 3 10. NC 11. CATHODE 3 12. NC 13. ANODE 4 14. NC 15.
B01H HDMI 1 2 HDMI SIDE CONNECTOR 19 18 HDMI 3 CONNECTOR 1 2 19 18 HDMI 2 CONNECTOR HDMI 1 CONNECTOR 23 RXD 22 DRX1DRX0+ 20 DRXC- 12 69 RXA 68 ARX2ARX1+ ARX1ARX0+ 3 BRXC- 17 16 15 14 CRX2CRX1+ CRX1CRX0+ +3V3-HDMI 12 CRXC- 12 9,27,64 11 13 CRX0- CRXC+ 9 10 4 6 7 3 18 CRX2+ 1 1P02 2 BRXC+ 12 1 3 BRX0- 9 10 VCC33 RXC 5 RXB 4 BRX1BRX0+ 4 6 7 7 6 BRX2BRX1+ 3 8 BRX2+ 1 1P03 ARXC- OPTIONAL 66 ARXC+ 12 65 67 ARX0- 9 10 4 6 7 71 70 ARX2+ 1 72 19
HDMI SIDE CONNECTOR 23 RXD 22 DRX1DRX0+ 20 DRXC- 12 HDMI 2 CONNECTOR HDMI 1 CONNECTOR 5 RXB 4 BRX1BRX0+ BRXC- 12 15 RXC 14 CRX1CRX0+ CRXC- 12 14 12 11 13 CRX0- CRXC+ 9 10 2F79 2F75 3F81 3F80 IF+ IF- IF AGC 2 4 DIGITAL AUDIO OUT VGA AUDIO AUDIO IN L+R eHDMI+ 1E07 1E10 1E09 1E08 1 2 1 3 4 6 +3V3 1 3 2 TS-FE-DATA TS-FE-VALID TS-FE-SOP TS-FE-CLOCK AUDIO-IN1-R AUDIO-IN1-L PNX-IF-N PNX-IF-P RESET-SYSTEMn B02E 8 +3V3 +3V3 HDMIA-RX2- HDMIA-RX2+ HDMIA-RX1-
SD-CARD ETHERNET + SERVICE B04C B04D 5 6 7 8 6 2 5 8 3 6 29 IF- +5V HDMI 4x HDMI CONNECTOR LED-1 LED-2 ARX-HOTPLUG 1P02-19 BRX-HOTPLUG 1P03-19 CRX-HOTPLUG 1P04-19 DRX-HOTPLUG 1P05-19 TO PIN: 1P02-13 1P03-13 PCEC-HDMI 1P04-13 1P05-13 B03H B03C B02E 45 41 31 35 18 19 7 4 3 5 HDMI SWITCH 7EC1 SII9187BCNU SII9287BCNU 7U43 9 7 19 +3V3 3S0W HDMIA-RX CEC-HDMI W24 AF19 AB22 AC20 AA22 AD23 AD26 AD19 AC25 AE26 LCD-PWR-ONn 7EC0 EF B02A VIDEO STREAM B02A FLASH RREF RX
8 FLASH XIO-D(00-07) ETHERNET 7E10 LAN8710A-EZK AA1 AA4 AB1 AB2 AA2 ETH-TXD(2) ETH-TXD(3) ETH-TXCLK 20 AA3 ETH-TXD(0) ETH-TXD(1) 7 22 23 24 25 AC1 Y5 Y6 AB4 ETH-RXD(3) ETH-RXCLK ETH-RXD(2) ETH-RXD(0) ETH-RXD(1) B02G A DQ TXCLK TXD_2 TXD_3 TXD_0 TXD_1 RXD_2 RXD_3 RXCLK RXD_0 RXD_1 ERR 15 GPIO_3 GPIO_2 2_SCL 2_SDA 4_SCL 4_SDA ANALOGUE VIDEO VGA_EDID_SCL VGA_EDID_SDA B02I GPIO_3 GPIO_2 HDMI_DV DDC_A_SCL DDC_A_SDA P3_1 P3_0 MC_SCL MC_SDA 1_SCL 1_SDA B02C ERR 53
8 9 8 9 6 7 8 6 7 8 GND1 +24V B03e B03d B03e B03c B03e B03e B03e B03e B03e B03e B03e +3V3 B01G +5V-TUN B01F +5V T 3.
B01A Common Interface Common Interface 10-1 B01 393912365213 10.
B01B Flash Flash NAND-RDY1n XIO-OEn XIO-WEn NAND-WPn NAND-CLE NAND-ALE NAND-CE1n XIO-D00 XIO-D01 XIO-D02 XIO-D03 XIO-D04 XIO-D05 XIO-D06 XIO-D07 +3V3 +3V3 3F22-4 3F23 4 100R 3F20-2 100R 3F20-4 100R 3F21-2 100R 3F21-4 4 2 4 2 2K2 3F24 100R 3F22-3 3 10K 3F22-1 1 5 100R 6 3F21-3 3 7 8 3F21-1 1 2 6 3F20-3 3 3F22-2 8 3F20-1 1 10. 3F19 8 6 5 7 5 7 2F20 IF23 IF21 2011-Feb-18 back to div.
SCENARIO 1x USB 1x USB + WIFI 2x USB 2x USB + WIFI USB-OVR1 USB2-DM USB2-DP RESET-USBn USB1-DM USB1-DP USB-DM USB-DP USB2-DM USB2-DP USB-WIFI-DDn USB-WIFI-DDp 1P07 N N Y Y +3V3 +5V +3V3 1 3 100K 3FLE-2 100K 3FLE-1 7 8 6 1F24 N Y N Y 10K 3FLF 100K 3FLE-3 1P08 Y Y Y Y 3 100K 4 3FLE-4 5 2 1 10K 3FLD 24M 1FL5 12p 3FLG N Y Y N +3V3 +3V3 9FLF 9FLG 3FL2 N N Y Y 3FL4 N N Y Y 3FL7 N Y N Y 10K 3FLH 10K 3FLG 9FLK 9FLL 9FLC 9FLD 9F26 9F25 3F32 Y Y Y Y 9FLH 9FLJ 3F34 N Y
B01D SD Card SD-Card +3V3 47K 3F41-4 3 5 2 47K 3 3F42-3 6 47K 6 10K 3F45 RES 47K 3F41-3 IF47 47K 3F42-2 47K 7 1 3F41-1 8 1 3F42-1 8 47K 2 3F41-2 7 4 Circuit Diagrams and PWB Layouts 2F40 SDIO-WP SDIO-CDn SDIO-DAT2 SDIO-DAT1 SDIO-DAT0 SDIO-CLK SDIO-CMD SDIO-DAT3 +3V3 0R3 3F40 SDIO-WP SDIO-CDn SDIO-DAT2 SDIO-DAT1 SDIO-DAT0 SDIO-CLK SDIO-CMD SDIO-DAT3 +T Q552.2L LA 22u 16V FF45 10. 100R 3F44-1 100R 3F44-2 8 7 100R 6 div.
+3V3 2F49 IF59 3F58 PNX-SPI-SDI IF51 1 2 3 0 1 2 7F58 2 W S C D VSS HOLD 512K FLASH Φ VCC IF58 MAIN NVM Q 100n RES 2F52 +3V3-STANDBY ADR SCL WC FF57 SDA Φ (8K × 8) EEPROM 100n 2F58 RES 7 3 1 6 5 IF54 IF53 IF52 IF50 5 6 7 100R 3F59 +3V3-STANDBY 7F52 M25P05-AVMN6 +3V3-STANDBY FF04 FF29 RXD-UP RESET-STBYn SPI-PROG TXD-UP FF63 FF61 100R 3F65 100R 100R div.
1T01 2F61 2F62 9F02 9F03 9F04 9F05 9F06 2F73 2F82 2F72 2F80 2F77 5F71 5F74 Item No.
Toshiba supply +3V3 2FA2 B01G 100n Toshiba Supply 3 IN FFA2 COM OUT 7FA3 LD1117DT12 1 2 +1V2-BRA-DR1 div. table 2011-Feb-18 back to FFAF +1V2-BRA-VDDC EN 68 5FA3 2FA3 10. 30R 100n Q552.2L LA 5FA4 2FA4 Circuit Diagrams and PWB Layouts 30R 10u SPB SSB TV550 2K11 4DDR BR SD 2010-12-23 2011-03-09 19110_016_110415.
B01H HDMI HDMI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FFB5 21 23 1P05 20 22 FFB6 FFB3 FFB4 FFB1 FFB2 DIN-5V HDMI CONNECTOR SIDE Q552.2L LA DRX0DRXC+ DRX1DRX0+ DRX2DRX1+ DRX2+ EN 69 div. table DRX-DDC-SCL DRX-DDC-SDA 2011-Feb-18 back to DRX-HOTPLUG DRX-DDC-SCL DRX-DDC-SDA DRXCPCEC-HDMI 10. DIN-5V 1 3FBF-1 8 Circuit Diagrams and PWB Layouts 47K 2 3FBF-2 7 47K DIN-5V SPB SSB TV550 2K11 4DDR BR SD 2010-12-23 2011-03-09 19110_017_110415.
B01I VGA VGA 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1216-02D-15L-2EC VGA CONNECTOR 1E05 FFC6 FFC4 10K RES 3FC2 10K RES 3FC1 Q552.2L LA FFC9 FFC8 FFC7 FFC5 FFC3 FFC2 FFC1 10. EN 70 div.
Temp sensor & headphone AMP2 AMP1 SCL-SSB SDA-SSB 100R 3FD4 RES 3FD1 RES 100R 3FD3 6FD1 1K0 IFD4 IFD2 LTST-C190KGKT 2 1 3 SCL SDA OS 7FD1 LM75BDP A2 A1 A0 EN 71 2FD1 5 6 7 IFD1 IFD3 div. table 2011-Feb-18 back to 1K0 B01J 8 +VS GND 4 IFD5 1K0 RES Temp sensor & headphone 3FDG-2 7 2 100n 8 1K0 3FDG-1 1 1K0 9FD1 RES 3FD6 1FD2 3FD2 9FD5 CDS4C12GTA 12V 1FD3 9FD2 RES 1K0 3FD7 6FD2 RES 6FD3 +3V3 RES 10. CDS4C12GTA 12V 2FDC Q552.
SCL-SSB SDA-SSB IF+ IF- 2FG2 AGND 18p 3 25M4 AGND 4 2 1 1FE0 2FG3 18p AGND AGND AGND AGND AGND 3FE8 3FE6 10n 2FG6 100R 3FE9 3FE7 10K 2FH7 100n 2FH6 100n 2FG8 +3V3-BRA-FLT 2FG9 2FG7 2FG4 30R 5FE5 30R AGND 1u0 1u0 1u0 5FE3 BFE3 BFE2 IF49 100R 10K IF29 100n 100n 100n 10n IF17 IF18 45 46 11 7 1 41 8 40 39 26 24 25 28 27 30 29 3 2 18 19 7FE0 TC90517FG X SCL SDA CKI AGCI 0 TSMD 1 S_INFO DTMB DTCLK AGND AD_VREF P AD_VREF N P ADQ_AI N P ADI
B02A CA-RDY J24 J23 L26 L24 J21 L23 CA-MOVAL N25 N24 L25 N23 K26 K25 J22 P21 P22 P23 P24 P25 P26 N21 N22 7S00-11 PNX85500 CA-MOSTRT IS25 MCLK VPPEN VCCEN RST RDY OOB_EN MOVAL MOSTRT MIVAL MISTRT O I DATA_EN DATA_DIR ADD_EN D25 D26 C24 D23 C23 B23 A22 E22 F24 F25 F26 E23 E24 E25 E26 D24 K21 1 K22 2 K23 1 K24 2 N26 M21 M22 M23 M24 M25 M26 L21 T21 DATA T23 ERR T22 TNR_SER1 MICLK R23 MIVAL R22 SOP CA CD VS 0 1 2 3 MDO 4 5 6 7 E21 CE1_ D21 CE2_ A20 NAND RDY2 F21 RDY1 A
DDR2-VREF-CTRL3 FS02 180R 1% 180R 1% 3S20 3S22 DDR2-VREF-CTRL2 PNX85500: SDRAM FS01 +1V8 3S06 3S07 B02B 180R 1% 180R 1% D1 D5 R3 T5 F3 C2 F2 C3 B4 F1 C1 E1 F4 B2 E5 C5 A4 G5 B3 F5 U3 P2 U2 P3 N1 U1 P1 T1 V4 R5 U5 P5 N3 V3 R4 V5 DDR2-DQM0 DDR2-DQM1 DDR2-DQM2 DDR2-DQM3 DDR2-D0 DDR2-D1 DDR2-D3 DDR2-D2 DDR2-D6 DDR2-D5 DDR2-D4 DDR2-D7 DDR2-D8 DDR2-D9 DDR2-D10 DDR2-D11 DDR2-D12 DDR2-D13 DDR2-D14 DDR2-D15 DDR2-D16 DDR2-D17 DDR2-D19 DDR2-D18 DDR2-D22 DDR2-D23 DDR2-D20 DDR2-D21 DDR2-D24 DDR2-D30 DDR2-D
B02C PNX85500: Digital video in Digital video in +3V3 HDMIA-RXC+ HDMIA-RXC- HDMIA-RX0+ HDMIA-RX0- HDMIA-RX1+ HDMIA-RX1- HDMIA-RX2+ HDMIA-RX2- Circuit Diagrams and PWB Layouts 12K 3S0W Q552.2L LA RES 2S2E 10u IS01 10. HDMI_DV P RX0_A N div.
AUDIO-IN4-R AUDIO-IN4-L AUDIO-IN3-R AUDIO-IN3-L AUDIO-IN1-R 1 2 3 4 22K 3S13-2 22K 3S13-1 22K 3S13-3 22K 5 7 7 8 6 3S13-4 22K 2 3S12-2 22K 8 IS1Q IS1P IS0R IS1J IS1H 10K 6 3S17-2 1 2 7 10K 8 10K 3S17-1 6 10K 5 10K 3S17-4 3 3S17-3 4 3S16-4 5 4 10K 3S16-3 3 7 10K 1 3S16-1 8 10K 2 3S16-2 2S3F 3S12-1 10u 2S3E IS19 IS0V IS1B SPDIF-OUT-PNX 56R 3S3F 2S2L 1u0 IS1A 1u0 2S32 1u0 2S33 1u0 2S30 1u0 2S31 1u0 2S2Y 1u0 2S2Z 1u0 2S2V 1u0 2S2W AE5
+3V3 +3V3 +3V3 +3V3 +3V3 +3V3 +3V3 +3V3 +3V3 10K 3S84 10K 3S83 10K 3S64 10K 10K 3S62 RES 3S21 3S80 3S81 10K 10K 3S82 3S40 10K 3S45 10K 10K 3D-LR BOOST-PWM DS52 BOOTMODE GPIO6 FS64 TXD1-MIPS RXD1-MIPS SELECT-SAW PNX-SPI-CS-BLn IS04 FS10 TXD2-MIPS FS11 RXD2-MIPS IS05 USB-DM USB-DP PNX-SPI-CS-BLn BOOST-PWM SELECT-SAW GPIO6 BOOTMODE 3D-LR RXD1-MIPS TXD1-MIPS RXD2-MIPS TXD2-MIPS IS17 9S09 GPIO_0 GPIO_1 GPIO_2 GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7 GPIO_10 GPIO_11 B25 SDA A2
B02F 9S90 9S91 PX2EPX2E+ PX2DPX2D+ PX2CPX2C+ A16 B16 N C P A18 B18 N D P C19 B19 N E P B A div. table E D C CLK 2011-Feb-18 back to LOUT2 LOUT4 C15 N B15 B P PX2BPX2B+ C17 N B17 CLK P A14 N B14 A P PX2APX2A+ 9S92 9S93 C12 N B12 E P PX1EPX1E+ PX2CLKPX2CLK+ D A11 N B11 D P PX1DPX1D+ E C CLK B A N C P LOUT1 LOUT3 LVDS A9 B9 C10 N B10 CLK P N B P N A P EN 78 PX1CPX1C+ PX1CLKPX1CLK+ C8 B8 PX1BPX1B+ 7S00-7 PNX85500 10. A7 B7 Q552.
+3V3-STANDBY +3V3-STANDBY +3V3-STANDBY 10K RES 3S1K 3S1H 10K 3S3T RES 3S3S 3S3P 3S3M 3S1E 10K 3S1C 10K 10K 10K 10K 3S3L RES 10K RES 3S1F 10K 3S1L 100K RES 3S1J 10K RES 3S2A 3S1G 10K 3S1B 10K RES 10K 3S3N RES 10K 3S3Q RES 10K 3S3R 10K RES 10K 3S1D 27K 100n 2S4E SPI-PROG KEYBOARD RESET-SYSTEMn DETECT2 RXD-UP TXD-UP LCD-PWR-ONn EJTAG-DETECTn LAMP-ON STANDBY FAN-CTRL1 FAN-CTRL2 POWER-OK ENABLE-3V3n RC TACHO CEC-HDMI BACKLIGHT-PWM-ANA-DISP SDM 2S4D 1n0 SPI-PROG PNX-SPI-WPn
A1 A10 A12 A15 A17 A19 A26 A3 A8 B1 B20 C20 C4 D2 D20 E13 E20 E4 F10 F12 F14 F16 F18 F20 F8 G10 G12 7S00-12 PNX85500 VSS +1V1 100n VSS VSS VSSA AA16 AA8 Y11 Y14 Y16 Y9 2S43 SENSE+1V1 PNX85500: Power VSS M7 N2 N20 P10 P12 P14 P16 P18 P4 P6 P7 T10 T12 T14 T16 T18 T2 T6 T7 U4 V10 V12 V14 V16 V18 V2 Y20 100n 100n B02H 2S27 Power 2S28 G14 G16 G18 G2 G20 G8 H4 H6 H7 J20 K10 K12 K14 K16 K18 K2 K6 K7 L20 L4 M10 M12 M14 M16 M18 M6 8 2S5G-1 1 8 2S5K-1 1 7 100n 2S5G-2 2 7 100n 2S5K-2 2
AP: VGA EU: VGA +CVBS SCART2 YPBPR2 EU: YPBPR1 YPBPR1 - AP: AP: EU: AP: EU: SCART1 Connectivity RES 8 VGA-SDA-EDID VGA-SCL-EDID RES 1 3 100R 100R 100R 3S5V-1 3S5V-3 8 6 V-SYNC-VGA 100R 3 3S5T-3 6 3S5T-1 1 H-SYNC-VGA B-VGA G-VGA R-VGA AV4-PB AV4-PR AV4-Y AV2-CVBS AV3-PB AV3-PR AV3-Y YPBPR1-SYNCIN1 AV1-G AV1-B AV1-R 47R 56R 56R 56R * 3S59 22n 2S7K 2S7J 2S7U 2S7R 2S8G 22n 2S86 22n 2S85 22n 2S84 22n 2S7E 22n 22n 22n 22n 2S7P 22n 2S7N 22n 10n
FD03 FD08 FD01 RIGHT-SPEAKER LEFT-SPEAKER A-STBY AUDIO-MUTE-UP +AUDIO-L A-PLOP -AUDIO-R 6 ID14 2 6 4K7 3 GND-AUDIO ID34 3 ID15 3D02-3 4K7 7 3D02-2 2 7D11-2 BC847BS(COL) 4 GND-AUDIO 7D11-1 BC847BS(COL) 1 1u0 2D29 1u0 2D28 +24V-AUDIO-POWER +3V3-STANDBY GND-AUDIO 7D15-2 BC847BS(COL) 4 3 7D15-1 BC847BS(COL) 1 6 47K 3D01-4 5 4 3 100K 3D06-4 100K 5 6 100K 2 10u 2D02 100K 8 3D06-1 1 7 3D06-2 DETECT2 3D06-3 FD07 GND-AUDIO 4 5 47n 2D23 47n 5 10.
+3V3-STANDBY IU03 3U01 10K 3U00 RES ENABLE-1V8 100n 2U06 1 2 3 +1V8 7U00 BC847BW 10u 2U00 2U03 330R 1% 3U08 +1V1 GND-SIG IU24 12K 1K0 1% 3U03 +1V1 +1V8 3U22 GND-SIG 22K GND-SIG 3U02 1n0 RES 10K IU04 IU02 IU01 GND-SIG IU06 20 21 16 5 8 4 9 3 10 2 11 VIN GND-SIG 1 2 1 2 1 2 SW PGND TEST GND 1 2 DRVH V5FILT VREG5 1 2 100n 2U02 DRVL GND-SIG 1 TRIP 2 1 VFB 2 1 VO 2 1 EN 2 1 VBST 2 22K 2U01 3U09 7U03 TPS53126PW 3U10 IU05 GND-SIG 18 19 7 17
+12VIN 1-2041145-4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1M95 *** 1-2041145-3 1 2 3 4 5 6 7 8 9 10 11 12 13 1M99 * FU77 GND_AL GND_AL GND_AL FU76 FU62 FU67 FU58 FU59 FU60 FU61 FU63 FU75 RES 2U57 4U01 4U00 ** ** 2U58 * +12VD GND_AL +24V 10n 1u0 2U47 2U68 +12VIN FU50 FU49 FU48 +12V_AL optionally 1M99 is a 9 pin connector 1n0 100n 2U56 ** 100p 3U64 FU52 FU51 1K0 FU55 FU53 FU66 +3V3-STANDBY GND-AUDIO RES 2U48 1n0 +3V3 LED-1 100R RES 3U84 100R 100R 100R 3U43 I
3 RES 7U06-2 BC847BS(COL) 4 +2V5-REF 3U25-4 5 470R 3UB6-4 4 5 1K0 3UB7-4 5 4 3U25-3 6 5 100K RES 3 100K RES 4 +12V 3 IU29 6 7UA7-2 4 BC847BS(COL) 5 3UB6-3 6 1K0 IUB2 3UB6-2 6 2 7 1K0 3UB6-1 1 8 1K0 IUB5 3 1 3 2 RES 7U06-1 BC847BS(COL) 1 2UB8 +5V5-TUN 3UA0 K A 2K2 R 22u 7UA0 TS2431 2 IUB6 IUB4 3U25-2 IU30 3U25-1 IU26 +3V3 +3V3 ENABLE-1V8 7UA7-1 BC847BS(COL) 3U13 2 7UA6 BC817-25W 3U12 IUB3 3UB7-2 7 2 470R 3UB7-3 6 3 3UB7-1470R 1 8 330R 1% 330R 1% +2V5-REF 470R
* 30R 0402 Jumper 5UD3 IUD1 2UD2 2UE0 * * +12V * 10u 10u 2UD1 2UD9 10u 10u 2UD0 2UD8 IUD0 * ENABLE-3V3-5V +5V ENABLE-3V3-5V 2UD3 30R 0402 Jumper 10u 10u A SYNC INH 11 A SYNC INH S1D 6UD1 10 7UD1-2 ST1S10PH 5 2 7UD1-1 ST1S10PH 10 7UD0-2 ST1S10PH 5 2 7UD0-1 ST1S10PH 4 5UD0 11 13 +12V SW VIA SW VIA IUD5 IUD4 IUD3 COM OUT IN COM 2 2 3u6 5UD2 3u6 5UD1 div.
B03F Temperature sensor & AmbiLight Temperature sensor & AmbiLight Circuit Diagrams and PWB Layouts +3V3 Q552.2L LA 30R 5UM1 IUM0 10. T 1.0A 63V 1UM0 div. table 2011-Feb-18 back to EN 87 FUM0 V-AMBI SPB SSB TV550 2K11 4DDR BR SD 2010-12-23 2011-03-09 19110_035_110415.
TACHO TACH02 TACH01 FAN-DRV FAN-CTRL2 3US3 +3V3 10K 10K FAN-CTRL1 1K0 3US7 +12V IUT2 IUT1 RES 3US2 +12V 3US4-2 +3V3 10K 10K +12V 6 7 4 5 IUS5 10 11 8 9 10K Fan control 1 3US4-1 8 B03G +12V 12 3 +12V 12 3 +12V +12V 2011-Feb-18 back to +3V3 10K IUS4 3US5-4 5 4 10K IUS3 3US5-1 8 1 div.
B03H 5 47K RES 3UU0-4 +12VD LCD-PWR-ONn +3V3-STANDBY Vdisp switch 4 2 IUU0 RES 7UU2-1 PUMD12 1 6 5 RES 7UU2-2 PUMD12 3 4 47K 1 1u0 1 9UU0-1 RES 2 9UU0-2 RES 3 9UU0-3 RES 4 9UU0-4 RES 1 9UU1-1 RES 2 9UU1-2 RES 3 9UU1-3 RES 4 9UU1-4 RES 5 6 7 8 5 6 7 8 IUU2 RES 7UU1 SI3441BDV div. table VDISP-SWITCH 2011-Feb-18 back to 47R IUU1 RES 3UU0-1 8 1 RES 3UU1 3UU3-1 47K RES RES 2UU1 8 RES 7UU0 SI4835DDY EN 89 47K Vdisp switch 10. 2 RES 3UU0-2 7 Q552.
AV1-R YPBPR1-PR AV1-G YPBPR1-SYNCIN1 AV1-B YPBPR1-PB AUDIO-IN1-L AUDIO-IN1-R IE55 FE86 IE53 1u8 5E76 1u8 5E74 1u8 5E73 BEC3 RES 18R EU 3E78 18R BEC5 3E79 RES 18R 3E77 EU 3E76 18R RES 18R 3E75 EU 3E74 18R Analogue externals A IE22 FE23 2E06 B04A 100p 100p 2E04 Analogue externals A 4 1 8 1K0 5 3E07-4 1K0 3E07-1 Circuit Diagrams and PWB Layouts RES 6E03 10-4 B04 393912365213 2E79 2E83 2E85 150p 150p 150p 2E80 2E84 2E86 150p 150p 150p CDS4C12GTA 12V F
RES GND_A YELLOW 1 GND_A 1 2 FE42 GND_A 1 1E08-3 4 GND MT 7 6 5 4 VIN 3 1 1E10 3150-831-030-H1 2 VCC FE44 FE01 +3V3 VGA ( OR DVI ) AUDIO GND_A 1E09 MSJ-035-69A-B-RF-PBT-BRF 2 3 1 ** FE43 GND_A RED 5 1E08-2 3 * MSP-8033SH-05-NI-FE-RF-PBT-BRF RES WHITE 4E24 RES ** 4E23 * MSP-8033SH-05-NI-FE-RF-PBT-BRF 6 YPBPR AUDIO RES ** 4E22 MTJ-032-21B-42 NI FE 2 1E04 RES ** 4E21 1E03 MTJ-032-21B-45 NI FE (PBT) ** 4E20 1E08-1 * MSP-8033SH-05-NI-FE-RF-PBT-BRF 2 YPBPR FE51 FE54
FE28 FE29 FE31 ETH-TXN ETH-RXP ETH-RXN ETH-REGOFF ETH-INTSEL FE27 ETH-TXP ETH-MDC ETH-MDIO ETH-TXER ETH-TXD(3) ETH-TXD(0) ETH-TXD(1) ETH-TXD(2) ETH-TXEN ETH-COL 3E51 3E70 RES RES 27n ETH-RXD(0) ETH-RXD(1) ETH-RXD(2) ETH-RXD(3) RESET-ETHERNETn 1K5 3E69 RES 10K IE26 15p +3V3 +3V3-ET-ANA 10K 25M 10p IE32 1 4 1 1E88 3 ACM2012 2 4 34 35 36 CR VIA MDC MDIO 0 1 2 TXD 3 4 INT TXER TXEN COL CRS_DV MODE2 0 MODE 1 RMIISEL PHYAD2 RXD<0:3> RST VSS VIA P N TX RXDV TXCLK
FECP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 21 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FECG 21 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 FEC6 21 23 20 22 20 22 20 22 +5V AIN-5V BIN-5V FECM FECN FECK FECL FECJ 100R 3ECD 100K 3ECF IEC4 IE11 +5V-EDID FECZ 3ECG BAT54 6EC1 3ECE IEC7 9EC0 IEC6 1u0 2ECU AIN-5V BIN-5V AIN-5V CIN-5V BIN-5V CIN-5V +5V-VGA CEC-HDMI +3V3-STANDBY CRX-DDC-SCL CRX-DDC-SDA BRX-DDC-SCL BRX-DDC-SDA ARX-DDC-SCL ARX-DDC-SDA
A-PLOP ADAC(4) ADAC(3) Headphone IEE2 IEE0 1u0 2EE3 1u0 2EE4 IEE1 8 10K 3EE0-1 1 10K 4 10K 3 3EE0-3 6 5 3EE0-4 IEE4 IEE3 1u0 2EE2 RESET-AUDIO 22K B04E IEE6 IEE5 4 1 2 3 5 6 2 VDD IN- 2 1 10 11 7 1 div. table 100n 2011-Feb-18 back to VIA GND GND_HS BYPASS VO AMPLIFIER Φ SHUTDOWN 2 1 5 8 7EE0-1 PUMD12 1 6 EN 94 47p +3V3 22K 2EE5 3EE1-4 22K 47p 3EE1-1 2EE0 10. 7EE1 TPA6111A2DGN FEE0 Q552.
DDR2-VREF-DDR FB00 +1V8 240R 3B28 240R 3B27 240R 3B22 DDR2-CLK_N DDR2-CLK_P DDR2-CLK_N DDR2-CLK_P DDR2-CLK_N DDR2-CLK_P AT T-POINT DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM2 DDR2-ODT DDR2-BA2 DDR2-BA0 DDR2-BA1 DDR2-A0 DDR2-A1 DDR2-A2 DDR2-A3 DDR2-A4 DDR2-A5 DDR2-A6 DDR2-A7 DDR2-A8 DDR2-A9 DDR2-A10 DDR2-A11 DDR2-A12 DDR2-A13 3B23 3B01 33R RES 240R 1X20 HOOK1 DDR2-CLK_P DDR2-CLK_N DDR2-CKE DDR2-CS DDR2-RAS DDR2-CAS DDR2-WE DDR2-DQM0 DDR2-ODT 1X21 HOO
B06A Display interfacing-Vdisp Display interfacing-Vdisp 10-6 B06 393912365213 +VDISP-INT Q552.2L LA 30R RES 2G43 div. table IG11 FG0H 6G00 LTST-C190KGKT RES For Development use only 2K2 RES 3G28 2011-Feb-18 back to T 3.0A 32V RES 30R RES 5G02 T 3.0A 32V 1G03 EN 96 1G00 10. 5G01 22u RES Circuit Diagrams and PWB Layouts 100n 2G44 +VDISP SPB SSB TV550 2K11 4DDR BR SD 2 3 2010-12-10 2010-12-10 19110_044_110415.
47p 47p 47p 47p 2G96 2G99 2G97 2G98 FG11 FG1C FG1D FG1E FG1F FG1G FG1H FG19 FG1A FG1B FG1Q FG1P PX4DPX4D+ PX4EPX4E+ FG18 FG15 FG16 FG17 FG12 FG13 FG14 PX4CLKPX4CLK+ PX4APX4A+ PX4BPX4B+ PX4CPX4C+ FG1J 100n 2G95 FG1K FG1L FG1M FG1N 100n 2G94 PX3DPX3D+ PX3EPX3E+ 100n 2G93 PX3CLKPX3CLK+ PX3APX3A+ PX3BPX3B+ PX3CPX3C+ 100n 2G92 1G50 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 FI-RE41S-HF 50 51 48 49 46 47 44 45 42 43
+3V3 7 +3V3 3G15 8 1 2 3 4 5 6 RES 3GA2-1 RES 3GA2-2 RES 3GA2-3 RES 3GA2-4 1 2 3 4 DEBUG ONLY RES 1G35 1u0 8 7 6 5 GTS1 GTS2 GSR AMBI-SPI-CS-OUTn_R2-R AMBI-PWM-CLK_B2 AMBI-SPI-CS-OUTn_R2 AMBI-LATCH1_G2 AMBI-TEMP CPLED3 CPLED2 PNX-SPI-CS-BLn PNX-SPI-SDO PNX-SPI-SDI PNX-SPI-CLK PXCLK54 GCK2 GCK3 30R 5GA1 10p 2G11 RES 1G36 2GA5 1 2 3 4 5 6 SD51022 100R 100R 100R 100R 2GA1 10p 30R 2GA0 2GA3 10K 100n 10p 2G12 5GA0 100n 2GA2 FGA5 FGA3 BACKLIGHT-PWM +3V3 FGA4 33R 3 33R 11 9 2
B06D SPI buffer SPI buffer Direct +3V3 47R 3GE0-3 47R 3 RES 47R 3GE3 47R 3 2011-Feb-18 back to div. table 3GE4 RES * ** 4 RES 9GE1 BL-SPI-SDI PNX-SPI-CS-BLn 2 RES 9GE0-2 RES 9GE2 RES 5 9GE0-4 IGE0 3GE1-3 6 7 3 4 5 6 7 8 9 2 19 PNX-SPI-SDO 2 3EN1 3EN2 G3 RES 7GE0 74LVC245A 1 EN 99 1 1 +3V3 10. RES 9GE0-1 IGE1 100n 8 17 16 15 14 13 12 11 18 RES 2GE0 PNX-SPI-CLK AMBI-SPI-SDI-OUT_G1-R BL-SPI-SDI PNX-SPI-SDO PNX-SPI-CLK Buffer * ** RES Q552.
Y N N N 1C86 1C87 FAN-DRV FAN-CTRL2 SDA-BL TACH02 SCL-BL TACH01 FAN-CTRL1 EMMY BLOCKBUSTER 2C70 ITEMS * Option table for Ambilight AMBI-BLANK_R1 AMBI-PROG_B1 AMBI-LATCH2_DIS AMBI-TEMP AMBI-SPI-CS-OUTn_R2 AMBI-LATCH1_G2 AMBI-PWM-CLK_B2 AMBI-SPI-SDO-OUT AMBI-SPI-SDI-OUT_G1 3C70 100n AMBI-SPI-CLK-OUT +12V_AL +24V +3V3 +12V +3V3 10K * RES 3C93 100R RES 3C83 FC86 FC64 RES 3C82 FC63 30R RES 5C54 30R RES 5C53 100R * RES 3C92 100R 100R RES3C81 100R FC85 * RES 3C91 100R
3C74 3G38 2C77 3C78 3C77 2C80 2C78 3C79 9U41 3U75 7U42 9U42 3U69 7U43 2C81 3C95 2C86 2C87 2C90 3C94 2C91 6C05 2C82 6C03 2C93 3C76 6C02 3C75 2C76 2G77 2G75 2G76 2G27 2G78 2G26 2G25 2G24 2G79 2G7A 3U68 IC74 IC75 3U59 3U53 3E33 3E51 2E66 9E43 5D05 5D04 2E56 5E02 6E47 3E28 2E07 IE07 2E52 2E53 3E68 5E01 2E63 3E72 3E35 3E34 2E55 2E54 1N00 2E57 3E25 3E22 7E10 9E42 1G50 1D50 1D52 5D08 2D06 2E49 1735 1D38 1G51 1M20 1M19 2G28 3E98 2D24
FFB6 FFB5 FFB3 FFB1 FL40 FL41 FGA4 FFC6 FFB4 3FBF 9FC2 FGA6 FFC8 FL42 FL39 FFC5 3FLG FFDA FFDC FFC3 FFC9 FFC2 IFL3 3FLH IFLE 2FLB 2FL5 2FL2 2FLC 3U25 IU30 IS40 IUB5 IUB4 IFLG IFL2 2UB5 3FLB FF66 IFLD IFLA IFLC IFLF 2UB6 IFL1 IU29 IGE0 9GE1 2GA2 7UA7 3UB6 3UA0 7UA5 2FLA IFL4 FL36 FUA0 2G13 7GE1 9GE2 9GA1 IGE1 3UB7 9F25 9F26 FL37 2FL3 FL30 FC83 7UA0 IUB1 IUB3 2GA6 9GE0 7U06 FUD3 IS17 FC76 IUD7 FFC7 FF65 FF64 FL43 IFLB 2FL8 2FL1
BLOCKBUSTER / EMMY 32" 11-1 Blockbuster/Emmy 32" 11. Styling Sheets 1108 5216 1150 Styling Sheets Q552.2L LA 0004 11. div. table 2011-Feb-18 back to 1004 EN 103 8308 5213 0029 5216 0004 0011 0029 0260 1004 1005 1085 1108 1150 1161 1162 5213 5216 8191 8308 8G50 8G51 Pos No. 1005 Description Front Cabinet Back Cover Hard Switch bracket Stand Display panel Power Supply Unit Remote Control Keyboard + IR assy Board SSB AmbiLight AmbiLight Loudspeaker box Tweeter Mainscord 1.
BLOCKBUSTER / EMMY 40"- 46" 11-2 Blockbuster/Emmy 40" - 46" 1108 5216 Styling Sheets 1150 Q552.2L LA 0004 11. div. table 1004 2011-Feb-18 back to 1005 EN 104 8308 0040 POS. NO. 0004 0011 0040 0260 1004 1005 1085 1108 1150 1161 1162 5213 5216 8191 8308 8G50 8G51 5216 5213 DESCRIPTION. Front Cabinet Back Cover Hard Switch bracket Stand Display panel Power Supply Unit Remote Control Keyboard + IR assy Board SSB AmbiLight AmbiLight Loudspeaker box Tweeter Mainscord 1.
