INTEGRATED CIRCUITS USER MANUAL P89LPC906/907/908 8-bit microcontrollers with accelerated two-clock 80C51 core 1KB 3V Low-Power byte-eraseable Flash with 128 Byte RAM 2003 Dec 8 Philips Semiconductors PHILIPS
User’s Manual - Preliminary - Philips Semiconductors Table of Contents P89LPC906/907/908 1. General Description................................................................................ 7 Pin Configurations ..................................................................................... 7 Product comparison................................................................................... 8 Pin Descriptions - P89LPC906 ................................................................
User’s Manual - Preliminary - Philips Semiconductors Table of Contents P89LPC906/907/908 6. Real-Time Clock/System Timer............................................................ 47 Real-time Clock Source ........................................................................... Changing RTCS1-0 ................................................................................. Real-time Clock Interrupt/Wake Up .........................................................
User’s Manual - Preliminary - Philips Semiconductors Table of Contents P89LPC906/907/908 Power down operation ............................................................................. 84 Watchdog Clock Source .......................................................................... 84 Periodic wakeup from Power down without an external oscillator ........... 85 13. Additional Features............................................................................. 87 Software Reset ...................
User’s Manual - Preliminary - Philips Semiconductors List of Figures P89LPC906/907/908 List of Figures Special function registers table - P89LPC906. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Special function registers table - P89LPC907. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Special function registers table - P89LPC908. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 P89LPC906/907/908 Memory Map . . . . . . . . . . . . . . . .
User’s Manual - Preliminary - Philips Semiconductors List of Figures P89LPC906/907/908 Serial Port Control Register (SCON). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Port Status Register (SSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serial Port Mode 0 (Double Buffering Must Be Disabled) . . . . . . . . . . . . . . . . . . . . . . . . . Serial Port Mode 1 (Only Single Transmit Buffering Case Is Shown) . . . . . . . .
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION P89LPC906/907/908 1. GENERAL DESCRIPTION The P89LPC906/907/908 is a single-chip microcontroller designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC906/907/908 is based on a high performance processor architecture that executes instructions six times the rate of standard 80C51 devices.
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION P89LPC906/907/908 Logic Symbols XTAL1 VDD CIN1A CMPREF CMP1 P89 LPC907 PORT0 KBI4 KBI5 KBI6 CIN1A CMPREF CMP1 PORT0 VDD KBI4 KBI5 KBI6 P89 LPC908 The following table highlights differences between these three devices.
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION P89LPC906/907/908 Block Diagram - P89LPC906 High Performance Accelerated 2-clock 80C51 CPU 1 KB Code Flash Internal Bus 128 byte Data RAM Port 3 Configurable I/Os Timer0 Timer1 Real-Time Clock/ System Timer Port 1 Input Port 0 Configurable I/Os Analog Comparator Keypad Interrupt Watchdog Timer and Oscillator Programmable Oscillator Divider Crystal or Resonator 2003 Dec 8 Configurable Oscillator CPU Clock Power Monitor
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION P89LPC906/907/908 Block Diagram - P89LPC907 High Performance Accelerated 2-clock 80C51 CPU 1 KB Code Flash Internal Bus UART 128 byte Data RAM Timer0 Timer1 Port 1 Configurable I/O Real-Time Clock/ System Timer Port 0 Configurable I/Os Analog Comparator Keypad Interrupt Watchdog Timer and Oscillator Programmable Oscillator Divider CPU Clock Power Monitor (Power-On Reset, Brownout Reset) On-Chip RC Oscillator 2003 Dec 8 10
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION P89LPC906/907/908 Block Diagram - P89LPC908 High Performance Accelerated 2-clock 80C51 CPU UART 1 KB Code Flash Internal Bus Timer0 Timer1 128 byte Data RAM Real-Time Clock/ System Timer Port 1 Configurable I/Os Port 0 Configurable I/Os Analog Comparator Keypad Interrupt Watchdog Timer and Oscillator Programmable Oscillator Divider CPU Clock Power Monitor (Power-On Reset, Brownout Reset) On-Chip RC Oscillator 2003 Dec 8
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION P89LPC906/907/908 PIN DESCRIPTIONS - P89LPC906 Mnemonic P0.4 - P0.6 Pin no. 3, 7,8 Type Name and function I/O Port 0: Port 0 is an I/O port with a user-configurable output types. During reset Port 0 latches are configured in the input only mode with the internal pullup disabled. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently.
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION P89LPC906/907/908 PIN DESCRIPTIONS - P89LPC907 Mnemonic P0.4 - P0.6 Pin no. 3, 7,8 Type I/O Name and function Port 0: Port 0 is an I/O port with a user-configurable output types. During reset Port 0 latches are configured in the input only mode with the internal pullup disabled. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently.
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION P89LPC906/907/908 PIN DESCRIPTIONS - P89LPC908 Mnemonic P0.4 - P0.6 Pin no. 3, 7,8 Type I/O Name and function Port 0: Port 0 is an I/O port with a user-configurable output types. During reset Port 0 latches are configured in the input only mode with the internal pullup disabled. The operation of port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently.
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION P89LPC906/907/908 Special function registers Note: Special function registers (SFRs) accesses are restricted in the following ways: 1. User must NOT attempt to access any SFR locations not defined. 2. Accesses to any defined SFR locations must be strictly for the functions for the SFRs. 3.
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION Name Description P89LPC906/907/908 Bit Functions and Addresses SFR Address MSB Reset Value LSB Hex Binary IP1H# Interrupt Priority 1 High F7H - - - - - PCH PKBIH - 00H1 00x00000 KBCON# Keypad Control Register 94H - - - - - - PATN_S EL KBIF 00H1 xxxxxx00 KBMASK# Keypad Interrupt Mask Register 86H 00H 00000000 KBPATN# Keypad Pattern Register 93H FFH 11111111 87 P0* Port 0 80H - 97 P1* Port
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION Name Description SFR Address P89LPC906/907/908 Bit Functions and Addresses Reset Value LSB MSB Hex Binary TH0 Timer 0 High 8CH 00H 00000000 TH1 Timer 1 High 8DH 00H 00000000 TL0 Timer 0 Low 8AH 00H 00000000 TL1 Timer 1 Low 8BH TMOD Timer 0 and 1 Mode 89H - - T1M1 T1M0 - - T0M1 T0M0 TRIM# Internal Oscillator Trim Register 96H - ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION P89LPC906/907/908 Table 2: Special function registers table - P89LPC907 Name Description SFR Address Bit Functions and Addresses Reset Value LSB MSB Hex Binary 00H 00000000 00H1 000000x0 F0H 00H 00000000 BRGR0#§ Baud Rate Generator Rate Low BEH 00H 00000000 BRGR1#§ Baud Rate Generator Rate High BFH 00H 00000000 BRGCON# Baud Rate Generator Control BDH - - - - - - SBRGS BRGEN 00H xxxxxx00 CMP1# Com
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION Name Description SFR Address P89LPC906/907/908 Bit Functions and Addresses Reset Value LSB MSB Hex Binary KBMASK# Keypad Interrupt Mask Register 86H 00H 00000000 KBPATN# Keypad Pattern Register 93H FFH 11111111 87 P0* P1* Port 0 Port 1 80H 90H - 86 85 84 CMP1/ CMPREF/ CIN1A/ KB6 KB5 KB4 83 82 81 80 - KB2 - KB0 97 96 95 94 93 92 91 90 - - RST - - T0 - TxD B7 B6 B5 B4 B3 B2 B1 B
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION Name Description SFR Address P89LPC906/907/908 Bit Functions and Addresses Reset Value LSB MSB Hex Binary TH0 Timer 0 High 8CH 00H 00000000 TH1 Timer 1 High 8DH 00H 00000000 TL0 Timer 0 Low 8AH 00H 00000000 TL1 Timer 1 Low 8BH 00H 00000000 TMOD Timer 0 and 1 Mode 89H - - T1M1 T1M0 - - T0M1 T0M0 00H 00000000 TRIM# Internal Oscillator Trim Register 96H - - TRIM.5 TRIM.4 TRIM.3 TRIM.
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION P89LPC906/907/908 Table 3: Special function registers table - P89LPC908 Name Description SFR Address Bit Functions and Addresses Reset Value LSB MSB Hex Binary 00H 00000000 00H1 000000x0 F0H 00H 00000000 BRGR0#§ Baud Rate Generator Rate Low BEH 00H 00000000 BRGR1#§ Baud Rate Generator Rate High BFH 00H 00000000 BRGCON# Baud Rate Generator Control BDH - - - - - - SBRGS BRGEN 00H xxxxxx00 CMP1# Com
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION Name Description SFR Address P89LPC906/907/908 Bit Functions and Addresses Reset Value LSB MSB Hex Binary KBMASK# Keypad Interrupt Mask Register 86H 00H 00000000 KBPATN# Keypad Pattern Register 93H FFH 11111111 87 P0* P1* Port 0 Port 1 80H 90H - 86 85 84 CMP1/ CMPREF/ CIN1A/ KB6 KB5 KB4 83 82 81 80 - KB2 - - 97 96 95 94 93 92 91 90 - - RST - - - RxD TxD Note 1 P0M1# Port 0 Output M
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION Name Description SFR Address P89LPC906/907/908 Bit Functions and Addresses Reset Value LSB MSB Hex Binary TL0 Timer 0 Low 8AH 00H 00000000 TL1 Timer 1 Low 8BH 00H 00000000 TMOD Timer 0 and 1 Mode 89H - - T1M1 T1M0 - - T0M1 T0M0 00H 00000000 TRIM# Internal Oscillator Trim Register 96H - - TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.
User’s Manual - Preliminary - Philips Semiconductors GENERAL DESCRIPTION P89LPC906/907/908 MEMORY ORGANIZATION The P89LPC906/907/908 memory map is shown in Figure 1-1. 03FFh 0300h 02FFh 0200h 01FFh 0100h 00FFh Sector 3 Special Function Registers (directly addressable) Sector 2 DATA 128 Bytes On-Chip Data Memory (stack, direct and indir. addr.) 4 Reg.
User’s Manual - Preliminary - Philips Semiconductors CLOCKS P89LPC906/907/908 2. CLOCKS ENHANCED CPU The P89LPC906/907/908 uses an enhanced 80C51 CPU which runs at 6 times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. CLOCK DEFINITIONS The P89LPC906/907/908 device has several internal clocks as defined below: • OSCCLK - Input to the DIVM clock divider.
User’s Manual - Preliminary - Philips Semiconductors CLOCKS P89LPC906/907/908 Quartz crystal or ceramic resonator P89LPC906 The oscillator must be configured in one of the following modes: - Low Frequency Crystal - Medium Frequency Crystal - High Frequency Crystal XTAL1 * * A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals.
User’s Manual - Preliminary - Philips Semiconductors CLOCKS P89LPC906/907/908 EXTERNAL CLOCK INPUT OPTION - P89LPC906 In this configuration, the processor clock is derived from an external source driving the XTAL1 / P3.1 pin. The rate may be from 0 Hz up to 12 MHz. The XTAL2 / P3.0 pin may be used as a standard port pin or a clock output. . TRIM Address: 96h 7 6 5 4 3 2 1 0 - ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.
User’s Manual - Preliminary - Philips Semiconductors CLOCKS P89LPC906/907/908 LOW POWER SELECT (P89LPC906) The P89LPC906 is designed to run at 12MHz (CCLK) maximum. However, if CCLK is 8MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a ’1’ to lower the power consumption further. On any reset, CLKLP is ’0’ allowing highest performance. This bit can then be set in software if CCLK is running at 8MHz or slower. RTCS1:0 XTAL1 XTAL2 High freq. Med freq. RTC Low freq.
User’s Manual - Preliminary - Philips Semiconductors CLOCKS P89LPC906/907/908 R T C S 1 :0 RTC CPU C lo ck F O S C 2 :0 OSC CLK D IV M CCLK CPU R C O scillato r /2 (7.
User’s Manual - Preliminary - Philips Semiconductors CLOCKS 2003 Dec 8 P89LPC906/907/908 30
User’s Manual - Preliminary - Philips Semiconductors INTERRUPTS P89LPC906/907/908 3. INTERRUPTS The P89LPC906/907/908 use a four priority level interrupt structure. This allows great flexibility in controlling the handling of the many interrupt sources. The P89LPC906 supports 6 interrupt sources: timers 0 and 1, brownout detect, watchdog/ realtime clock, keyboard, and the comparator.
User’s Manual - Preliminary - Philips Semiconductors INTERRUPTS P89LPC906/907/908 Table 3-3: Summary of Interrupts - P89LPC907,P89LPC908 Interrupt Vector Interrupt Description Flag Bit(s) Address Enable Bit(s) Timer 0 Interrupt Timer 1 Interrupt Serial Port Tx and Rx 1,3 1,3 Serial Port Rx Brownout Detect Watchdog Timer/Realtime Clock KBI Interrupt Comparator interrupt 2 Serial Port Tx Interrupt Priority Arbitration Ranking Power down Wakeup TF0 000Bh ET0 (IEN0.1) IP0H.1, IP0.
User’s Manual - Preliminary - Philips Semiconductors INTERRUPTS P89LPC906/907/908 BOPD EBO RTCF ERTC (RTCCON.1) WDOVF Wakeup (if in Power down) KBIF EKBI EWDRT CMF EC EA (IE0.7) TF1 ET1 Interrupt to CPU TF0 ET0 Figure 3-1: Interrupt sources, enables, and Power down Wake-up sources - P89LPC906 BOPD EBO RTCF ERTC (RTCCON.1) WDOVF Wakeup (if in Power down) KBIF EKBI EWDRT CMF EC EA (IE0.
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User’s Manual - Preliminary - Philips Semiconductors I/O PORTS P89LPC906/907/908 4. I/O PORTS The P89LPC906/907/908 has between 3 and 6 I/O pins.
User’s Manual - Preliminary - Philips Semiconductors I/O PORTS P89LPC906/907/908 The third pullup is referred to as the "strong" pullup. This pullup is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong pullup turns on for two CPU clocks quickly pulling the port pin high . The quasi-bidirectional port configuration is shown in Figure 4-1.
User’s Manual - Preliminary - Philips Semiconductors I/O PORTS P89LPC906/907/908 INPUT-ONLY CONFIGURATION The input port configuration is shown in Figure 4-3.
User’s Manual - Preliminary - Philips Semiconductors I/O PORTS P89LPC906/907/908 Table 4-3: Port Output Configuration - P89LPC906 Port Pin Configuration SFR Bits PxM1.y PxM2.y P0.4 P0M1.4 P0M2.4 KBI4,CIN1A P0.5 P0M1.5 P0M2.5 KBI5,CMPREF P0.6 P0M1.6 P0M2.6 KBI6,CMP1 P1.5 Table 4-4: Alternate Usage not configurable RST P3.0 P3M1.0 P3M2.0 XTAL2,CLKOUT P3.1 P3M1.1 P3M2.1 XTAL1 Notes Refer to section "Port 0 Analog Functions" for usage as analog inputs CIN1A and CMPREF.
User’s Manual - Preliminary - Philips Semiconductors I/O PORTS P89LPC906/907/908 All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.
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User’s Manual - Preliminary - Philips Semiconductors TIMERS 0 AND 1 P89LPC906/907/908 5. TIMERS 0 AND 1 The P89LPC906/907/908 has two general-purpose counter/timers which are similar to the 80C51 Timer 0 and Timer 1. Timer 0 of the P89LPC907 can be configured to operate either as a timer or event counter (see Figure 5-1). An option to automatically toggle the T0 pin upon timer overflow has been added.
User’s Manual - Preliminary - Philips Semiconductors TIMERS 0 AND 1 P89LPC906/907/908 TAMOD - P89LPC907 7 6 5 4 3 2 1 0 Address: 8Fh - - - - - - - T0M2 Not bit addressable Reset Source(s): Any reset Reset Value: xxx0xxx0B BIT SYMBOL TAMOD.7-1 TAMOD.0 - FUNCTION Reserved for future use. Should not be set to 1 by user programs. T0M2 TnM2-TnM0 Mode Select bit 2 for Timer 0. Used with T0M1 and T0M0 in the TMOD register to determine Timer 0 mode (P89LPC907).
User’s Manual - Preliminary - Philips Semiconductors TIMERS 0 AND 1 P89LPC906/907/908 MODE 3 When Timer 1 is in Mode 3 it is stopped. The effect is the same as setting TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for Mode 3 on Timer 0 is shown in Figure 5-7. TL0 uses the Timer 0 control bits: TR0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1.
User’s Manual - Preliminary - Philips Semiconductors TIMERS 0 AND 1 P89LPC906/907/908 Overflow T0C/T = 0 PCLK T0 Pin* T0C/T = 1 Control TLn (5-bits) THn (8-bits) TFn Interrupt Toggle TRn T0 Pin* ENT0 (AUXR1.4) * T0 Pin functions available on P89LPC907 Figure 5-4: Timer/Counter 0 or 1 in Mode 0 (13-bit counter) Overflow T0C/T = 0 PCLK T0 Pin* T0C/T = 1 Control TLn (8-bits) THn (8-bits) TFn Interrupt Toggle TRn T0 Pin* ENT0 (AUXR1.
User’s Manual - Preliminary - Philips Semiconductors TIMERS 0 AND 1 P89LPC906/907/908 C/T = 0 PCLK T0 Pin* C/T = 1 Control TL0 (8-bits) Overflow TF0 Interrupt Toggle T0 Pin* TR0 ENT0 PCLK Control TH0 (8-bits) TR1 Overflow TF1 Interrupt * T0 Pin functions available on P89LPC907 Figure 5-7: Timer/Counter 0 Mode 3 (two 8-bit counters) T0C/T = 0 PCLK Control TL0 (8-bits) Overflow TF0 Interrupt Reload TH0 on falling transition and (256-TH0) on rising transition Toggle TR0 T0 Pin T
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User’s Manual - Preliminary - Philips Semiconductors REAL-TIME CLOCK/SYSTEM TIMER P89LPC906/907/908 6. REAL-TIME CLOCK/SYSTEM TIMER The P89LPC906/907/908 has a simple Real-time clock/system timer that allows a user to continue running an accurate timer while the rest of the device is powered down. The Real-time clock can be an interrupt or a wake-up source (see Figure 6-2). The Real-time clock is a 23-bit down counter.
User’s Manual - Preliminary - Philips Semiconductors REAL-TIME CLOCK/SYSTEM TIMER P89LPC906/907/908 Power-On Reset RTCH XTAL2 XTAL1 RTC Reset RTCL Reload on underflow MSB LSB Low freq. Med. freq. High freq. 7-bit prescaler 23-bit down counter ÷ 128 CCLK Int. Osc’s W ake up from Power-down RTCEN RTCF Interrupt if enabled (shared w.
User’s Manual - Preliminary - Philips Semiconductors REAL-TIME CLOCK/SYSTEM TIMER FOSC2 FOSC1 FOSC0 RTCS1:0 (UCFG1.2) (UCFG1.1) (UCFG1.
User’s Manual - Preliminary - Philips Semiconductors REAL-TIME CLOCK/SYSTEM TIMER FOSC2 FOSC1 FOSC0 RTCS1:0 (UCFG1.2) (UCFG1.1) (UCFG1.0) CCLK Frequency P89LPC906/907/908 RTC Clock Frequency 00 01 1 0 0 10 undefined WDT Oscillator/DIVM WDT Oscillator/DIVM (CCLK) 11 1 0 1 1 1 0 1 1 1 xx undefined CHANGING RTCS1-0 RTCS1-0 cannot be changed if the RTC is currently enabled (RTCCON.0 =1). Setting RTCEN and updating RTCS1-0 may be done in a single write to RTCCON.
User’s Manual - Preliminary - Philips Semiconductors REAL-TIME CLOCK/SYSTEM TIMER P89LPC906/907/908 RTCCON Address: D1h Not bit addressable 7 6 5 4 3 2 1 0 RTCF RTCS1 RTCS0 - - - ERTC RTCEN Reset Source(s): Power-up only Reset Value: 011xxx00B BIT RTCCON.7 SYMBOL RTCF RTCCON.6-5 RTCS1-0 RTCCON.4-2 - FUNCTION Real-time Clock Flag. This bit is set to ’1’ when the 23-bit Real-time clock reaches a count of ’0’. It can be cleared in software.
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User’s Manual - Preliminary - Philips Semiconductors POWER MONITORING FUNCTIONS P89LPC906/907/908 7. POWER MONITORING FUNCTIONS The P89LPC906/907/908 incorporates power monitoring functions designed to prevent incorrect operation during initial poweron and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and Brownout Detect. BROWNOUT DETECTION The Brownout Detect function determines if the power supply voltage drops below a certain level.
User’s Manual - Preliminary - Philips Semiconductors POWER MONITORING FUNCTIONS P89LPC906/907/908 Table 7-1: Brownout Options BOE (UCFG1.5) PMOD1-0 (PCON.1-0) BOPD (PCON.5) BOI (PCON.4) EBO (IEN0.5) EA (IEN0.7) 0 (erased) XX X X X X 11 (total power down) X X X X 1 (brownout detect powered down) X X X Brownout disabled. VDD operating range is 2.4V-3.6V. However, BOPD is default to ’0’ upon power-up. X X Brownout reset enabled. VDD operating range is 2.7V3.6V.
User’s Manual - Preliminary - Philips Semiconductors POWER MONITORING FUNCTIONS P89LPC906/907/908 Table 7-2: Power Reduction Modes PMOD1 (PCON.1) PMOD0 (PCON.0) 0 0 Normal Mode (Default) - no power reduction. 0 1 Idle Mode. The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.
User’s Manual - Preliminary - Philips Semiconductors POWER MONITORING FUNCTIONS 7 PCON 6 SMOD1 SMOD0 Address: 87h P89LPC906/907/908 5 4 3 2 BOPD BOI GF1 GF0 1 0 PMOD1 PMOD0 Not bit addressable Reset Source(s): Any reset Reset Value: BIT 00000000B SYMBOL FUNCTION PCON.7 SMOD1 Double Baud Rate bit for the serial port (UART) when Timer 1 is used as the baud rate source. When 1, the Timer 1 overflow rate is supplied to the UART.
User’s Manual - Preliminary - Philips Semiconductors POWER MONITORING FUNCTIONS P89LPC906/907/908 PCONA Address: B5H Not bit addressable 7 6 5 4 3 2 1 0 RTCPD - VCPD - - - SPD - Reset Source(s): Any reset Reset Value: 00000000B BIT SYMBOL FUNCTION PCONA.7 RTCPD Real-time Clock Power down: When ’1’, the internal clock to the Real-time Clock is disabled. PCONA.6 - PCONA.5 VCPD PCONA.4 - Not used. Reserved for future use. PCONA.3 - Not used. Reserved for future use. PCONA.
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User’s Manual - Preliminary - Philips Semiconductors UART P89LPC906/907/908 8. UART (P89LPC907, P89LPC908) The P89LPC907 and P89LPC908 devices have an enhanced UART that is compatible with the conventional 80C51 UART, except that Timer 2 overflow cannot be used as a baud rate source. The UART does include an independent Baud Rate Generator. The baud rate can be selected from the CCLK (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator.
User’s Manual - Preliminary - Philips Semiconductors UART P89LPC906/907/908 SFR SPACE The UART SFRs are at the following locations: Table 8-1: SFR Locations for UARTs Register Description SFR Location PCON Power Control 87H SCON Serial Port (UART) Control 98H SBUF Serial Port (UART) Data Buffer 99H SADDR Serial Port (UART) Address A9H SADEN Serial Port (UART) Address Enable B9H SSTAT Serial Port (UART) Status BAH BRGR1 Baud Rate Generator Rate High Byte BFH BRGR0 Baud Rate Genera
User’s Manual - Preliminary - Philips Semiconductors UART P89LPC906/907/908 BRGCON Address: BDh 7 6 5 4 3 2 Not bit addressable - - - - - - 1 0 SBRGS BRGEN Reset Source(s): Any reset Reset Value: xxxxxx00B BIT SYMBOL BRGCON.7-2 - FUNCTION Reserved for future use. Should not be set to 1 by user programs. BRGCON.1 SBRGS Select Baud Rate Generator as the source for baud rates to UART in modes 1 & 3 (see Table for details) BRGCON.0 BRGEN Baud Rate Generator Enable.
User’s Manual - Preliminary - Philips Semiconductors UART P89LPC906/907/908 . SCON Address: 98h Bit addressable 7 6 5 4 3 2 1 0 SM0/FE SM1 SM2 REN TB8 RB8 TI RI Reset Source(s): Any reset Reset Value: 00000000B BIT SCON.7 SCON. 6 SYMBOL SM0/FE SM1 FUNCTION The use of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0, this bit is read and written as SM0, which with SM1, defines the serial port mode. If SMOD0 = 1, this bit is read and written as FE (Framing Error).
User’s Manual - Preliminary - Philips Semiconductors UART P89LPC906/907/908 SSTAT Address: BAh Not bit addressable Reset Source(s): Any reset 7 6 5 4 3 2 1 0 DBMOD INTLO CIDIS DBISEL FE BR OE STINT Reset Value: 00000000B BIT SYMBOL FUNCTION SSTAT.7 DBMOD Double buffering mode. When set = 1 enables double buffering. Must be ’0’ for UART mode 0. In order to be compatible with existing 80C51 devices, this bit is reset to ’0’ to disable double buffering. SSTAT.
User’s Manual - Preliminary - Philips Semiconductors UART P89LPC906/907/908 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...S16 S1...
User’s Manual - Preliminary - Philips Semiconductors UART P89LPC906/907/908 MORE ABOUT UART MODES 2 AND 3 Reception is the same as in Mode 1. The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. (a) RI = 0, and (b) Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is lost, and RI is not set.
User’s Manual - Preliminary - Philips Semiconductors UART P89LPC906/907/908 DOUBLE BUFFERING The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, provided the next character is written between the start bit and the stop bit of the previous character. Double buffering can be disabled.
User’s Manual - Preliminary - Philips Semiconductors UART P89LPC906/907/908 TxD Write to SBUF Tx Interrupt Single Buffering (DBMOD/SSTAT.7 = 0), Early Interrupt (INTLO/SSTAT.6 = 0) is Shown TxD Write to SBUF Tx Interrupt Double Buffering (DBMOD/SSTAT.7 = 1), Early Interrupt (INTLO/SSTAT.6 = 0) is Shown, No Ending Tx Interrupt (DBISEL/SnSTAT.4 = 0) TxD Write to SBUF Tx Interrupt Double Buffering (DBMOD/SSTAT.7 = 1), Early Interrupt (INTLO/SSTAT.6 = 0) is Shown, With Ending Tx Interrupt (DBISEL/SSTAT.
User’s Manual - Preliminary - Philips Semiconductors UART P89LPC906/907/908 - If DBISEL is ’1’ and INTLO is ’1’, a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter (which is also the last data). 7. If there is more data, the CPU writes to TB8 again. 8. The CPU writes to SBUF again. Then: - If INTLO is ’0’, the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter.
User’s Manual - Preliminary - Philips Semiconductors UART P89LPC906/907/908 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.
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User’s Manual - Preliminary - Philips Semiconductors RESET P89LPC906/907/908 9. RESET The P1.5/RST pin can function as either an active low reset input or as a digital input, P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin. NOTE: During a power-on sequence, The RPE selection is overriden and this pin will always functions as a reset input.
User’s Manual - Preliminary - Philips Semiconductors RESET P89LPC906/907/908 RSTSRC Address: DFH 7 6 5 4 3 2 1 0 Not bit addressable - - BOF POF R_BK R_WD R_SF R_EX Reset Sources: Power-on only Reset Value: xx110000B (This is the power-on reset value. Other reset sources will set corresponding bits.) BIT RSTSRC.7-6 SYMBOL - FUNCTION Reserved for future use. Should not be set to 1 by user programs. RSTSRC.5 BOF Brownout Detect Flag.
User’s Manual - Preliminary - Philips Semiconductors ANALOG COMPARATORS P89LPC906/907/908 10. ANALOG COMPARATORS An analog comparator is provided on the P89LPC906/907/908 . Comparator operation is such that the output is a logical one when the positive input is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. The output may be read in a register. The output may also be routed to a pin.
User’s Manual - Preliminary - Philips Semiconductors ANALOG COMPARATORS P89LPC906/907/908 Comparator 1 OE1 + (P0.4) CIN1A CO1 (P0.5) CMPREF CMP1 (P0.6) - Vref Change Detect CN1 Interrupt CMF1 EC Figure 10-2: Comparator Input and Output Connections CN1, OE1 = 0 0 CIN1A + CMPREF - CN1, OE1 = 0 1 CO1 CIN1A + CMPREF - CN1, OE1 = 1 0 CIN1A + Vref (1.23V) - CO1 CMP1 CN1, OE 1= 1 1 CO1 CIN1A + Vref (1.
User’s Manual - Preliminary - Philips Semiconductors ANALOG COMPARATORS P89LPC906/907/908 If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in power down mode. The reason is that with the oscillator stopped, the temporary strong pullup that normally occurs during switching on a quasi-bidirectional port pin does not take place.
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User’s Manual - Preliminary - Philips Semiconductors KEYPAD INTERRUPT (KBI) P89LPC906/907/908 11. KEYPAD INTERRUPT (KBI) The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when the Port 0 bits are equal to or not equal to a certain pattern. This function can be used for keypad recognition. The user can configure the port via SFRs for different tasks. There are three SFRs used for this function.
User’s Manual - Preliminary - Philips Semiconductors KEYPAD INTERRUPT (KBI) KBMASK 7 Address: 86h - 6 P89LPC906/907/908 5 4 KBMASK.6 KBMASK.5 KBMASK.4 3 2 1 0 - - - - Not bit addressable Reset Source(s): Any reset Reset Value: 00000000B BIT SYMBOL FUNCTION KBMASK.7 - Reserved. KBMASK.6 - When set, enables P0.6 as a cause of a Keypad Interrupt. KBMASK.5 - When set, enables P0.5 as a cause of a Keypad Interrupt. KBMASK.4 - When set, enables P0.
User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER P89LPC906/907/908 12. WATCHDOG TIMER The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. The watchdog timer can only be reset by a power-on reset.
User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER Watchdog Oscillator PCLK P89LPC906/907/908 ÷32 ÷2 ÷32 ÷64 ÷2 ÷128 ÷2 ÷256 ÷2 ÷512 ÷2 ÷1024 ÷2 ÷2048 ÷2 ÷4096 WDCLK after a watchdog feed sequence PRE2 DECODE PRE1 PRE0 TO WATCHDOG DOWN COUNTER (after one prescaler count delay 000 001 010 011 100 101 110 111 Figure 12-1: Watchdog Prescaler FEED SEQUENCE The watchdog timer control register and the 8-bit down counter (Figure 12-3) are not directly loaded by the user.
User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER P89LPC906/907/908 MOV WFEED1,#0A5h ; do watchdog feed part 1 MOV WFEED2,#05Ah ; do watchdog feed part 2 SETB EA ; enable interrupt In timer mode (WDTE = 0), WDCON is loaded to the control register every CCLK cycle (no feed sequence is required to load the control register), but a feed sequence is required to load from the WDL SFR to the 8-bit down counter before a time-out occurs.
User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER P89LPC906/907/908 Table 12-2: P89LPC906/907/908 Watchdog Timeout Values PRE2-PRE0 000 001 010 011 100 101 110 111 2003 Dec 8 Watchdog Clock Source WDL in decimal) Timeout Period (in watchdog clock cycles) 400KHz Watchdog Oscillator Clock (Nominal) 12MHz CCLK (6MHz CCLK/2 Watchdog Clock) 0 33 82.5µs 5.50µs 255 8,193 20.5ms 1.37ms 0 65 162.5µs 10.8µs 255 16,385 41.0ms 2.73ms 0 129 322.5µs 21.
User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER P89LPC906/907/908 WDL (C1H) MOV WFEED1, #0A5H MOV WFEED2, #05AH Watchdog Oscillator PCLK ÷32 8-Bit Down Counter PRESCALER RESET Watchdog reset can also be caused by an invalid feed sequence, or by writing to WDCON not immediately followed by a feed sequence SHADOW REGISTER FOR WDCON control register PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK WDCON(A7H) Figure 12-3: Watchdog Timer in Watchdog Mode (WDTE = 1) WATCHDOG TIMER IN TIMER
User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER P89LPC906/907/908 WDL (C1H) MOV WFEED1, #0A5H MOV WFEED2, #05AH Watchdog Oscillator ÷32 8-Bit Down Counter PRESCALER CLK Interrupt SHADOW REGISTER FOR WDCON control register PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK WDCON(A7H) Figure 12-4: Watchdog Timer in Timer Mode (WDTE = 0) POWER DOWN OPERATION The WDT oscillator will continue to run in power down, consuming approximately 50uA, as long as the WDT oscillator is selected as t
User’s Manual - Preliminary - Philips Semiconductors WATCHDOG TIMER P89LPC906/907/908 PERIODIC WAKEUP FROM POWER DOWN WITHOUT AN EXTERNAL OSCILLATOR Without using an external oscillator source, the power consumption required in order to have a periodic wakeup is determined by the power consumption of the internal oscillator source used to produce the wakeup.The Real-time clock running from the internal RC oscillator can be used. The power consumption of this oscillator is approximately 300uA.
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User’s Manual - Preliminary - Philips Semiconductors ADDITIONAL FEATURES P89LPC906/907/908 13. ADDITIONAL FEATURES The AUXR1 register contains several special purpose control bits that relate to several chip features. AUXR1 is described in Figure 13-1. AUXR1 Address: A2h 7 6 5 4 3 2 1 0 CLKLP EBRR - - SRST 0 - DPS Not bit addressable Reset Source(s): Any reset Reset Value: 000000x0B BIT SYMBOL FUNCTION AUXR1.7 CLKLP Clock Low Power Select.
User’s Manual - Preliminary - Philips Semiconductors ADDITIONAL FEATURES P89LPC906/907/908 • MOV DPTR, #data16 Load the Data Pointer with a 16-bit constant. • MOVCA, @A+DPTR Move code byte relative to DPTR to the accumulator. • MOVXA, @DPTR Move data byte the accumulator to data memory relative to DPTR. • MOVX@DPTR, A Move data byte from data memory relative to DPTR to the accumulator.
User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC906/907/908 14. FLASH PROGRAM MEMORY GENERAL DESCRIPTION The P89LPC906/907/908 Flash memory provides in-circuit electrical erasure and programming. The Flash can be read and written as bytes. On-chip erase and write timing generation contribute to a user-friendly programming interface. The cell is designed to optimize the erase and programming mechanisms.
User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC906/907/908 "wrap -around" to the first byte in the page register, but will not affect FMADRL[7:4]. Bytes loaded into the page register do not have to be continuous. Any byte location can be loaded into the page register by changing the contents of FMADRL prior to writing to FMDATA. However, each location in the page register can only be written once following each LOAD command.
User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY FMCON Address: E4h P89LPC906/907/908 7 6 5 4 3 2 1 0 - - - - HVA HVE SV OI Not bit addressable Reset Source(s): Any reset Reset Value: BIT SYMBOL FMCON.7-4 - FUNCTION Reserved. FMCON.3 HVA High voltage abort. Set if either an interrupt or a brown-out is detected during a program or erase cycle. Also set if the brown-out detector is disabled at the start of a program or erase cycle. FMCON.
User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC906/907/908 Figure 14-2: Assembly language routine to erase/program all or part of a page unsigned char idata dbytes[16]; unsigned char Fm_stat; // data buffer // status result bit PGM_USER (unsigned char, unsigned char); bit prog_fail; void main () { prog_fail=PGM_USER(0x1F,0xC0); } bit PGM_USER (unsigned char page_hi, unsigned char page_lo) { #define LOAD 0x00 // clear page register, enable loading #define EP 0x68 // er
User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC906/907/908 Table 14-1: Flash elements accesable through IAP-Lite Element Address Description UCFG1 00h User Configuration byte 1.
User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC906/907/908 r ;* Inputs: ;* R5 = data to write(byte) ;* R7 = element address(byte) ;* Outputs: ;* None CONF EQU * * * * * 6CH WR_ELEM: MOV MOV MOV MOV MOV ANL JNZ CLR RET BAD: SETB RET FMADRL,R7 FMCON,#CONF FMDAT,R5 R7,FMCON A,R7 A,#0FH BAD C ;write the address ;load CONF command ;write the data ;copy status for return ;read status ;save only four lower bits ;see if good or bad ;clear error flag if good ;and return C
User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC906/907/908 #include
User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC906/907/908 USER CONFIGURATION BYTES A number of user-configurable features of the P89LPC906/907/908 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of Flash byte UCFG1 shown in Figure 14-7. UCFG1 Address: xxxxh 7 6 5 4 3 2 1 0 WDTE RPE BOE WDSE - FOSC2 FOSC1 FOSC0 Default: 63h BIT SYMBOL FUNCTION UCFG1.
User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC906/907/908 USER SECURITY BYTES There are four User Sector Security Bytes (SEC0, ..., SEC3), each corresponding to one sector and having the following bit assignments: SECx Address: xxxxh 7 6 5 4 3 2 - - - - - EDISx 1 0 SPEDISx MOVCDISx Unprogrammed value: 00h BIT SYMBOL SECx.7-3 - FUNCTION Reserved (should remain unprogrammed at zero). SECx.2 EDISx Erase Disable x.
User’s Manual - Preliminary - Philips Semiconductors FLASH PROGRAM MEMORY P89LPC906/907/908 Boot Vector BOOTVEC 7 6 5 Address: xxxxh - - - 4 3 2 1 0 BOOTV4 BOOTV3 BOOTV2 BOOTV1 BOOTV0 Factory default value: 00h BIT SYMBOL FUNCTION BOOTVEC.7-5 - Reserved (should remain unprogrammed at zero). BOOTVEC.4-0 - Boot Vector.
User’s Manual - Preliminary - Philips Semiconductors INSTRUCTION SET P89LPC906/907/908 15.
User’s Manual - Preliminary - Philips Semiconductors INSTRUCTION SET P89LPC906/907/908 Mnemonic Hex code Bytes Cycles AND A to direct byte 2 1 52 AND immediate to direct byte 3 2 53 ORL A,Rn OR register to A 1 1 48-4F ORL A,dir OR direct byte to A 2 1 45 ORL A,@Ri OR indirect memory to A 1 1 46-47 ORL A,#data OR immediate to A 2 1 44 ORL dir,A OR A to direct byte 2 1 42 OR immediate to direct byte 3 2 43 XRL A,Rn Exclusive-OR register to A 1 1 68-6F XRL A,di
User’s Manual - Preliminary - Philips Semiconductors INSTRUCTION SET P89LPC906/907/908 Mnemonic Hex code Bytes Cycles Move immediate to direct byte 3 2 75 MOV @Ri,A Move A to indirect memory 1 1 F6-F7 MOV @Ri,dir Move direct byte to indirect memory 2 2 A6-A7 MOV @Ri,#data Move immediate to indirect memory 2 1 76-77 Move immediate to data pointer 3 2 90 Move code byte relative DPTR to A 1 2 93 Move code byte relative PC to A 1 2 94 MOVX A,@Ri Move external data(A8) to
User’s Manual - Preliminary - Philips Semiconductors INSTRUCTION SET P89LPC906/907/908 Mnemonic Description Bytes Cycles Hex code ACALL addr 11 Absolute jump to subroutine 2 2 116F1 LCALL addr 16 Long jump to subroutine 3 2 12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LJMP addr 16 Long jump unconditional 3 2 02 Short jump (relative address) 2 2 80 JC rel Jump on carry = 1 2 2 40 JNC r
User’s Manual - Preliminary - Philips Semiconductors REVISION HISTORY P89LPC906/907/908 16. REVISION HISTORY 2003 Dec 8 Initial release.
User’s Manual - Preliminary - Philips Semiconductors REVISION HISTORY 2003 Dec 8 P89LPC906/907/908 104
User’s Manual - Preliminary - Philips Semiconductors INDEX P89LPC906/907/908 17.
User’s Manual - Preliminary - Philips Semiconductors INDEX P89LPC906/907/908 block fill 7, 25, 31, 35, 41, 47, 53, 59, 71, 73, 77, 79, 87, 89, 99, 103 hardware reset 7, 25, 31, 35, 41, 47, 53, 59, 71, 73, 77, 79, 87, 89, 99, 103 Dual Data Pointers 87 F FLASH 7, 25, 31, 35, 41, 47, 53, 59, 71, 73, 77, 79, 87, 89, 99, 103 Boot Status 98 Boot Vector 98 features 89 hardware activation of the boot loader 71 power-on reset code execution 71 I IAP programming 89 Interrupts 35 arbitration ranking 31 external in
User’s Manual - Preliminary - Philips Semiconductors INDEX P89LPC906/907/908 FLASH code 89 organization 24 O Oscillator high speed crystal option 25, 26 low speed crystal option 25 medium speed crystal option 25 R-C option 26 watchdog (WDT) option 26 P Pin configuration 7 Port 0 12, 13, 14 Port 3 12 Ports additional features 38 I/O 35 input only configuration 37 open drain output configuration 36 Port 0 analog functions 37 Port 2 in 20-pin package 37 push-pull output configuration 37 quasi-bidirectional
User’s Manual - Preliminary - Philips Semiconductors INDEX P89LPC906/907/908 S SFR AUXR1 87 BRGCON 61 CMPn 73 KBCON 77 KBMASK 78 KBPATN 77 PCON 56 PCONA 57 RSTSRC 72 RTCCON 51 SCON 62 SSTAT 63 TAMOD 42 TCON 43 TMOD 41 TRIM 26, 27, 91 UCFG1 96 WDCON 81 SFRs undefined locations, use of 15 Special Function Registers (SFR) table 15, 18, 21 T Timer/counters 41 mode 0 42 mode 1 42 mode 2 (8-bit auto reload) 42 mode 3 (seperates TL0 & TH0) 43 mode 6 (8-bit PWM) 43 toggle output 45 TRIM (SFR) power-on reset val
User’s Manual - Preliminary - Philips Semiconductors INDEX P89LPC906/907/908 double buffering in 9-bit mode 67 double buffering in different modes 66 framing error 61, 65 mode 0 63 mode 0 (shift register) 59 mode 1 64 mode 1 (8-bit variable baud rate) 59 mode 2 65 mode 2 (9-bit fixed baud rate) 59 mode 3 65 mode 3 (9-bit variable baud rate) 59 multiprocessor communications 68 status register 63 transmit interrupts with double buffering enabled (modes 1, 2 and 3) 66 W Watchdog timer 79 feed sequence 80 t
Philips Semiconductors User’s manual – Preliminary – P89LPC906/907/908 Definitions Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device.
