Specifications

9. Circuit descriptions and List of abbreviationsEN 48
DVP320
9
.2.7 OPERATING DESCRIPTION
The NCP302 and NCP303 series devices consist of a precision voltage detector that drives a time delay generator. Figures 37 and 38
show a timing diagram and a typical application. Initially consider that input voltage Vin is at a nominal level and it is greater than the
voltage detector upper threshold (VDET+). The voltage at Pin 5 and capacitor CD will be at the same level as Vin, and the reset
output (Pin 1) will be in the high state for active low devices, or in the low state for active high devices. If there is a power interruption
and Vin becomes significantly deficient, it will fall below the lower detector threshold (VDET–) and the external time delay capacitor
CD will be immediately discharged by an internal N–channel MOSFET that connects to Pin 5. This sequence of events causes the
Reset output to be in the low state for active low devices, or in the high state for active high devices. After completion of the power
interruption, Vin will again return to its nominal level and become greater than the VDET+. The voltage detector will turn off the
N–channel MOSFET and allow pull-up resistor RD to charge external capacitor CD, thus creating a programmable delay for releasing
the reset signal. When the voltage at Pin 5 exceeds the inverter/buffer threshold, typically 0.675 Vin, the reset output will revert back
to its original state. The voltage detector and inverter/buffer have built–in hysteresis to prevent erratic reset operation.