Specifications

Table Of Contents
Circuit Descriptions, List of Abbreviations, and IC Data Sheets
EN 87DPTV585 AA 9.
9.3.7 Sound Trap Switching
Figure 9-14 Sound trap switching circuit
Composite video is output on pin 10 of 7323 and buffered by
transistor 7411. The signal is then applied to the 5.5 MHz trap,
1406. In the PAL/SECAM mode, the LMN line is Low, switching
transistor 7407 "on", causing the signal to bypass 1407, the 4.5
MHz filter. The video is then buffered by transistor 7322 before
being applied to pin 14 of 7323.
In the NTSC mode, the LMN line goes "high" and transistor
7406 turns "on", switching the 4.5 MHz SAW filter "on".
Transistor 7407 is turned "off".
9.3.8 1fH Component Buffer Amplifiers
Figure 9-15 Component (YPbPr) buffers
The Y signal is buffered by transistors 7800 and 7801. This is
an impedance matching and YPbPr to YUV circuit. This circuit
does not invert the signal. The Pb signal is amplified by 7802
and buffered by 7803. The Pr signal is amplified by 7804 and
buffered by 7805. The Pb and Pr signals are inverted.
9.3.9 Feature Box
Figure 9-16 FBX block diagram
E_15000_079.eps
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E_15000_080.eps
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CLAMP
AGC
PREFILTER
AGC
CLAMP
PREFILTER
AGC
CLAMP
PREFILTER
TIME
BASE
CORRECTION
NOISE
REDUCTION
HISTOGRAM
TRIPLE
DAC
TRIPLE
ANALOG
FILTER
7714
FM1
BUS C
MUX
SYNC
PROCESSING
MICROCONTROLLER CORE
PROGRAM
ROM
7716
EPROM
ADDRESS
DATA
BUS D
7611
PICNIC
12
14
15
SN-DA
SN-CL
1
2
26
27
7718
FALCONIC
SAA4992
18
19
23
25
26
28
29
4
5
Y-PIP+MAIN-IN
U-PIP+MAIN-IN
V-PIP+MAIN-IN
HA50
VA50
SCL-F
SDA-F
SAA4978
1682
6
8
9
A/D
A/D
A/D
DYNAMIC
NOISE
REDUCTION
7717
FM2
FM3
7719
DE-INTERLACER
MP
MP
MOTION
ESTIMATOR
UP-
CONVERSION
VERT
PEAK
C
B
D
E
F
G
MF
TO
EAGLE
TO EAGLE
E_15000_084.eps
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16b
16b
16b
16b
16b
16b
16b
NOT
USED