Data Sheet

AV6302 Datasheet (Preliminary) revision 0.3
CONTENTS SUBJECT TO CHANGE WITHOUT NOTICE 7 AVNERA PROPRIETARY & CONFIDENTIAL | PROVIDED UNDER NDA
1.2 Functional Diagram
PWR
V3P6
18
GPIO
DSCP,DSCN
SPI, I2C
GPIO (Buttons, LEDs)
I2S
Audio
CODEC
MICN
MICP
VDDMIC
DAC_GND
HPR
VCM
HPL
BGOUT VDDXO IREF
PHY EQ
Digital Block
RESETN
MCU
XLATP XTALN
GPIO
SRC
RFP
RFN
ROM
RAM
OTP
3.6V
LDO
VBGSUP REF
DIG
Regs
3.3V
REG
Pwr
SW
XTAL
VDD1P8 VDDDIG VDDIO
RF/IF
Transceiver
Batt
Chgr
PWR
pin
CFN CFP VBAT VDC VIN
3
ADC
ADC
USB
DP
DM
Figure 1-2 AV6302 Block Diagram
1.3 Audio Signal Routing Diagram
HPL
DAC
DAC
HPR
DAC
MCLK
WCLK
BCLK
I2S
CLK
GEN
I2S MONO IN
I2S MONO OUT
I2S
STEREO OUT
ADC
MIC
TONE
GENERATOR
AUDIO
EQ
AUDIO
PROC
ALC
Auto
Level
Control
MIC
EQ
RADIO
Mic
Gain
Mix back
Chat Mixback Gain
Gain Pre-Amp
HP-Amp
Gain
Gain
Gain
Tone
NG
Threshold
Noise
Gate
Threshold
Figure 1-3 AV6302 Audio Routing Diagram