USB

4
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High Speed Interface Standards
INDEX
DDR4 is the next generation memory standard targeted for enterprise computing.
The standard enables higher capacity DIMM’s (128 GB), doubles the data rate (3200
MT/s) and operates at lower voltage (1.2V) compared to the previous generation.
JEDEC.org
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Interface Verification and Debug
Design Challenges
n Signal Access for debug and validation
n Read / Write separation for analysis
n De-embedding to remove the effects of the interposer and probe, and to
view signals @ the memory controller
n Triggering on error conditions such as data-dependent errors
n Protocol error checking
Tektronix Solution
n Interposer solutions enable signal access for both electrical and protocol validation
n DDRA automatically separates Reads / Writes then performs the relevant measurements
n SDLA enables generation of de-embed filters
n Visual Trigger can be used to define complex conditions, enables capturing conditions of interest
n The TLA7000 Logic Analyzer and the MCA5000 Memory compliance analyzers can be used to
perform Logic validation and protocol compliance
DDR4
|
High Speed Interface Standards
Tektronix Visual Trigger can accurately capture
fast reads & writes on DDR signaling
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