USB

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High Speed Interface Standards
INDEX
PCI Express is a high-speed serial computer expansion
bus standard designed to replace the older PCI,
PCI-X, and AGP bus standards. PCIe has a variety of
improvements over the older standards, including higher
maximum system bus throughput, lower pin count and
smaller physical footprint. PCI Express recently released
its 3rd generation specification to operate @ 8 Gb/s and
work is underway to define the next or 4th generation
specification targeted to operate @ 16 Gb/s.
PCISIG.com
Design Challenges
n Validating all bus speeds and presets per lane, for example, 8 Gb/s
requires testing at 5 Gb/s and 2.5Gb/s with 11 de-emphasis presets
on up to 16 lanes
n Placing the device into loopback to perform stressed receiver eye
measurements
n Tracking link training sequences to validate speed and link width
negotiation between transmitter and receiver
Tektronix Solution
n TekExpress for PCI Express automation software for in-depth compliance testing
n DPOJET and SDLA advanced link analysis for host and device system modeling
n BERTScope PCIe automation simplifies calibration and receiver tolerance testing
n TLA Logic Protocol Analyzer to trace and validate link layer behavior
PCI Express
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High Speed Interface Standards
Observe PCI express link layer interactions using
the oscilloscope’s bus decode capability.
Observe receiver bit error map for all of the PCI
Express’ preset levels to assess BER margin.
Get our Primer on PCI Express
®
Transmitter
PLL Testing – A Comparison of Methods
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