USB

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High Speed Interface Standards
Next generation interface standards are pushing the limits of today’s compliance
and debug tools. Electrical validation of PCIe 4.0 16 Gb/s, SAS 12 Gb/s,
SuperSpeed USB 10Gb/s, and DDR4 3200 MT/s and other high-speed bus
technologies require even more complex test considerations than before.
Transmitter performance, for example, is best evaluated with new analysis
techniques that can accurately identify jitter & noise from sources such as crosstalk
or other multi-lane noise coupling. With a closed eye architecture, commonly found
in long channel designs, physical layer testing requires advanced techniques such
as channel de-embedding and end-to-end link simulation with reference receivers.
Design Challenges
n Smaller device geometries coupled with multi-layer PCBs incorporating buried via limit signal access
n Bus behavior with new power-saving schemes including frequency switching and clock gating
n Initiating test mode in-band through the channel, i.e., talk to the receiver’s link training and status
state machine
n Validating new signal encoding and equalization capability found in high-speed signaling interfaces
n Increasing complexity and quantity for electrical validation – so many tests, so little time!
Standards
a. PCI Express
b. DDR4
c. USB
d. SAS/SATA
Introduction
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High Speed Interface Standards
Tektronix automation software simplifies the complexities of
validating next-generation high-speed interfaces.