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Intel Order Number C11343-001

Intel

SHG2 DP Server Board

Technical Product Specification

Intel Order Number C11343-001

Revision 1.0

June 2002

Enterprise Platforms and Services Division

Summary of content (97 pages)

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Intel® SHG2 DP Server Board Technical Product Specification Intel Order Number C11343-001 Revision 1.
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Revision History Intel® SHG2 DP Server Board Technical Product Specification Revision History Date 06/05/02 Revision Number 1.0 Modifications Final draft. Disclaimers Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppels or otherwise, to any intellectual property rights is granted by this document.
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Intel® SHG2 DP Server Board Technical Product Specification Table of Contents Table of Contents 1. Introduction............................................................................................................ 1 1.1 SHG2 Architecture Overview............................................................................... 2 1.2 Document Structure and Outline ......................................................................... 4 2. Processor and Chipset ....................................
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Table of Contents 2.5 Intel® SHG2 DP Server Board Technical Product Specification Chipset Support Components ........................................................................... 14 2.5.1 Legacy I/O (Super I/O) National* PC87417VLA........................................... 14 3. Baseboard PCI I/O Subsystem ........................................................................... 18 3.1 Overview...................................................................................................
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Intel® SHG2 DP Server Board Technical Product Specification Table of Contents 5.2.1 Power-up Reset ........................................................................................... 31 5.2.2 Hard Reset................................................................................................... 32 5.2.3 Soft Reset .................................................................................................... 32 5.3 Intelligent Platform Management Buses............................
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Table of Contents Intel® SHG2 DP Server Board Technical Product Specification 7. Jumpers ............................................................................................................... 48 7.1 Hardware Configuration..................................................................................... 48 8. Connections......................................................................................................... 50 8.1 Connector Locations .........................................
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Intel® SHG2 DP Server Board Technical Product Specification Table of Contents 9.2 Airflow Specification for CIOB-X2 and CMIC-LE ............................................... 73 9.3 Electrical Specifications..................................................................................... 73 9.3.1 Power Consumption..................................................................................... 73 9.3.2 Power Supply Specifications.............................................................
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List of Figures Intel® SHG2 DP Server Board Technical Product Specification List of Figures Figure 1. Intel® SHG2 Server Board ............................................................................... 1 Figure 2. SHG2 Server Board Placement Diagram ........................................................ 2 Figure 3. SHG2 Memory Bank Layout.......................................................................... 10 Figure 4. SHG2 Interrupt Routing (PIC Mode)..........................................
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Intel® SHG2 DP Server Board Technical Product Specification List of Tables List of Tables Table 1. Memory DIMM Pairs....................................................................................... 10 Table 2. CSB5 GPIO Usage Table............................................................................... 13 Table 3. Serial Port Connector Pinout .......................................................................... 14 Table 4. Parallel Port Connector Pinout ..................................
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List of Tables Intel® SHG2 DP Server Board Technical Product Specification Table 31. Recovery BIOS POST Codes........................................................................ 44 Table 32. POST Error Messages and Codes ................................................................ 45 Table 33. SHG2 Configuration Jumper Options ............................................................ 49 Table 34. SHG2 Baseboard Connectors .......................................................................
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Intel® SHG2 DP Server Board Technical Product Specification List of Tables Table 64. SHG2 Ripple and Noise Specification ........................................................... 74 Table 65. Voltage Timing Parameters ........................................................................... 74 Table 66. Turn On/Off Timing........................................................................................ 75 Table 67. Transient Load Requirements .....................................................
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List of Tables Intel® SHG2 DP Server Board Technical Product Specification < This page intentionally left blank. > xii Intel Order Number C11343-001 Revision 1.
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Intel® SHG2 DP Server Board Technical Product Specification 1. Introduction Introduction ® This chapter provides an architectural overview of the Intel SHG2 Server Board, including functional blocks and the electrical relationships. Figure 1 shows the functional blocks of the SHG2 baseboard.
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Introduction Intel® SHG2 DP Server Board Technical Product Specification +12V CPU Pwr 1 23 4 USB 1 1 8 8 5 2 1 C 6 B A 2 1 5 3 6 36 DIMM 3B Serial A Proc 1 DIMM 3A DIMM 2B 1 1 5 50 5 9 Parallel Aux Sig 1 KB/MS Main Pwr DIMM 2A DIMM 1B DIMM 1A 2 1 1 16 1 1 4 1 Video NIC2 (Gbit) Proc 2 82 71 NIC1 (10/100) Video 7 CMIC-LE Gbit Serial B PCIX-1 (64/100) Floppy USB BMC PCIX-2 (64/100) 2 1 1 Sec IDE 4 2 0 0 2 1 1 Prim IDE 4 2 0 0 Front Panel PCI-3 (32/33) 10/100 NIC SCSI C
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Intel® SHG2 DP Server Board Technical Product Specification Introduction Server management and monitoring hardware are also included. These features, and the others listed below, make this one of the most highly integrated server boards in this class. SHG2 supports two interleaved memory channels at 100 MHz, each utilizing the rising edge and falling edge of the clock cycle for 200MT/s per channel (also known as “double pumped”) for a combined throughput of 400 MT/s.
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Introduction Intel® SHG2 DP Server Board Technical Product Specification Super I/O* controller chip providing all PC-compatible I/O (floppy, parallel, serial, keyboard, mouse). - Sahalee Baseboard Management Controller (BMC) providing monitoring, alerting, and logging of critical system information obtained from embedded sensors on baseboard. Four Universal Serial Bus (USB) ports.
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Intel® SHG2 DP Server Board Technical Product Specification Chapter 11 Revision 1.
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Processor and Chipset Intel® SHG2 DP Server Board Technical Product Specification 2. Processor and Chipset 2.1 Overview The Intel SHG2 Server Board consists of one to two identical Intel Xeon processors, the Grand Champion LE chipset, and support circuitry. The baseboard houses two surface mount zero insertion force (ZIF) processor sockets and one embedded processor voltage regulator module (VRMs) to power one or both processors.
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Intel® SHG2 DP Server Board Technical Product Specification Processor and Chipset be applied to the system unless primary slot is populated with a processor, unless used in fault resilient booting (FRB) mode (details in Section 5). When using two processors, notice that the processor pins are physically 180 degrees out-ofphase. Improper processor installation may permanently damage processor pins. 2.2.
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Processor and Chipset 2.2.4 Intel® SHG2 DP Server Board Technical Product Specification ServerWorks* Grand Champion* LE Chipset The CMIC-LE, CIOB-X2, and CSB5 chips provide the pathway between processor and I/O systems. The CMIC-LE is responsible for accepting access requests from the host (processor) bus, and directing all I/O accesses to one of the PCI buses or legacy I/O locations.
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Intel® SHG2 DP Server Board Technical Product Specification 2.3 Processor and Chipset Memory Subsystem Features provided in the SHG2 server board memory subsystem include the following: • • • • • • • • • • Six DIMM sockets, supporting three pairs of PC1600 (DDR200), upward compatible with PC2100 (DDR266) DIMMs. Memory can be implemented with either single-sided (one row) or double-sided (two row) DIMMs. Minimum memory capacity of 256 MB (2 x 128MB DIMMs).
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Processor and Chipset • • • • Intel® SHG2 DP Server Board Technical Product Specification DIMM capacity (in pairs): 128 MB, 256 MB, 512 MB, 1 GB and 2 GB Serial PD: JEDEC Rev 2.0 Voltage Options: 2.5 V (VDD/VDDQ) DIMMs must be populated in pairs for a x144 wide memory data path Table 1. Memory DIMM Pairs Memory DIMM DIMM PAIR Row DIMM 1A, DIMM 1B 1 1, 2 DIMM 2A, DIMM 2B 2 3, 4 DIMM 3A, DIMM 3B 3 5, 6 DIMM Pair 3A/B DIMM Pair 2A/B DIMM Pair 1A/B Figure 3.
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Intel® SHG2 DP Server Board Technical Product Specification 2.3.3 Processor and Chipset CIOB-X2 The Champion I/O Bridge (CIOB-X2) provides an integrated I/O bridge that provides a highperformance data flow path between the IMB and the 64-bit I/O subsystem. This subsystem supports 2 peer 64-bit PCI (-X) segments. Having two PCI (-X) interfaces, the CIOB-X2 is able to provide large and efficient I/O configurations.
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Processor and Chipset • • • • • Intel® SHG2 DP Server Board Technical Product Specification Four port USB interface PCI-compatible timer/counter and DMA controllers APIC and legacy 8259 interrupt controller Power management General purpose I/O The following are descriptions of how each supported feature is implemented in SHG2. 2.4.1 PCI Interface The CSB5 fully implements a 32-bit PCI master/slave interface, in accordance with the PCI Local Bus Specification, Revision 2.2.
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Intel® SHG2 DP Server Board Technical Product Specification 2.4.6 Processor and Chipset Power Management One of the embedded functions of CSB5 is a power management controller. The SHG2 server board uses this to implement ACPI-compliant power management features. The SHG2 supports four sleep states: S0, S1, S4, and S5. 2.4.7 General Purpose Input and Output Pins The CSB5 provides a number of general-purpose input (GPI) and general-purpose output (GPO) pins.
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Processor and Chipset 2.5 2.5.1 Intel® SHG2 DP Server Board Technical Product Specification Chipset Support Components Legacy I/O (Super I/O) National* PC87417VLA The National* PC87417VLA is integrated on the SHG2 baseboard as the Super I/O controller (SIO). The SIO is a Plug and Play-compatible device with ACPI-compliant controller/extender.
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Intel® SHG2 DP Server Board Technical Product Specification 2.5.1.2 Processor and Chipset Parallel Port The SHG2 baseboard provides a 25-pin parallel port connector. The SIO provides an IEEE 1284-compliant, 25-pin bi-directional parallel port. BIOS programming of the SIO registers enables the parallel port and determines the port address and interrupt. When disabled, the interrupt is available to add in adapters. Parallel port pinouts are shown in Table 4. Table 4. Parallel Port Connector Pinout Pin 2.
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Processor and Chipset Pin 12 Intel® SHG2 DP Server Board Technical Product Specification Name FD_DR1_L 2.5.1.4 Pin 24 Name FD_WGATE_L Pin Name Keyboard and Mouse Connectors The PS/2-compatible keyboard and mouse connectors are mounted within a single stacked housing. The mouse connector is stacked over the keyboard connector. External to the board, they appear as two connectors. The keyboard controller is functionally compatible with the 8042AH and PC87911.
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Intel® SHG2 DP Server Board Technical Product Specification Processor and Chipset management events, the BMC, or the front panel. This circuitry is powered from stand-by voltage, which is present anytime the system is plugged into an AC outlet. Revision 1.
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Baseboard PCI I/O Subsystem Intel® SHG2 DP Server Board Technical Product Specification 3. Baseboard PCI I/O Subsystem 3.1 Overview The I/O buses for the Intel SHG2 server board are both PCI-X and PCI, with one PCI and two PCI-X bus segments or peers. All the PCI (-X) buses comply with the PCI Local Bus Specification, Revision 2.2 and PCI-X Specification, Revision 1.0a.
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Intel® SHG2 DP Server Board Technical Product Specification 3.2.2 Baseboard PCI I/O Subsystem 64/100MHz PCI-X Arbitration A 64/100MHz segment supports three PCI (-X) masters: slots PCIX-1 (64/100), PCIX-2 (64/100), and 82544GC Gigabit Ethernet Controller. All PCI (-X) masters must arbitrate for PCI (-X) access, using resources supplied by the CIOB-X2. The host bridge PCI (-X) interface (CIOB-X2) arbitration lines REQx* and GNTx* are a special case in that they are internal to the host bridge.
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Baseboard PCI I/O Subsystem Intel® SHG2 DP Server Board Technical Product Specification using resources supplied by the CIOB-X2. The CIOB-X2 interface arbitration connections are internal to the device. Table 13 defines the external arbitration connections: Table 13. 64/133 MHz Segment Arbitration Connections 3.3.
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Intel® SHG2 DP Server Board Technical Product Specification • Baseboard PCI I/O Subsystem PCI 82550PM Network Interface Controller. 3.5.1 Device IDs (IDSEL) Each device under the PCI host bridge has its IDSEL signal connected to one bit of AD[31::16], which acts as a chip select on the PCI bus segment in configuration cycles. This determines a unique PCI device ID value for use in configuration cycles.
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Baseboard PCI I/O Subsystem • • • • • Intel® SHG2 DP Server Board Technical Product Specification Integrated IEEE 802.3 10Base-T and 100Base-TX compatible PHY IEEE 820.3u auto-negotiation support Chained memory structure similar to the 82559, 82558, 82557, and 82596 Full duplex support at both 10 Mbps and 100 Mbps operation Low power +3.3 V device 3.5.3.1 NIC Connector and Status LEDs The 82550PM drives status LEDs on the NIC to indicate link/activity on the LAN and operational speed, 10- or 100-Mbps.
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Intel® SHG2 DP Server Board Technical Product Specification Baseboard PCI I/O Subsystem 640x480 60,72,75,90,100 Supported Supported Supported Supported 800x600 60,70,75,90,100 Supported Supported Supported Supported 1024x768 60,72,75,90,100 Supported Supported Supported Supported 1280x1024 43,60,70,72 Supported Supported – – 1600x1200 60,66,76,85 Supported – – – 3D Mode Refresh Rate (Hz) SHG2 3D Video Mode Support with Z Buffer Disabled 640x480 60,72,75,90,100 Supported
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Baseboard PCI I/O Subsystem Intel® SHG2 DP Server Board Technical Product Specification CSB5 SCAN IRQ IRQ 0 IRQ 1 Cascade IRQ 2 Serial Port2 Connection IRQ 3 Serial Port1 IRQ 4 ESMINT IRQ 5 FDD IRQ 6 Parallel Port IRQ 7 RTC IRQ #8 IRQ 9 ESMINT IRQ 10 ESMINT IRQ 11 Mouse IRQ 12 IRQ 13 IRQ 14 IRQ 15 Timer Super I/O Keyboard FERR# P_IDE S_IDE SCSI i INTA# j SCSI i INTB# j st 1 LAN 82550 nd 2 LAN 82544 GA Slot3 intA Slot4 intA Slot6 intA Slot5 intA Slot2 intA Slot1 intA Slot1intD,Slot2intC,Slot3intB, Slot
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Intel® SHG2 DP Server Board Technical Product Specification Baseboard PCI I/O Subsystem Timer KB (Cascade Connection) SIO2 SIO1 ESMINT Floppy Parallel RTC ESMINT ESMINT Mouse CoprocessorErr P_IDE S_IDE SCSI Port A SCSI Port B LAN 1 82550 LAN 2 82544 VGA SLOT 01 02 03 04 05 06 Slot03 INTA Slot04 INTA Slot06 INTA Slot05 INTA Slot02 INTA Slot01 INTA B C SCI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 PIRQ0 PIRQ1 PIRQ2 PIRQ3 PIRQ4 PIRQ5 PIRQ6 PIRQ7 PIRQ8 PIR
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Baseboard PCI I/O Subsystem Intel® SHG2 DP Server Board Technical Product Specification The XIOAPIC logic inside CSB5 has 48 entries of which 16 entries are for legacy interrupts 015, and 32 entries are for PCI interrupts. The 48 entries are implemented as three 16-entry XIOAPIC units. The basic building block for the XIOAPIC is a 16-entry IOAPIC. The SHG2 baseboard supports mapping (redirection) of any of the 32 PCI interrupt sources to legacy interrupts.
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Intel® SHG2 DP Server Board Technical Product Specification 4. Clock Generation and Distribution Clock Generation and Distribution All buses on the Intel SHG2 server board operate using synchronous clocks. Clock synthesizer/driver circuitry on the baseboard generates clock frequencies and voltage levels as required, including the following: • • • 100 MHz at 2.5 V logic levels - for CPU1 and CPU2, the CMIC-LE, memory buffer, and the ITP port. 48 MHz at 3.3V logic levels – for CSB5 and Super I/O. 33.
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Clock Generation and Distribution HOST CLOCK: 100 MHz 100 MHz 100 MHz 100 MHz HOST CLOCK BUFFER 100 MHz 14 MHz 48 MHz 48 MHz 33 MHz Intel® SHG2 DP Server Board Technical Product Specification PCI CLOCK: 33 MHz CPU1 33 MHz CPU2 33 MHz CMIC-LE CSB5 / VGA 33 MHz PCI CLOCK BUFFER SIO 33 MHz 33 MHz 33 MHz CSB5 / SIO 33 MHz PCI CLK BUF 33 MHz 14.
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Intel® SHG2 DP Server Board Technical Product Specification 5. Server Management Server Management Speaker Network Activity LEDs Power LED System Indentify LED Drive Activity/Fault LED Fault Status LED Power Button Reset Button System Identify Button Sleep Button Front Panel NMI Switch Chassis Intrusion The SHG2 server management features are implemented using the Sahalee BMC chip.
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Server Management 5.1 Intel® SHG2 DP Server Board Technical Product Specification Sahalee Baseboard Management Controller The Sahalee BMC contains a 32-bit RISC processor core and associated peripherals used to monitor the system for critical events. The Sahalee BMC, packaged in a 156-pin BGA, monitors all power supplies, including those generated by the external power supplies, and those regulated locally on the server board.
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Intel® SHG2 DP Server Board Technical Product Specification Type Server Management Pin ADM1026 Signal Name External Signal Name / Function active low output with a 200 ms minimum pulse width. This is asserted whenever 3.3VSTBY is below the reset threshold. It remains asserted for approx. 200ms after 3.3VSTBY rises above the reset threshold.
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Server Management Intel® SHG2 DP Server Board Technical Product Specification After the system is turned on, the power supply will assert the PWRGD+00 signal after all voltage levels in the system have reached valid levels. The BMC receives PWRGD+00 and after approximately 500 ms, asserts RST_P6_PWRGOOD, which indicates to the processors and CSB5 that the power is stable. Upon RST_P6_PWRGOOD assertion, the CSB5 will toggle PCI reset. 5.2.
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Intel® SHG2 DP Server Board Technical Product Specification 5.3 Server Management Intelligent Platform Management Buses Management controllers (and sensors) communicate on the I2C-based IPMB. A bit protocol, defined by the I2C Bus Specification, and a byte-level protocol, defined by the Intelligent Platform Management Bus Communications Protocol Specification, provide an independent 2 interconnect for all devices operating on this I C bus. The IPMB extends throughout the server board and system chassis.
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Server Management Intel® SHG2 DP Server Board Technical Product Specification 2 Table 23: Private I C* Bus 3 Devices Function Voltage Aux Power Connector 3 VSB Address Notes 0xBC, 0xAC 0xB0, 0xA0 0xB1, 0xA1 0xB2, 0xA2 ADM1026 3 VSB 0x58 2 Table 24: Private I C* Bus 4 Devices Function Voltage Address CPU1 3 VSB 0xC0, 0x30 CPU2 3 VSB 0xC1, 0x31 PC87417 SIO 3 VSB 0x60 Notes 2 Table 25: Private I C* Bus 5 Devices Function NIC1 (82550PM) 34 Voltage 3 VSB Address Notes 0x84 Intel
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Intel® SHG2 DP Server Board Technical Product Specification 6. Error Reporting and Handling Error Reporting and Handling This section defines how errors are handled by the system BIOS on the Intel SHG2 server board. Also discussed is the role of BIOS in error handling, and the interaction between the BIOS, platform hardware, and server management firmware with regard to error handling. In addition, error-logging techniques are described, and beep codes for errors are defined. 6.
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Error Reporting and Handling Intel® SHG2 DP Server Board Technical Product Specification The BIOS logs the following SEL entries: Table 26.
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Intel® SHG2 DP Server Board Technical Product Specification Event Trigger Class Event Data Event Data 2 7:4 3:0 unspecified. 6.3 Error Reporting and Handling Optional offset from ‘Severity’ Event Trigger. (0Fh if unspecified). Optional offset from Event Trigger for previous discrete event state. 0Fh if System Management Interrupt (SMI) Handler The SMI handler is used to handle and log system level events that are not visible to the server management firmware.
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Error Reporting and Handling Intel® SHG2 DP Server Board Technical Product Specification first OEM data byte is 0. The BIOS depends upon the BMC to log the watchdog timer reset event. 6.3.6 Boot Event The BIOS downloads the system date and time to the BMC during POST and logs a boot event. This does not indicate an error, and software that parses the event log should treat it as such. 6.3.7 Chip Set Failure The BIOS detects the chip set (CMIC-LE and CIOB-X2) failure and logs this event.
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Intel® SHG2 DP Server Board Technical Product Specification • Error Reporting and Handling FRB level 3 is intended to recover from a watchdog timeout on hard reset or power-up. The Sahalee BMC provides hardware functionality for this level of FRB. 6.4.3.1 FRB-1 In a multiprocessor system, the BIOS registers the application processors in the multiprocessor (MP) table and the ACPI APIC tables.
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Error Reporting and Handling 6.5.1 Intel® SHG2 DP Server Board Technical Product Specification Alert Standard Forum (ASF) Progress Codes The BIOS utilizes ASF Progress Events as described in the ASF Specification, Revision 1.0a from the Distributed Management Task Force (DMTF). BIOS supported events are shown in Table 28. Table 28. Event Request Message Event Data Field Contents 6.5.2 ASF Code 01h Description Memory initialization. Comment At beginning of ECC initialization or memory test.
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Intel® SHG2 DP Server Board Technical Product Specification Error Reporting and Handling code of 1-3-1-1 is generated. The dash between the numbers defines an audible pause that delimits the sequence. POST codes will occur prior to the video display being initialized. To assist in determining the fault, a unique beep-code is derived from these checkpoints as follows: 1. The 8-bit test point is broken down to four 2-bit groups. 2. Each group is made one-based (1 through 4). 3.
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Error Reporting and Handling CP 34 Beeps Reason Test CMOS 35 RAM Initialize alternate chipset registers 36 Warm start shut down 37 Reinitialize the chipset 38 Shadow system BIOS ROM 39 Reinitialize the cache 3A Auto-size cache 3C Configure advanced chipset registers 3D Load alternate registers with CMOS values 40 Set Initial Processor speed new 42 Initialize interrupt vectors 44 Initialize BIOS interrupts 46 2-1-2-3 Check ROM copyright notice 47 Initialize manager for PCI Optio
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Intel® SHG2 DP Server Board Technical Product Specification CP 7C Beeps Reason Set up hardware interrupt vectors 7D Intelligent system monitoring 7E Test coprocessor if present 82 Detect and install external RS232 ports 85 Initialize PC-compatible PnP ISA devices 86 Re-initialize on board I/O ports 88 Initialize BIOS Data Area 8A Initialize Extended BIOS Data Area 8C Initialize floppy controller 90 Initialize hard disk controller 91 Initialize local bus hard disk controller 92 Jump
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Error Reporting and Handling CP D4 Intel® SHG2 DP Server Board Technical Product Specification Beeps Reason Pending interrupt error D6 Initialize option ROM error D8 Shutdown error DA Extended Block Move DC Shutdown 10 error Table 31.
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Intel® SHG2 DP Server Board Technical Product Specification Error Reporting and Handling Table 32.
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Error Reporting and Handling Intel® SHG2 DP Server Board Technical Product Specification Code 0B51: Error Message Processor #2 with error taken offline Failure Description Failed Processor 2 because an error was detected. 0B52 Processor #3 with error taken off line Failed Processor 3 because an error was detected. 0B53 0B5F: Processor #4 with error taken off line Forced to use CPU with error Failed Processor 4 because an error was detected.
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Intel® SHG2 DP Server Board Technical Product Specification Error Reporting and Handling the LCD Display Control command), a BIOS message will override a software message written to the BIOS area. Normally, the BIOS will use the BIOS LCD Message command that will cause the BMC to display a BMC-stored message in the BIOS message area (first line) of the LCD. 6.5.4.
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Jumpers Intel® SHG2 DP Server Board Technical Product Specification 7. Jumpers 7.1 Hardware Configuration This section describes jumper options on the baseboard. The SHG2 server board has 10 jumpers to control various configuration options. CN14 CN27 CN32 CN43 CN47 CN48 CN58 CN53 CN57 CN56 Figure 9. Jumper Location 48 Intel Order Number C11343-001 Revision 1.
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Intel® SHG2 DP Server Board Technical Product Specification Jumpers Table 33.
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Connections Intel® SHG2 DP Server Board Technical Product Specification 8. Connections 8.1 Connector Locations The diagram below identifies all the connector locations M L K 1 J N I H G F E D C A B Figure 10. SHG2 Baseboard Connector Identification and Locations Table 34.
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Intel® SHG2 DP Server Board Technical Product Specification 8.
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Connections Intel® SHG2 DP Server Board Technical Product Specification 2 Table 37. Power Connector for I C* Bus CN4 [Key-L] Pin 8.3 Signal Pin Signal 1 SM3_CLK+PWBP 4 RETURN_S 2 SM3_DATA 5 +3.3V 3 PS_ALERT SCSI Connectors CN54 & CN55 [Key-A & B] The SHG2 baseboard provides two SCSI connectors. The two connectors have the same pinout. Table 38 details the pin-out of the SCSI connectors. Table 38.
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Intel® SHG2 DP Server Board Technical Product Specification Connector Contact Number Signal Name Connector Contact Number Signal Name 22 GROUND 45 -DT(5) 23 +BSY 46 -DT(6) 8.4 Connections Connector Contact Number 68 Signal Name -DT(11) Floppy Connector CN31 [Key-H] Table 39 details the pin-out of the 34-pin Legacy floppy connector. Table 39. Legacy 34-pin Floppy Connector Pin-out CN31 [Key-H] Pin Revision 1.
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Connections 8.5 Intel® SHG2 DP Server Board Technical Product Specification IDE Connectors CN38 & CN34 [Key-F & G] Table 40 lists the pinout and signal names for the IDE connectors. Table 40.
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Intel® SHG2 DP Server Board Technical Product Specification 8.6 Connections Front Panel Interface CN37 [Key-E] A 34-pin header is provided that attaches to the system front panel. The header contains reset, NMI, sleep, and power control buttons, and LED indicators. Table 41 summarizes the front panel signal pins, including the pin number, signal mnemonic, and a brief description. Table 41.
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Connections 8.7 Intel® SHG2 DP Server Board Technical Product Specification Processor Connector CPU1 & CPU2 [Key-J & I] The Intel Xeon Processor connector pin-out, CPU1 & CPU2 [Key-J & I], lists the pins of the processor connector and the signal name that appears on the SHG2 baseboard schematic diagram. ® Table 42.
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Intel® SHG2 DP Server Board Technical Product Specification Pin † Signal Pin Signal Connections Pin Signal Pin Signal B1 Reserved F28 VSS R4 VSS AB3 Reserved B2 VSS F29 VCC R5 VCC AB4 VCCA B3 VID4 F30 No Connect R6 VSS AB5 VSS B4 No Connect F31 No Connect R7 VCC AB6 D63# B5 OTDEN G1 No Connect R8 VSS AB7 PWRGOOD B6 VCC G2 VCC R9 VCC AB8 VCC B7 A31# G3 VSS R23 VCC AB9 DB13# B8 A27# G4 VCC R24 VSS AB10 D55# B9 VSS G5 VSS R25 VCC A
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Connections Pin † Intel® SHG2 DP Server Board Technical Product Specification Signal Pin Signal Pin Signal Pin Signal C12 A23# J3 VSS U23 VCC AC14 D50# C13 VSS J4 VCC U24 VSS AC15 DP2# C14 A16# J5 VSS U25 VCC AC16 VCC C15 A15# J6 VCC U26 VSS AC17 D34# C16 VCC J7 VSS U27 VCC AC18 DP0# C17 A8# J8 VCC U28 VSS AC19 VSS C18 A6# J9 VSS U29 VCC AC20 D25# C19 VSS J23 VSS U30 No Connect AC21 D26# C20 REQ3# J24 VCC U31 No Connect AC22 VC
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Intel® SHG2 DP Server Board Technical Product Specification Pin † Signal Pin Signal Connections Pin Signal Pin Signal D23 BPRI# L9 VSS W29 VCC AD25 D18# D24 VCC L23 VSS W30 No Connect AD26 VCC D25 Reserved L24 VCC W31 No Connect AD27 D4# D26 VSSSENSE L25 VSS Y1 No Connect AD28 SM_ALERT# D27 VSS L26 VCC Y2 VCC AD29 SM_WP D28 VSS L27 VSS Y3 Reserved AD30 No Connect D29 VCC L28 VCC Y4 BCLK0 AD31 No Connect D30 No Connect L29 VSS Y5 VSS AE2
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Connections 8.8 8.8.1 Intel® SHG2 DP Server Board Technical Product Specification System Management Interfaces ICMB Connector CN21 [Key-N] The external Intelligent Chassis Management Bus (ICMB) provides external access to IMB devices that are within the chassis. This makes it possible to externally access chassis management functions, alert logs, post-mortem data, etc. It also provides a mechanism for chassis power control.
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Intel® SHG2 DP Server Board Technical Product Specification 8.9 Connections Baseboard Fan Connectors (FAN1 through FAN8) SHG2 provides eight 3-pin, shrouded, and keyed fan connectors. Each fan can be equipped with a sensor that indicates whether the fan is operating. Two fan connectors are for processor cooling fans, two fan connectors are for back of chassis, and four connectors on the baseboard attach to chassis fans equipped with a sensor that indicates whether the fan is operating.
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Connections Intel® SHG2 DP Server Board Technical Product Specification FAN 1 FAN 5 FAN 1 to CN23 CN 1 FAN 5 to CN28 Core Cooling Zone FAN 2 FAN 3 CN 18 CN 22 FAN 3 to CN41 CN 23 FAN 4 FAN 2 to CN22 CN 28 CN 36 FAN 4 to CN46 Fan headers I/O Cooling Zone CN 41 CN 46 Figure 12. SHG2 System Redundant Cooling Fan Support 62 Intel Order Number C11343-001 Revision 1.
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Intel® SHG2 DP Server Board Technical Product Specification Connections Table 45.
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Connections Intel® SHG2 DP Server Board Technical Product Specification 8.10 Standard I/O Panel Connectors Figure 13 shows a graphical representation with identification of the physical connections at the I/O panel (also referred to as the back panel). Note: The orientation of the RJ45 connectors for NIC and NIC2 are inverted with respect to one another (tab-up and tab-down). The intial production release boards will ship with connectors oriented in this fashion.
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Intel® SHG2 DP Server Board Technical Product Specification Connections Table 47. I/O Panel Connectors Key 8.10.
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Connections Intel® SHG2 DP Server Board Technical Product Specification Pin 8 8.10.2 Name Internal USB Connector USBP3_GND 9 Key 10 Reserved for future use Mouse and Keyboard Ports [Key-D & E] Two identical PS/2 compatible ports share a common stacked housing. The top PS/2 connector is labeled "mouse" and the bottom connector is labeled "keyboard," although the SHG2 server board will support swapping these connections. Table 50.
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Intel® SHG2 DP Server Board Technical Product Specification Connections The COM2 serial port can be used either as an emergency management port (EMP) or as a normal serial port. As an EMP, COM2 is used as a communication path by the Server Management RS-232 connection to the BMC. This port can provide a level of emergency management through an external modem. The RS-232 connection can be monitored by the BMC when the system is in a powered down (standby) state.
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Connections 8.10.5 Intel® SHG2 DP Server Board Technical Product Specification Video Port The video port interface is a standard VGA-compatible 15-pin connector. An ATI Rage XL video controller, with 8 MB of onboard video SDRAM, supplies on-board video. Table 54.
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Intel® SHG2 DP Server Board Technical Product Specification Connections indicates network connection when illuminated, and TX/RX activity when blinking. When the SPEED LED is OFF, it indicates network connection at 10Mbps; a green LED indicates 100Mbps operation when illuminated. Table 56.
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Connections Intel® SHG2 DP Server Board Technical Product Specification 8.11 Connector Manufacturers and Part Numbers Table 58 shows the quantity and manufacturers’ part numbers for connectors on the baseboard. Item numbers reference the circled numbers on the mechanical drawing. Refer to manufacturers’ documentation for more information on connector mechanical specifications. Table 58.
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Intel® SHG2 DP Server Board Technical Product Specification Interface Definition Primary and Secondary ATA Description / Manufacturer Connections Item Number Foxconn Electronics, Inc. HL13178 Tyco Electronics Corporation 111685-7 Molex Connector Corporation 0872563456 CONN, HDR, 2 X 20, PLG, VT, 0.1, 062ST, KP 20 1 Foxconn Electronics, Inc. HL09207-D2 Tyco Electronics Corporation 111971-8 Foxconn Electronics, Inc.
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General Specifications 9. Intel® SHG2 DP Server Board Technical Product Specification General Specifications This chapter specifies the operational parameters and physical characteristics for the Intel SHG2 server board. This is a board-level specification only. System specifications are beyond the scope of this document. 9.
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Intel® SHG2 DP Server Board Technical Product Specification 9.2 General Specifications Airflow Specification for CIOB-X2 and CMIC-LE The maximum thermal specifications for components listed require installation of a heat sink or maintenance of a minimum level of airflow. Failure to maintain sufficient cooling airflow will result in components exceeding maximum case temperature. Table 61 lists several chipset components and their required airflow. Table 61. Airflow Specification for Key Components 9.
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General Specifications 9.3.2 Intel® SHG2 DP Server Board Technical Product Specification Power Supply Specifications This section provides power supply design guidelines for an SHG2-based system, including voltage and current specifications, and power supply power cycling sequence characteristics. Table 63. SHG2 DC Power Supply Voltage Specification Parameter +3.3 V Min Nom Max Units Tolerance +3.168 +3.30 +3.46 Vrms +5/-4% +5 V +4.80 +5.00 +5.25 Vrms +5/-4% +12 V +11.52 +12.00 +12.
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Intel® SHG2 DP Server Board Technical Product Specification General Specifications Vout V1 10% Vout V2 V3 V4 Tvout rise Tvout on Tvout_on Figure 15. Output Voltage Timing Table 66 shows the timing requirements for the power supply being turned on and off via the AC input with PSON held low, and the power supply being turned on and off with the PSON signal after AC input is applied. Table 66.
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General Specifications Item T pwok_off Intel® SHG2 DP Server Board Technical Product Specification Description Delay from PWOK deasserted to output voltages (3.3V, 5V, 12V, -12V) dropping out of regulation limits. Duration of PWOK being in the deasserted state during an off/on cycle using AC or the PSON signal. Delay from 5VSB being in regulation to O/Ps being in regulation at AC turn on.
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Intel® SHG2 DP Server Board Technical Product Specification General Specifications 2. Voltage regulation limits shall be maintained over the entire AC input range and any steady state temperature and operating conditions specified. 3. Voltages shall be stable as determined by bode plot and transient response. The combined error of peak overshoot, set point, regulation, and undershoot voltage shall be less than or equal to +/-5% of the output voltage setting.
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Mechanical Specifications Intel® SHG2 DP Server Board Technical Product Specification 10. Mechanical Specifications The following diagrams show the mechanical specifications of the SHG2 server baseboard. All dimensions are given in inches, and are dimensioned per ANSI Y15.4M. Connectors are dimensioned to pin 1. Figure 17. SHG2 Baseboard Mechanical Diagram 1 78 Intel Order Number C11343-001 Revision 1.
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Intel® SHG2 DP Server Board Technical Product Specification Mechanical Specifications Figure 18. SHG2 Baseboard Mechanical Diagram 2 Revision 1.
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Regulatory and Integration Information Intel® SHG2 DP Server Board Technical Product Specification 11. Regulatory and Integration Information 11.1 Product Regulatory Compliance 11.1.1 Product Safety Compliance The Intel SHG2 Server Board complies with the following safety requirements: • • • • 11.1.
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Intel® SHG2 DP Server Board Technical Product Specification 11.2.2 Regulatory and Integration Information Australian Communications Authority (ACA) (C-Tick Declaration of Conformity) This product has been tested to AS/NZS 3548, and complies with ACA emission requirements. The product has been marked with the C-Tick Mark to illustrate its compliance. 11.2.
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Regulatory and Integration Information Intel® SHG2 DP Server Board Technical Product Specification VARNING Explosionsfara vid felaktigt batteribyte. Använd samma batterityp eller en ekvivalent typ som rekommenderas av apparattillverkaren. Kassera använt batteri enligt fabrikantens instruktion. VAROITUS Paristo voi räjähtää, jos se on virheellisesti asennettu. Vaihda paristo ainoastaan laitevalmistajan suosittelemaan tyyppiin. Hävitä käytetty paristo valmistajan ohjeiden mukaisesti.
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Intel® SHG2 DP Server Board Technical Product Specification Appendix A: Glossary Appendix A: Glossary Term AGTL+ Assisted Gunning Transceiver Logic + Definition AP Application Processor APIC Advanced Programmable Interrupt Controller ASF Alert Standard Forum ASR Asynchronous System Reset BGA Ball-Grid Array BIST Built-In Self Test BMC Baseboard Management Controller BSP Bootstrap Processor CIOB-X2 PCI-X 64-bit bridge CMIC-LE Processor, CIOB-X2, memory interface device, and legacy PCI
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Appendix A: Glossary Intel® SHG2 DP Server Board Technical Product Specification NMI Non-maskable Interrupt PBGA Pin Ball Grid Array PGA Pin Grid Array PIC Programmable Interrupt Controller POST Power On Self Test RISC Reduced Instruction Set Computing RTC Real Time Clock SEC Single Edge Contact SEL System Event Log SERIRQ Serialized IRQ SDRAM Synchronous Dynamic RAM SHV Standard High Volume SIO Super I/O* bridge SM Server Management SMI System Management Interrupt SMM Serve
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Intel® SHG2 DP Server Board Technical Product Specification Appendix B: Reference Documents Appendix B: Reference Documents Refer to the following documents for additional information: • • • • • • • • • • • • • • • • • • • • Foster Processor Electrical, Mechanical, and Thermal Specification Rev 1.5 ServerWorks Champion Memory & I/O Controller-Low End (CMIC-LE) Specification Rev 2.0 ServerWorks Champion South Bridge (CSB5) Specification Rev 2.0 ServerWorks Champion IO Bridge (CIOB-X2) Specification Rev 1.