Propeller Manual
Table Of Contents
- Preface
- Chapter 1 : Introducing the Propeller Chip
- Concept
- Package Types
- Pin Descriptions
- Specifications
- Hardware Connections
- Boot Up Procedure
- Run-Time Procedure
- Shutdown Procedure
- Block Diagram
- Shared Resources
- System Clock
- Cogs (processors)
- Hub
- I/O Pins
- System Counter
- CLK Register
- Locks
- Main Memory
- Main RAM
- Main ROM
- Character Definitions
- Log and Anti-Log Tables
- Sine Table
- Boot Loader and Spin Interpreter
- Chapter 2 : Spin Language Reference
- Structure of Propeller Objects/Spin
- Categorical Listing of Propeller Spin Language
- Spin Language Elements
- ABORT
- BYTE
- BYTEFILL
- BYTEMOVE
- CASE
- CHIPVER
- CLKFREQ
- _CLKFREQ
- CLKMODE
- _CLKMODE
- CLKSET
- CNT
- COGID
- COGINIT
- COGNEW
- COGSTOP
- CON
- CONSTANT
- Constants (pre-defined)
- CTRA, CTRB
- DAT
- DIRA, DIRB
- FILE
- FLOAT
- _FREE
- FRQA, FRQB
- IF
- IFNOT
- INA, INB
- LOCKCLR
- LOCKNEW
- LOCKRET
- LOCKSET
- LONG
- LONGFILL
- LONGMOVE
- LOOKDOWN, LOOKDOWNZ
- LOOKUP, LOOKUPZ
- NEXT
- OBJ
- Operators
- Expression Workspace
- Operator Attributes
- Unary / Binary
- Normal / Assignment
- Constant and/or Variable Expression
- Level of Precedence
- Intermediate Assignments
- Constant Assignment ‘=’
- Variable Assignment ‘:=’
- Add ‘+’, ‘+=’
- Positive ‘+’ (unary form of Add)
- Subtract ‘-’, ‘-=’
- Negate ‘-’ (unary form of Subtract)
- Decrement, pre- or post- ‘- -’
- Increment, pre- or post- ‘+ +’
- Multiply, Return Low ‘*’, ‘*=’
- Multiply, Return High ‘**’, ‘**=’
- Divide ‘/’, ‘/=’
- Modulus ‘//’, ‘//=’
- Limit Minimum ‘#>’, ‘#>=’
- Limit Maximum ‘<#’, ‘<#=’
- Square Root ‘^^’
- Absolute Value ‘||’
- Sign-Extend 7 or Post-Clear ‘~’
- Sign-Extend 15 or Post-Set ‘~~’
- Shift Arithmetic Right ‘~>’, ‘~>=’
- Random ‘?’
- Bitwise Decode ‘|<’
- Bitwise Encode ‘>|’
- Bitwise Shift Left ‘<<’, ‘<<=’
- Bitwise Shift Right ‘>>’, ‘>>=’
- Bitwise Rotate Left ‘<-’, ‘<-=’
- Bitwise Rotate Right ‘->’, ‘->=’
- Bitwise Reverse ‘><’, ‘><=’
- Bitwise AND ‘&’, ‘&=’
- Bitwise OR ‘|’, ‘|=’
- Bitwise XOR ‘^’, ‘^=’
- Bitwise NOT ‘!’
- Boolean AND ‘AND’, ‘AND=’
- Boolean OR ‘OR’, ‘OR=’
- Boolean NOT ‘NOT’
- Boolean Is Equal ‘==’, ‘===’
- Boolean Is Not Equal ‘<>’, ‘<>=’
- Boolean Is Less Than ‘<’, ‘<=’
- Boolean Is Greater Than ‘>’, ‘>=’
- Boolean Is Equal or Less ‘=<’, ‘=<=’
- Boolean Is Equal or Greater ‘=>’, ‘=>=’
- Symbol Address ‘@’
- Object Address Plus Symbol ‘@@’
- OUTA, OUTB
- PAR
- PHSA, PHSB
- PRI
- PUB
- QUIT
- REBOOT
- REPEAT
- RESULT
- RETURN
- ROUND
- SPR
- _STACK
- STRCOMP
- STRING
- STRSIZE
- Symbols
- TRUNC
- VAR
- VCFG
- VSCL
- WAITCNT
- WAITPEQ
- WAITPNE
- WAITVID
- WORD
- WORDFILL
- WORDMOVE
- _XINFREQ
- Chapter 3 : Assembly Language Reference
- The Structure of Propeller Assembly
- Categorical Listing of Propeller Assembly Language
- Assembly Language Elements
- ABS
- ABSNEG
- ADD
- ADDABS
- ADDS
- ADDSX
- ADDX
- AND
- ANDN
- CALL
- CLKSET
- CMP
- CMPS
- CMPSUB
- CMPSX
- CMPX
- CNT
- COGID
- COGINIT
- COGSTOP
- Conditions ( IF_x )
- CTRA, CTRB
- DIRA, DIRB
- DJNZ
- Effects ( WC, WZ, WR, NR )
- FIT
- FRQA, FRQB
- HUBOP
- IF_x (Conditions)
- INA, INB
- JMP
- JMPRET
- LOCKCLR
- LOCKNEW
- LOCKRET
- LOCKSET
- MAX
- MAXS
- MIN
- MINS
- MOV
- MOVD
- MOVI
- MOVS
- MUXC
- MUXNC
- MUXNZ
- MUXZ
- NEG
- NEGC
- NEGNC
- NEGNZ
- NEGZ
- NOP
- NR
- Operators
- OR
- ORG
- OUTA, OUTB
- PAR
- PHSA, PHSB
- RCL
- RCR
- RDBYTE
- RDLONG
- RDWORD
- Registers
- RES
- RET
- REV
- ROL
- ROR
- SAR
- SHL
- SHR
- SUB
- SUBABS
- SUBS
- SUBSX
- SUBX
- SUMC
- SUMNC
- SUMZ
- Symbols
- TEST
- TESTN
- TJNZ
- TJZ
- VCFG
- VSCL
- WAITCNT
- WAITPEQ
- WAITPNE
- WAITVID
- WC
- WR
- WRBYTE
- WRLONG
- WRWORD
- WZ
- XOR
- Appendix A: Reserved Word List
- Appendix B: Math Samples and Function Tables
- Index
RDLONG – Assembly Language Reference
RDLONG
Instruction: Read long of main memory.
RDLONG Value, 〈#〉 Address
Result: Long is stored in Value.
•
Value (d-field) is the register to store the long value into.
•
Address (s-field) is a register or a 9-bit literal whose value is the main memory
address to read from.
Opcode Table:
–INSTR– ZCRI –CON– –DEST– –SRC– Z Result C Result Result Clocks
000010 001i 1111 ddddddddd sssssssss
Result = 0 --- Written 7..22
Concise Truth Table:
In Out
Destination Source Z
C
Effects
Destination
1
Z
2
C
$----_----; - $----_----; - -
-
wz wc long value
0 0
1
Destination Out is always generated since including an NR effect would turn RDLONG into a WRLONG instruction.
2
The Z flag is cleared (0) unless Destination Out equals 0.
Explanation
RDLONG syncs to the Hub, reads the long of main memory at Address, and stores it into the
Value register. Address can point to any byte within the desired long; the address’ lower two
bits will be cleared to zero resulting in an address pointing to a long boundary.
If the
WZ effect is specified, the Z flag will be set (1) if the value read from main memory is
zero. The
NR effect can not be used with RDLONG as that would change it to a WRLONG
instruction.
RDLONG is a hub instruction. Hub instructions require 7 to 22 clock cycles to execute
depending on the relation between the cog’s hub access window and the instruction’s moment
of execution. See Hub on page 24 for more information.
Page 336 · Propeller Manual v1.1