Datasheet
Propeller™ P8X32A Datasheet www.parallax.com
Copyright © Parallax Inc. Page 22 of 37 Rev 1.1 9/12/2008
6.4. Propeller Assembly Instruction Table
The Propeller Assembly Instruction Table lists the instruction’s 32-bit opcode, outputs and number of clock cycles. The
opcode consists of the instruction bits (
iiiiii), the “effect” status for the Z flag, C flag, result and indirect/immediate status
(zcri), the conditional execution bits (cccc), and the destination and source bits (ddddddddd and sssssssss). The meaning of the
Z and C flags, if any, is shown in the Z Result and C Result fields; indicating the meaning of a 1 in those flags. The Result field
(
R) shows the instruction’s default behavior for writing (1) or not writing (0) the instruction’s result value. The Clocks field
shows the number of clocks the instruction requires for execution.
0 1 Zeros (0) and ones (1) mean binary 0 and 1.
i Lower case “i” denotes a bit that is affected by immediate status.
d s Lower case “d” and “s” indicate destination and source bits.
? Question marks denote bits that are dynamically set by the compiler.
--- Hyphens indicate items that are not applicable or not important.
.. Double-periods represent a range of contiguous values.
iiiiii zcri cccc ddddddddd sssssssss
Instruction Description Z Result C Result R
Clocks
000000 000i 1111 ddddddddd sssssssss WRBYTE D,S
Write D[7..0] to main memory byte S[15..0] - -
0
7..22 *
000000 001i 1111 ddddddddd sssssssss RDBYTE D,S
Read main memory byte S[15..0] into D (0-
extended)
Result = 0 -
1
7..22 *
000001 000i 1111 ddddddddd sssssssss WRWORD D,S
Write D[15..0] to main memory word S[15..1] - -
0
7..22 *
000001 001i 1111 ddddddddd sssssssss RDWORD D,S
Read main memory word S[15..1] into D (0-
extended)
Result = 0 -
1
7..22 *
000010 000i 1111 ddddddddd sssssssss WRLONG D,S
Write D to main memory long S[15..2] - -
0
7..22 *
000010 001i 1111 ddddddddd sssssssss RDLONG D,S
Read main memory long S[15..2] into D Result = 0 -
1
7..22 *
000011 000i 1111 ddddddddd sssssssss HUBOP D,S
Perform hub operation according to S Result = 0 -
0
7..22 *
000011 0001 1111 ddddddddd ------000 CLKSET D
Set the global CLK register to D[7..0] - -
0
7..22 *
000011 0011 1111 ddddddddd ------001 COGID D
Get this cog number (0..7) into D Result = 0 -
1
7..22 *
000011 0001 1111 ddddddddd ------010 COGINIT D
Initialize a cog according to D Result = 0 No cog free
0
7..22 *
000011 0001 1111 ddddddddd ------011 COGSTOP D
Stop cog number D[2..0] - -
0
7..22 *
000011 0011 1111 ddddddddd ------100 LOCKNEW D
Checkout a new LOCK number (0..7) into D Result = 0 No lock free
1
7..22 *
000011 0001 1111 ddddddddd ------101 LOCKRET D
Return lock number D[2..0] - -
0
7..22 *
000011 0001 1111 ddddddddd ------110 LOCKSET D
Set lock number D[2..0] - Prior lock state
0
7..22 *
000011 0001 1111 ddddddddd ------111 LOCKCLR D
Clear lock number D[2..0] - Prior lock state
0
7..22 *
000100 001i 1111 ddddddddd sssssssss MUL D,S
Multiply unsigned D[15..0] by S[15..0] Result = 0 -
1
future
000101 001i 1111 ddddddddd sssssssss MULS D,S
Multiply signed D[15..0] by S[15..0] Result = 0 -
1
future
000110 001i 1111 ddddddddd sssssssss ENC D,S
Encode magnitude of S into D, result = 0..31 Result = 0 -
1
future
000111 001i 1111 ddddddddd sssssssss ONES D,S
Get number of 1's in S into D, result = 0..31 Result = 0 -
1
future
001000 001i 1111 ddddddddd sssssssss ROR D,S
Rotate D right by S[4..0] bits Result = 0 D[0]
1
4
001001 001i 1111 ddddddddd sssssssss ROL D,S
Rotate D left by S[4..0] bits Result = 0 D[31]
1
4
001010 001i 1111 ddddddddd sssssssss SHR D,S
Shift D right by S[4..0] bits, set new MSB to 0 Result = 0 D[0]
1
4
001011 001i 1111 ddddddddd sssssssss SHL D,S
Shift D left by S[4..0] bits, set new LSB to 0 Result = 0 D[31]
1
4
001100 001i 1111 ddddddddd sssssssss RCR D,S
Rotate carry right into D by S[4..0] bits Result = 0 D[0]
1
4
001101 001i 1111 ddddddddd sssssssss RCL D,S
Rotate carry left into D by S[4..0] bits Result = 0 D[31]
1
4
001110 001i 1111 ddddddddd sssssssss SAR D,S
Shift D arithmetically right by S[4..0] bits Result = 0 D[0]
1
4
001111 001i 1111 ddddddddd sssssssss REV D,S
Reverse 32–S[4..0] bottom bits in D and 0-
extend
Result = 0 D[0]
1
4
010000 001i 1111 ddddddddd sssssssss MINS D,S
Set D to S if signed (D < S) D = S Signed (D < S)
1
4
010001 001i 1111 ddddddddd sssssssss MAXS D,S
Set D to S if signed (D => S) D = S Signed (D < S)
1
4
010010 001i 1111 ddddddddd sssssssss MIN D,S
Set D to S if unsigned (D < S) D = S Unsigned (D < S)
1
4
010011 001i 1111 ddddddddd sssssssss MAX D,S
Set D to S if unsigned (D => S) D = S Unsigned (D < S)
1
4
010100 001i 1111 ddddddddd sssssssss MOVS D,S
Insert S[8..0] into D[8..0] Result = 0 -
1
4
010101 001i 1111 ddddddddd sssssssss MOVD D,S
Insert S[8..0] into D[17..9] Result = 0 -
1
4
010110 001i 1111 ddddddddd sssssssss MOVI D,S
Insert S[8..0] into D[31..23] Result = 0 -
1
4
010111 001i 1111 ddddddddd sssssssss JMPRET D,S
Insert PC+1 into D[8..0] and set PC to S[8..0] Result = 0 -
1
4
010111 000i 1111 --------- sssssssss JMP S
Set PC to S[8..0] Result = 0 -
0
4