Datasheet

Propeller™ P8X32A Datasheet www.parallax.com
Copyright © Parallax Inc. Page 16 of 37 Rev 1.1 9/12/2008
Figure 8
Propeller Character
Interleaving
As shown in Figure 8, The character pairs are merged
row-by-row such that each character's 16 horizontal pixels
are spaced apart and interleaved with their neighbors' so
that the even character takes bits 0, 2, 4, ...30, and the odd
character takes bits 1, 3, 5, ...31. The leftmost pixels are in
the lowest bits, while the rightmost pixels are in the
highest bits. This forms a long for each row of pixels in
the character pair. 32 such longs, building from top row
down to bottom, make up the complete merged-pair
definition. The definitions are encoded in this manner so
that a cog’s video hardware can handle the merged longs
directly, using color selection to display either the even or
the odd character.
Some character codes have inescapable meanings, such as
9 for Tab, 10 for Line Feed, and 13 for Carriage Return.
These character codes invoke actions and do not equate to
static character definitions. For this reason, their character
definitions have been used for special four-color
characters. These four-color characters are used for
drawing 3-D box edges at run-time and are implemented
as 16 x 16 pixel cells, as opposed to the normal 16 x 32
pixel cells. They occupy even-odd character pairs 0-1, 8-
9, 10-11, and 12-13.
5.1.4. Math Function Tables
Base-2 Log and Anti-Log tables, each with 2048 unsigned
words, facilitate converting values to and from exponent
form to facilitate some operations; see the Propeller
Manual for access instructions. Also, a sine table
provides 2049 unsigned 16-bit sine samples spanning 0°
to 90° inclusively (0.0439° resolution).
5.2. Cog RAM
As stated in Section 4.3, the Cog RAM is used for
executable code, data, and variables, and the last 16
locations serve as interfaces to the System Counter, I/O
pins, and local cog peripherals (see Table 15).
When a cog is booted up, locations 0 ($000) through 495
($1EF) are loaded sequentially from Main RAM / ROM
and its special purpose locations, 496 ($1F0) through 511
($1FF), are cleared to zero. Each Special Purpose register
may be accessed via its physical address, its predefined
name, or indirectly in Spin via a register array variable
SPR with an index of 0 to 15, the last four bits of the
register's address.
Table 15: Cog RAM Special Purpose Registers
Cog RAM Map Address Name Type Description
$1F0
PAR
Read-Only
1
Boot Parameter
$1F1
CNT
Read-Only
1
System Counter
$1F2
INA
Read-Only
1
Input States for P31 - P0
$1F3
INB
Read-Only
1
Input States for P63- P32
3
$1F4
OUTA
Read/Write Output States for P31 - P0
$1F5
OUTB
Read/Write Output States for P63 – P32
3
$1F6
DIRA
Read/Write Direction States for P31 - P0
$1F7
DIRB
Read/Write Direction States for P63 - P32
3
$1F8
CTRA
Read/Write Counter A Control
$1F9
CTRB
Read/Write Counter B Control
$1FA
FRQA
Read/Write Counter A Frequency
$1FB
FRQB
Read/Write Counter B Frequency
$1FC
PHSA
Read/Write
2
Counter A Phase:
$1FD
PHSB
Read/Write
2
Counter B Phase
$1FE
VCFG
Read/Write Video Configuration
$1FF
VSCL
Read/Write Video Scale
Note 1: Only accessible as a source register (i.e. MOV Dest, Source).
Note 2: Only readable as a Source Register (i.e.
MOV Dest, Source); read-modify-write not possible as a Destination Register.
Note 3: Reserved for future use.