Datasheet

Propeller™ P8X32A Datasheet www.parallax.com
Copyright © Parallax Inc. Page 14 of 37 Rev 1.1 9/12/2008
4.11. CLK Register
The CLK register is the System Clock configuration
control; it determines the source and characteristics of the
System Clock. It configures the RC Oscillator, Clock
PLL, Crystal Oscillator, and Clock Selector circuits (See
the Block Diagram, page 1). It is configured at compile
time by the _CLKMODE declaration and is writable at run
time through the CLKSET command. Whenever the CLK
register is written, a global delay of ~75 µs occurs as the
clock source transitions.
Whenever this register is changed, a copy of the value
written should be placed in the Clock Mode value
location (which is BYTE[4] in Main RAM) and the
resulting master clock frequency should be written to the
Clock Frequency value location (which is LONG[0] in
Main RAM) so that objects which reference this data will
have current information for their timing calculations.
Use Spin's CLKSET command when possible (see sections
6.3 and 6.4) since it automatically updates all the above-
mentioned locations with the proper information.
Table 13: Valid Clock Modes
Valid Expression CLK Reg. Value Valid Expression CLK Reg. Value
RCFAST 0_0_0_00_000
RCSLOW 0_0_0_00_001
XINPUT 0_0_1_00_010
XTAL1 + PLL1X 0_1_1_01_011
XTAL1 + PLL2X 0_1_1_01_100
XTAL1 + PLL4X 0_1_1_01_101
XTAL1 + PLL8X 0_1_1_01_110
XTAL1 + PLL16X 0_1_1_01_111
XTAL1 0_0_1_01_010
XTAL2 0_0_1_10_010
XTAL3 0_0_1_11_010
XTAL2 + PLL1X 0_1_1_10_011
XTAL2 + PLL2X 0_1_1_10_100
XTAL2 + PLL4X 0_1_1_10_101
XTAL2 + PLL8X 0_1_1_10_110
XTAL2 + PLL16X 0_1_1_10_111
XINPUT + PLL1X 0_1_1_00_011
XINPUT + PLL2X 0_1_1_00_100
XINPUT + PLL4X 0_1_1_00_101
XINPUT + PLL8X 0_1_1_00_110
XINPUT + PLL16X 0_1_1_00_111
XTAL3 + PLL1X 0_1_1_11_011
XTAL3 + PLL2X 0_1_1_11_100
XTAL3 + PLL4X 0_1_1_11_101
XTAL3 + PLL8X 0_1_1_11_110
XTAL3 + PLL16X 0_1_1_11_111
Table 14: CLK Register Fields
Bit 7 6 5 4 3 2 1 0
Name
RESET PLLENA OSCENA OSCM1 OSCM2 CLKSEL2 CLKSEL1 CLKSEL0
RESET Effect
0
Always write ‘0’ here unless you intend to reset the chip.
1
Same as a hardware reset – reboots the chip.
PLLENA Effect
0
Disables the PLL circuit.
1
Enables the PLL circuit. The PLL internally multiplies the XIN pin frequency by 16. OSCENA must be ‘1’ to propagate the
XIN signal to the PLL. The PLL’s internal frequency must be kept within 64 MHz to 128 MHz – this translates to an XIN
frequency range of 4 MHz to 8 MHz. Allow 100 µs for the PLL to stabilize before switching to one of its outputs via the
CLKSEL bits. Once the OSC and PLL circuits are enabled and stabilized, you can switch freely among all clock sources by
changing the CLKSEL bits.
OSCENA Effect
0
Disables the OSC circuit
1
Enables the OSC circuit so that a clock signal can be input to XIN, or so that XIN and XOUT can function together as a
feedback oscillator. The OSCM bits select the operating mode of the OSC circuit. Note that no external resistors or
capacitors are required for crystals and resonators. Allow a crystal or resonator 10 ms to stabilize before switching to an
OSC or PLL output via the CLKSEL bits. When enabling the OSC circuit, the PLL may be enabled at the same time so that
they can share the stabilization period.
OSCM1 OSCM2 XOUT Resistance XIN and XOUT Capacitance Frequency Range
0 0
Infinite 6 pF (pad only) DC to 80 MHz Input
0 1
2000  36 pF 4 MHz to 16 MHz Crystal/Resonator
1 0
1000  26 pF 8 MHz to 32 MHz Crystal/Resonator
1 1
500  16 pF 20 MHz to 60 MHz Crystal/Resonator
CLKSEL2 CLKSEL1 CLKSEL0 Master Clock Source Notes
0
0 0 ~12 MHz Internal No external parts (8 to 20 MHz)
0
0 1 ~20 kHz Internal No external parts, very low power (13-33 kHz)
0
1 0 XIN OSC OSCENA must be ‘1’
0
1 1 XIN × 1 OSC+PLL OSCENA and PLLENA must be ‘1’
1
0 0 XIN × 2 OSC+PLL OSCENA and PLLENA must be ‘1’
1
0 1 XIN × 4 OSC+PLL OSCENA and PLLENA must be ‘1’
1
1 0 XIN × 8 OSC+PLL OSCENA and PLLENA must be ‘1’
1
1 1 XIN × 16 OSC+PLL OSCENA and PLLENA must be ‘1’