Datasheet

Propeller™ P8X32A Datasheet www.parallax.com
Copyright © Parallax Inc. Page 11 of 37 Rev 1.1 9/12/2008
Table 6: Counter Modes (CTRMODE Field Values)
CTRMODE Description
Accumulate
FRQx to PHSx
APIN
Output*
BPIN
Output*
%00000 Counter disabled (off) 0 (never) 0 (none) 0 (none)
%00001
%00010
%00011
PLL internal (video mode)
PLL single-ended
PLL differential
1 (always)
1
1
0
PLLx
PLLx
0
0
!PLLx
%00100
%00101
NCO single-ended
NCO differential
1
1
PHSx[31]
PHSx[31]
0
!PHSx[31]
%00110
%00111
DUTY single-ended
DUTY differential
1
1
PHSx-Carry
PHSx-Carry
0
!PHSx-Carry
%01000
%01001
%01010
%01011
POS detector
POS detector with feedback
POSEDGE detector
POSEDGE detector w/ feedback
A
1
A
1
A
1
& !A
2
A
1
& !A
2
0
0
0
0
0
!A1
0
!A1
%01100
%01101
%01110
%01111
NEG detector
NEG detector with feedback
NEGEDGE detector
NEGEDGE detector w/ feedback
!A
1
!A
1
!A
1
& A
2
!A
1
& A
2
0
0
0
0
0
!A1
0
!A1
%10000
%10001
%10010
%10011
%10100
%10101
%10110
%10111
%11000
%11001
%11010
%11011
%11100
%11101
%11110
%11111
LOGIC never
LOGIC !A & !B
LOGIC A & !B
LOGIC !B
LOGIC !A & B
LOGIC !A
LOGIC A <> B
LOGIC !A | !B
LOGIC A & B
LOGIC A == B
LOGIC A
LOGIC A | !B
LOGIC B
LOGIC !A | B
LOGIC A | B
LOGIC always
0
!A
1
& !B
1
A
1
& !B
1
!B
1
!A
1
& B
1
!A
1
A
1
<> B
1
!A
1
| !B
1
A
1
& B
1
A
1
== B
1
A
1
A
1
| !B
1
B
1
!A
1
| B
1
A
1
| B
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
*Must set corresponding DIR bit to affect pin. A1 = APIN input delayed by 1 clock. A2 = APIN input delayed by 2 clocks. B1 = BPIN input delayed by 1 clock.
4.10. Video Generator
Each cog has a video generator module that facilitates
transmitting video image data at a constant rate. There are
two registers and one instruction which provide control
and access to the video generator. Counter A of the cog
must be running in a PLL mode and is used to generate
the timing signal for the Video Generator. The Video
Scale Register specifies the number of Counter A PLL
(PLLA) clock cycles for each pixel and number of clock
cycles before fetching another frame of data provided by
the WAITVID instruction which is executed within the cog.
The Video Configuration Register establishes the mode
the Video Generator should operate, and can generate
VGA or composite video (NTSC or PAL).
The Video Generator should be initialized by first starting
Counter A, setting the Video Scale Register, setting the
Video Configuration Register, then finally providing data
via the WAITVID instruction. Failure to properly initialize
the Video Generator by first starting PLLA will cause the
cog to indefinitely hang when the WAITVID instruction is
executed.
4.10.1. VCFG – Video Configuration Register
The Video Configuration Register contains the
configuration settings of the video generator and is shown
in Table 7.
In Propeller Assembly, the VMode through AuralSub
fields can conveniently be written using the MOVI
instruction, the VGroup field can be written with the MOVD
instruction, and the VPins field can be written with the
MOVS instruction.
Table 7: VCFG Register
31 30..29 28 27 26 25..23 22..12 11..9 8 7..0
- VMode CMode Chroma1 Chroma0 AuralSub - VGroup - VPins