Datasheet

Propeller™ P8X32A Datasheet www.parallax.com
Copyright © Parallax Inc. Page 10 of 37 Rev 1.1 9/12/2008
4.9. Cog Counters
Each cog has two counter modules: CTRA and CTRB. Each
counter module can control or monitor up to two I/O pins
and perform conditional 32-bit accumulation of its FRQ
register into its PHS register on every clock cycle.
Each counter module also has its own phase-locked loop
(PLL) which can be used to synthesize frequencies up to
128 MHz.
With a little setup or oversight from the cog, a counter can
be used for:
• frequency synthesis
• frequency measurement
• pulse counting
• pulse measurement
• multi-pin state measurement
• pulse-width modulation
• duty-cycle measurement
• digital-to-analog conversion
• analog-to-digital conversion
For some of these operations, the cog can be set up and
left in a free-running mode. For others, it may use
WAITCNT to time-align counter reads and writes within a
loop, creating the effect of a more complex state machine.
Note that for a cog clock frequency of 80 MHz, the
counter update period is a mere 12.5 ns. This high speed,
combined with 32-bit precision, allows for very dynamic
signal generation and measurement.
The design goal for the counter was to create a simple and
flexible subsystem which could perform some repetitive
task on every clock cycle, thereby freeing the cog to
perform some computationally richer super-task. While
the counters have only 32 basic operating modes, there is
no limit to how they might be used dynamically through
software. Integral to this concept is the use of the
WAITPEQ, WAITPNE, and WAITCNT instructions, which can
event-align or time-align a cog with its counters.
Each counter has three registers:
4.9.1. CTRA / CTRB – Control register
The CTR (CTRA and CTRB) register selects the counter's
operating mode. As soon as this register is written, the
new operating mode goes into effect. Writing a zero to
CTR will immediately disable the counter, stopping all
pin output and PHS accumulation.
Table 4: CTRA and CTRB Registers
31 30..26 25..23 22..15 14..9 8..6 5..0
- CTRMODE PLLDIV - BPIN - APIN
The CTRMODE field selects one of 32 operating modes
for the counter, conveniently written (along with
PLLDIV) using the MOVI instruction. These modes of
operation are listed in Table 6 on page 11.
Table 5: PLLDIV Field
PLLDIV %000 %001 %010 %011 %100 %101 %110 %111
Output
VCO
128
VCO
64
VCO
32
VCO
16
VCO
8
VCO
4
VCO
2
VCO
1
PLLDIV selects a PLL output tap and may be ignored if
not used.
The PLL modes (%00001 to %00011) cause FRQ-to-PHS
accumulation to occur every clock cycle. This creates a
numerically-controlled oscillator (NCO) in PHS[31],
which feeds the counter PLL's reference input. The PLL
will multiply this frequency by 16 using its voltage-
controlled oscillator (VCO). For stable operation, it is
recommended that the VCO frequency be kept within 64
MHz to 128 MHz. This translates to an NCO frequency of
4 MHz to 8 MHz.
The PLLDIV field of the CTR register selects which
power-of-two division of the VCO frequency will be used
as the final PLL output. This affords a PLL range of 500
kHz to 128 MHz.
BPIN selects a pin to be the secondary I/O. It may be
ignored if not used and may be written using the MOVD
instruction.
APIN selects a pin to be the primary I/O. It may be
ignored if not used and may be written using the MOVS
instruction.
4.9.2. FRQA / FRQB – Frequency register
FRQ (FRQA and FRQB) holds the value that will be
accumulated into the PHS register. For some applications,
FRQ may be written once, and then ignored. For others, it
may be rapidly modulated.
4.9.3. PHSA / PHSB – Phase register
The PHS (PHSA and PHSB) register can be written and
read via cog instructions, but it also functions as a free-
running accumulator, summing the FRQ register into
itself on potentially every clock cycle. Any instruction
writing to PHS will override any accumulation for that
clock cycle. PHS can only be read through the source
operand (same as PAR, CNT, INA, and INB). Beware
that doing a read-modify-write instruction on PHS, like
"ADD PHSA, #1", will cause the last-written value to be
used as the destination operand input, rather than the
current accumulation.