BASIC stamp manual v2.2

BASIC Stamp Architecture – Memory Organization

Page 82 • BASIC Stamp Syntax and Reference Manual 2.2 • www.parallax.com

sets the corresponding I/O pin to an output direction and a low bit (0) sets

the corresponding I/O pin to an input direction.

The remaining words (W0 – W6) are available for general-purpose use.

Each word consists of separately addressable bytes and the first two bytes

(B0 and B1) are bit addressable as well.

You may assign other names (symbols) to these RAM registers as shown

in section "Defining and Using Variables", below.

When the BS1 is powered up, or reset, all memory locations are cleared to

0, so all pins are inputs (DIRS = %00000000). Also, if the PBASIC program

sets all the I/O pins to outputs (DIRS = %11111111), then they will initially

output low, since the output latch (PINS) is cleared to all zeros upon

power-up or reset, as well.

Word Name Byte Names Bit Names Special Notes

PORT

PINS

DIRS

PIN0 – PIN7

DIR0 – DIR7

I/O pins; bit addressable.

I/O pins directions; bit addressable.

BIT0 – BIT7

BIT8 – BIT15

Bit addressable.

B10

B11

B12

B13

Used by GOSUB instruction.

Table 4.1: BS1 RAM Organization.

Note: There are eight words,

consisting of two bytes each for a

total of 16 bytes. The bits within

the upper two words are

individually addressable.

The BS2, BS2e, and BS2sx models have 32 bytes of Variable RAM space

arranged as shown in Table 4.2. Of these, the first six bytes are reserved

for input, output, and direction control of the I/O pins. The remaining 26

bytes are available for general-purpose use as variables.

The BS2p, BS2pe, and BS2px models have an extra set of INS, OUTS, and

DIRS registers for a total of 38 bytes of variable RAM. These are “shadow”

registers that are switched in and out of the memory map with the

AUXIO, MAINIO, and IOTERM commands. While this feature exists in

RAM ORGANIZATION.