Datasheet

Block diagram and pin description L3G4200D
8/42 Doc ID 17116 Rev 3
Figure 3. L3G4200D external low-pass filter values
(a)
Table 2. Pin description
Pin# Name Function
1 Vdd_IO Power supply for I/O pins
2
SCL
SPC
I
2
C serial clock (SCL)
SPI serial port clock (SPC)
3
SDA
SDI
SDO
I
2
C serial data (SDA)
SPI serial data input (SDI)
3-wire interface serial data output (SDO)
4
SDO
SA0
SPI serial data output (SDO)
I
2
C least significant bit of the device address (SA0)
5CS
SPI enable
I
2
C/SPI mode selection (1:SPI idle mode / I
2
C communication
enabled; 0: SPI communication mode / I
2
C disabled)
6 DRDY/INT2 Data ready/FIFO interrupt
7 INT1 Programmable interrupt
8 Reserved Connect to GND
9 Reserved Connect to GND
10 Reserved Connect to GND
11 Reserved Connect to GND
12 Reserved Connect to GND
13 GND 0 V supply
14 PLLFILT Phase-locked loop filter (see Figure 3)
15 Reserved Connect to Vdd
16 Vdd Power supply
a. Pin 14 PLLFILT maximum voltage level is equal to Vdd.
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