Datasheet

L3G4200D Register description
Doc ID 17116 Rev 3 33/42
Figure 19. INT1_Sel and Out_Sel configuration block diagram
Table 35. Out_Sel configuration setting
Hpen OUT_SEL1 OUT_SEL0 Description
x00
Data in DataReg and FIFO are non-high-
pass-filtered
x01
Data in DataReg and FIFO are high-pass-
filtered
01x
Data in DataReg and FIFO are low-pass-
filtered by LPF2
11x
Data in DataReg and FIFO are high-pass and
low-pass-filtered by LPF2
Table 36. INT_SEL configuration setting
Hpen INT_SEL1 INT_SEL2 Description
x00
Non-high-pass-filtered data are used for
interrupt generation
x01
High-pass-filtered data are used for interrupt
generation
01x
Low-pass-filtered data are used for interrupt
generation
11x
High-pass and low-pass-filtered data are
used for interrupt generation
ADC
LPF1
HPF
0
1
HPen
LPF2
10
11
01
00
Out_Sel <1:0>
DataReg
FIFO
32x16x3
00
11
10
01
Interrupt
generator
INT1_Sel <1:0>
AM07949V2