Datasheet

32/42 Doc ID 17116 Rev 3

7.5 CTRL_REG4 (23h)

7.6 CTRL_REG5 (24h)

Table 30. CTRL_REG4 register

BDU BLE FS1 FS0 - ST1 ST0 SIM

Table 31. CTRL_REG4 description

BDU Block Data Update. Default value: 0

(0: continous update; 1: output registers not updated until MSB and LSB

reading)

BLE Big/Little Endian Data Selection. Default value 0.

(0: Data LSB @ lower address; 1: Data MSB @ lower address)

FS1-FS0 Full Scale selection. Default value: 00

(00: 250 dps; 01: 500 dps; 10: 2000 dps; 11: 2000 dps)

ST1-ST0 Self Test Enable. Default value: 00

(00: Self Test Disabled; Other: See Table )

SIM SPI Serial Interface Mode selection. Default value: 0

(0: 4-wire interface; 1: 3-wire interface).

Table 32. Self test mode configuration

ST1 ST0 Self test mode

0 0 Normal mode

01Self test 0 (+)

(1)

1. DST sign (absolute value in Table 4)

10--

11Self test 1 (-)

(1)

Table 33. CTRL_REG5 register

BOOT FIFO_EN -- HPen INT1_Sel1 INT1_Sel0 Out_Sel1 Out_Sel0

Table 34. CTRL_REG5 description

BOOT Reboot memory content. Default value: 0

(0: normal mode; 1: reboot memory content)

FIFO_EN FIFO enable. Default value: 0

(0: FIFO disable; 1: FIFO Enable)

HPen High Pass filter Enable. Default value: 0

(0: HPF disabled; 1: HPF enabled. See Figure 20)

INT1_Sel1-

INT1_Sel0

INT1 selection configuration. Default value: 0

(See Figure 20)

Out_Sel1-

Out_Sel1

Out selection configuration. Default value: 0

(See Figure 20