Datasheet

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L3G4200D Output register mapping

Doc ID 17116 Rev 3 27/42

6 Output register mapping

The table given below provides a listing of the 8 bit registers embedded in the device and

the related addresses:

Table 18. Register address map

Name Type

Register address

Default Comment

Hex Binary

Reserved - 00-0E - -

WHO_AM_I r 0F 000 1111 11010011

Reserved - 10-1F - -

CTRL_REG1 rw 20 010 0000 00000111

CTRL_REG2 rw 21 010 0001 00000000

CTRL_REG3 rw 22 010 0010 00000000

CTRL_REG4 rw 23 010 0011 00000000

CTRL_REG5 rw 24 010 0100 00000000

REFERENCE rw 25 010 0101 00000000

OUT_TEMP r 26 010 0110 output

STATUS_REG r 27 010 0111 output

OUT_X_L r 28 010 1000 output

OUT_X_H r 29 010 1001 output

OUT_Y_L r 2A 010 1010 output

OUT_Y_H r 2B 010 1011 output

OUT_Z_L r 2C 010 1100 output

OUT_Z_H r 2D 010 1101 output

FIFO_CTRL_REG rw 2E 010 1110 00000000

FIFO_SRC_REG r 2F 010 1111 output

INT1_CFG rw 30 011 0000 00000000

INT1_SRC r 31 011 0001 output

INT1_TSH_XH rw 32 011 0010 00000000

INT1_TSH_XL rw 33 011 0011 00000000

INT1_TSH_YH rw 34 011 0100 00000000

INT1_TSH_YL rw 35 011 0101 00000000

INT1_TSH_ZH rw 36 011 0110 00000000

INT1_TSH_ZL rw 37 011 0111 00000000

INT1_DURATION rw 38 011 1000 00000000