Datasheet
Main digital blocks L3G4200D
16/42 Doc ID 17116 Rev 3
3 Main digital blocks
3.1 Block diagram
Figure 6. Block diagram
3.2 FIFO
The L3G4200D embeds a 32-slot, 16-bit data FIFO for each of the three output channels:
yaw, pitch, and roll. This allows consistent power saving for the system, as the host
processor does not need to continuously poll data from the sensor. Instead, it can wake up
only when needed and burst the significant data out from the FIFO. This buffer can work in
five different modes. Each mode is selected by the FIFO_MODE bits in the
FIFO_CTRL_REG. Programmable watermark level, FIFO_empty or FIFO_Full events can
be enabled to generate dedicated interrupts on the DRDY/INT2 pin (configured through
CTRL_REG3), and event detection information is available in FIFO_SRC_REG. The
watermark level can be configured to WTM4:0 in FIFO_CTRL_REG.
3.2.1 Bypass mode
In bypass mode, the FIFO is not operational and for this reason it remains empty. As
illustrated in Figure 7, only the first address is used for each channel. The remaining FIFO
slots are empty. When new data is available, the old data is overwritten.
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