Datasheet
Mechanical and electrical characteristics L3G4200D
12/42 Doc ID 17116 Rev 3
2.4 Communication interface characteristics
2.4.1 SPI - serial peripheral interface
Subject to general operating conditions for Vdd and Top.
Figure 4. SPI slave timing diagram
(b)
Table 7. SPI slave timing values
Symbol Parameter
Value
(1)
Unit
Min. Max.
tc(SPC) SPI clock cycle 100 ns
fc(SPC) SPI clock frequency 10 MHz
tsu(CS) CS setup time 5
ns
th(CS) CS hold time 8
tsu(SI) SDI input setup time 5
th(SI) SDI input hold time 15
tv(SO) SDO valid output time 50
th(SO) SDO output hold time 6
tdis(SO) SDO output disable time 50
1. Values are guaranteed at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results; not
tested in production.
b. Measurement points are done at 0.2·Vdd_IO and 0.8·Vdd_IO, for both input and output ports.
63&
&6
6',
6'2
W
VX&6
W
Y62
W
K62
W
K6,
W
VX6,
W
K&6
W
GLV62
W
F63&
06%,1
06%287
/6%287
/6%,1
!-V