Datasheet

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Preliminary data

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to

change without notice.

December 2010 Doc ID 17116 Rev 3 1/42

L3G4200D

MEMS motion sensor:

ultra-stable three-axis digital output gyroscope

Features

■ Three selectable full scales (250/500/2000

dps)

■ I

C/SPI digital output interface

■ 16 bit-rate value data output

■ 8-bit temperature data output

■ Two digital output lines (interrupt and data

ready)

■ Integrated low- and high-pass filters with user-

selectable bandwidth

■ Ultra-stable over temperature and time

■ Wide supply voltage: 2.4 V to 3.6 V

■ Low voltage-compatible IOs (1.8 V)

■ Embedded power-down and sleep mode

■ Embedded temperature sensor

■ Embedded FIFO

■ High shock survivability

■ Extended operating temperature range (-40 °C

to +85 °C)

■ ECOPACK

RoHS and “Green” compliant

Applications

■ Gaming and virtual reality input devices

■ Motion control with MMI (man-machine

interface)

■ GPS navigation systems

■ Appliances and robotics

Description

The L3G4200D is a low-power three-axis angular

rate sensor able to provide unprecedented

stablility of zero rate level and sensitivity over

temperature and time. It includes a sensing

element and an IC interface capable of providing

the measured angular rate to the external world

through a digital interface (I

C/SPI).

The sensing element is manufactured using a

dedicated micro-machining process developed by

STMicroelectronics to produce inertial sensors

and actuators on silicon wafers.

The IC interface is manufactured using a CMOS

process that allows a high level of integration to

design a dedicated circuit which is trimmed to

better match the sensing element characteristics.

The L3G4200D has a full scale of ±250/±500/

±2000 dps and is capable of measuring rates with

a user-selectable bandwidth.

The L3G4200D is available in a plastic land grid

array (LGA) package and can operate within a

temperature range of -40 °C to +85 °C.

LGA-16

(4x4x1.1 mm)

Table 1. Device summary

Order code Temperature range (°C) Package Packing

L3G4200D -40 to +85 LGA-16 (4x4x1.1 mm) Tray

L3G4200DTR -40 to +85 LGA-16 (4x4x1.1 mm) Tape and reel

www.st.com

Summary of content (42 pages)

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L3G4200D MEMS motion sensor: ultra-stable three-axis digital output gyroscope Preliminary data Features ■ Three selectable full scales (250/500/2000 dps) ■ I2C/SPI digital output interface ■ 16 bit-rate value data output ■ 8-bit temperature data output ■ Two digital output lines (interrupt and data ready) ■ Integrated low- and high-pass filters with userselectable bandwidth Description ■ Ultra-stable over temperature and time ■ Wide supply voltage: 2.4 V to 3.
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L3G4200D Contents 1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 2 Mechanical and electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . .
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L3G4200D 5.2.2 SPI write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.2.3 SPI read in 3-wire mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6 Output register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.1 WHO_AM_I (0Fh) . . . . . . . . . . . . . . . . . . . . . . . . .
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List of tables L3G4200D List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48.
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L3G4200D Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. List of tables INT1_CFG description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_SRC register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INT1_SRC description . . . . . . . . . . . . . .
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List of figures L3G4200D List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. 6/42 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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L3G4200D 1 Block diagram and pin description Block diagram and pin description Figure 1. Block diagram +Ω x,y,z X+ CHARGE AMP Y+ MIXER LOW-PASS FILTER Z+ Z- A D C 1 M U X Y- D I G I T A L X- DRIVING MASS Feedback loop TRIMMING CIRCUITS REFERENCE FIFO T E M P E R A T U R E S E N S O R F I L T E R I N G I2C SPI CS SCL/SPC SDA/SDO/SDI SDO A D C 2 INT1 CONTROL LOGIC & INTERRUPT GEN.
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Block diagram and pin description Table 2.
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L3G4200D Block diagram and pin description Table 3.
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Mechanical and electrical characteristics L3G4200D 2 Mechanical and electrical characteristics 2.1 Mechanical characteristics Table 4. Mechanical characteristics @ Vdd = 3.0 V, T = 25 °C, unless otherwise noted(1) Symbol Parameter Test condition Min. Typ.(2) Max. Unit ±250 FS Measurement range User-selectable ±500 dps ±2000 So SoDr DVoff OffDr NL DST Rn FS = 250 dps 8.75 FS = 500 dps 17.
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L3G4200D Mechanical and electrical characteristics 2.2 Electrical characteristics Table 5. Electrical characteristics @ Vdd =3.0 V, T=25 °C, unless otherwise noted(1) Symbol Vdd Vdd_IO Idd Parameter Test condition Supply voltage I/O pins supply voltage (3) Min. Typ.(2) Max. Unit 2.4 3.0 3.6 V Vdd+0.1 V 1.71 Supply current 6.1 mA IddSL Supply current in sleep mode(4) Selectable by digital interface 1.
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Mechanical and electrical characteristics L3G4200D 2.4 Communication interface characteristics 2.4.1 SPI - serial peripheral interface Subject to general operating conditions for Vdd and Top. Table 7. SPI slave timing values Value(1) Symbol Parameter Unit Min.
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L3G4200D Mechanical and electrical characteristics I2C - inter IC control interface 2.4.2 Subject to general operating conditions for Vdd and Top. Table 8. I2C slave timing values I2C standard mode(1) Symbol I2C fast mode (1) Parameter f(SCL) Unit SCL clock frequency Min Max Min Max 0 100 0 400 tw(SCLL) SCL clock low time 4.7 1.3 tw(SCLH) SCL clock high time 4.0 0.6 tsu(SDA) SDA setup time 250 100 th(SDA) SDA data hold time kHz µs 0 ns 3.45 0 0.
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Mechanical and electrical characteristics 2.5 L3G4200D Absolute maximum ratings Any stress above that listed as “Absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 9. Absolute maximum ratings Symbol Ratings Maximum value Unit Vdd Supply voltage -0.3 to 4.
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L3G4200D Mechanical and electrical characteristics 2.6 Terminology 2.6.1 Sensitivity An angular rate gyroscope is a device that produces a positive-going digital output for counterclockwise rotation around the sensitive axis considered. Sensitivity describes the gain of the sensor and can be determined by applying a defined angular velocity to it. This value changes very little over temperature and time. 2.6.
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Main digital blocks L3G4200D 3 Main digital blocks 3.1 Block diagram Figure 6. Block diagram /UT?3EL ,0& !$# ,0& (0& (0EN $ATA2EG &)&/ X X ) # 30) ).4?3EL )NTERRUPT GENERATOR 3#2 2%' #/.& 2%' ).4 !- V 3.2 FIFO The L3G4200D embeds a 32-slot, 16-bit data FIFO for each of the three output channels: yaw, pitch, and roll. This allows consistent power saving for the system, as the host processor does not need to continuously poll data from the sensor.
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L3G4200D Main digital blocks Figure 7. Bypass mode XI YI ZI EMPTY X Y I Z X Y Z X Y Z X Y Z !- V 3.2.2 FIFO mode In FIFO mode, data from the yaw, pitch, and roll channels are stored in the FIFO. A watermark interrupt can be enabled (I2_WMK bit in CTRL_REG3), which is triggered when the FIFO is filled to the level specified in the WTM 4:0 bits of FIFO_CTRL_REG. The FIFO continues filling until it is full (32 slots of 16-bit data for yaw, pitch, and roll).
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Main digital blocks L3G4200D older data as the new data arrives. Programmable watermark level events can be enabled to generate dedicated interrupts on the DRDY/INT2 pin (configured through CTRL_REG3). Stream mode is represented in Figure 9. Figure 9. Stream mode XI YI ZI X Y Z X Y Z X Y Z X Y Z X Y Z !- V 3.2.
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L3G4200D 3.2.5 Main digital blocks Stream-to-FIFO mode In stream-to-FIFO mode, data from yaw, pitch, and roll measurements are stored in the FIFO. A watermark interrupt can be enabled on pin DRDY/INT2, setting the I2_WTM bit in CTRL_REG3, which is triggered when the FIFO is filled to the level specified in the WTM4:0 bits of FIFO_CTRL_REG. The FIFO continues filling until full (32 slots of 16-bit data for yaw, pitch, and roll). When full, the FIFO discards the older data as the new data arrives.
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Application hints 4 L3G4200D Application hints Figure 12.
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L3G4200D 5 Digital interfaces Digital interfaces The registers embedded in the L3G4200D may be accessed through both the I2C and SPI serial interfaces. The latter may be software-configured to operate either in 3-wire or 4-wire interface mode. The serial interfaces are mapped onto the same pins. To select/exploit the I2C interface, the CS line must be tied high (i.e., connected to Vdd_IO). Table 11.
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Digital interfaces 5.1.1 L3G4200D I2C operation The transaction on the bus is started through a START (ST) signal. A START condition is defined as a HIGH to LOW transition on the data line while the SCL line is held HIGH. After this has been transmitted by the master, the bus is considered busy.
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L3G4200D Digital interfaces Table 15. Master Transfer when master is writing multiple bytes to slave ST SAD + W Slave SAK Table 16. Master ST SAD + W DATA SAK SUB SAK SAK SP SAK SR SAD + R SAK NMAK SAK SP DATA Transfer when master is receiving (reading) multiple bytes of data from slave Master ST SAD+W Slave DATA Transfer when master is receiving (reading) one byte of data from slave Slave Table 17.
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Digital interfaces L3G4200D Figure 13. Read and write protocol CS SPC SDI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 RW MS AD5 AD4 AD3 AD2 AD1 AD0 SDO DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 CS is the serial port enable and is controlled by the SPI master. It goes low at the start of the transmission and returns to high at the end. SPC is the serial port clock and is controlled by the SPI master. It is stopped high when CS is high (no transmission). SDI and SDO are, respectively, the serial port data input and output.
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L3G4200D Digital interfaces The SPI read command is performed with 16 clock pulses. A multiple byte read command is performed by adding blocks of 8 clock pulses to the previous one. Bit 0: READ bit. The value is 1. Bit 1: MS bit. When 0, do not increment address; when 1, increment address in multiple reading. Bit 2-7: address AD(5:0). This is the address field of the indexed register. Bit 8-15: data DO(7:0) (read mode). This is the data that is read from the device (MSb first). Bit 16-... : data DO(...-8).
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Digital interfaces L3G4200D Figure 17. Multiple byte SPI write protocol (2-byte example) CS SPC SDI DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DI15 DI14 DI13 DI12 DI11 DI10 DI9 DI8 RW MS AD5 AD4 AD3 AD2 AD1 AD0 5.2.3 SPI read in 3-wire mode 3-wire mode is entered by setting the SIM (SPI serial interface mode selection) bit to 1 in CTRL_REG2. Figure 18.
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L3G4200D 6 Output register mapping Output register mapping The table given below provides a listing of the 8 bit registers embedded in the device and the related addresses: Table 18.
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Output register mapping L3G4200D Registers marked as Reserved must not be changed. The writing to those registers may cause permanent damages to the device. The content of the registers that are loaded at boot should not be changed. They contain the factory calibration values. Their content is automatically restored when the device is powered-up.
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L3G4200D 7 Register description Register description The device contains a set of registers which are used to control its behavior and to retrieve acceleration data. The registers address, made of 7 bits, is used to identify them and to write the data through serial interface. 7.1 WHO_AM_I (0Fh) Table 19. WHO_AM_I register 1 1 0 1 0 0 1 1 BW0 PD Zen Yen Xen Device identification register. 7.2 CTRL_REG1 (20h) Table 20. DR1 Table 21.
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Register description Table 22. L3G4200D DR and BW configuration setting (continued) DR <1:0> BW <1:0> ODR [Hz] Cut-Off 01 00 200 12.5 01 01 200 25 01 10 200 50 01 11 200 70 10 00 400 20 10 01 400 25 10 10 400 50 10 11 400 110 11 00 800 30 11 01 800 35 11 10 800 50 11 11 800 110 Combination of PD, Zen, Yen, Xen are used to set device in different modes (power down / normal / sleep mode) according with the following table. Table 23.
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L3G4200D Register description Table 26. High pass filter mode configuration HPM1 High Pass filter Mode 0 0 Normal mode (reset reading HP_RESET_FILTER) 0 1 Reference signal for filtering 1 0 Normal mode 1 1 Autoreset on interrupt event Table 27. 7.4 HPM0 High pass filter cut off frecuency configuration [Hz] HPCF3 ODR= 100 Hz ODR= 200 Hz ODR= 400 Hz ODR= 800 Hz 0000 8 15 30 56 0001 4 8 15 30 0010 2 4 8 15 0011 1 2 4 8 0100 0.5 1 2 4 0101 0.2 0.
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Register description 7.5 L3G4200D CTRL_REG4 (23h) Table 30. CTRL_REG4 register BDU BLE Table 31. FS1 FS0 - ST1 ST0 SIM CTRL_REG4 description BDU Block Data Update. Default value: 0 (0: continous update; 1: output registers not updated until MSB and LSB reading) BLE Big/Little Endian Data Selection. Default value 0. (0: Data LSB @ lower address; 1: Data MSB @ lower address) FS1-FS0 Full Scale selection.
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L3G4200D Register description Figure 19. INT1_Sel and Out_Sel configuration block diagram Out_Sel <1:0> 00 01 0 LPF2 ADC LPF1 HPF 10 11 DataReg FIFO 32x16x3 1 INT1_Sel <1:0> HPen 10 11 01 Interrupt generator 00 AM07949V2 Table 35.
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Register description 7.7 L3G4200D REFERENCE/DATACAPTURE (25h) Table 37. Ref7 REFERENCE register Ref6 Table 38. Ref3 Ref2 Ref1 Ref0 Reference value for Interrupt generation. Default value: 0 OUT_TEMP (26h) Table 39. Temp7 OUT_TEMP register Temp6 Table 40. Temp5 Temp4 Temp3 Temp2 Temp1 Temp0 OUT_TEMP register description Temp7-Temp0 7.9 Ref4 REFERENCE register description Ref 7-Ref0 7.8 Ref5 Temperature data. STATUS_REG (27h) Table 41. ZYXOR STATUS_REG register ZOR Table 42.
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L3G4200D 7.10 Register description OUT_X_L (28h), OUT_X_H (29h) X-axis angular rate data. The value is expressed as two’s complement. 7.11 OUT_Y_L (2Ah), OUT_Y_H (2Bh) Y-axis angular rate data. The value is expressed as two’s complement. 7.12 OUT_Z_L (2Ch), OUT_Z_H (2Dh) Z-axis angular rate data. The value is expressed as two’s complement. 7.13 FIFO_CTRL_REG (2Eh) Table 43. REFERENCE register FM2 FM1 Table 44.
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Register description Table 47. 7.15 L3G4200D FIFO_SRC register description (continued) EMPTY FIFO empty bit. ( 0: FIFO not empty; 1: FIFO empty) FSS4-FSS1 FIFO stored data level INT1_CFG (30h) Table 48. AND/OR Table 49. INT1_CFG register LIR ZHIE ZLIE YHIE YLIE XHIE XLIE INT1_CFG description AND/OR AND/OR combination of Interrupt events. Default value: 0 (0: OR combination of interrupt events 1: AND combination of interrupt events LIR Latch Interrupt Request.
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L3G4200D Register description Table 51. INT1_SRC description IA Interrupt active. Default value: 0 (0: no interrupt has been generated; 1: one or more interrupts have been generated) ZH Z high. Default value: 0 (0: no interrupt, 1: Z High event has occurred) ZL Z low. Default value: 0 (0: no interrupt; 1: Z Low event has occurred) YH Y high. Default value: 0 (0: no interrupt, 1: Y High event has occurred) YL Y low. Default value: 0 (0: no interrupt, 1: Y Low event has occurred) XH X high.
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Register description 7.20 L3G4200D INT1_THS_YL (35h) Table 58. THSR7 Table 59. INT1_THS_YL register THSY6 - Table 61. THSY2 THSY1 THSY0 THSZ9 THSZ8 THSZ1 THSZ0 D1 D0 Interrupt threshold. Default value: 0000 0000 INT1_THS_ZH register THSZ14 THSZ13 THSZ12 THSZ11 THSZ10 INT1_THS_ZH description THSZ14 - THSZ9 Interrupt threshold. Default value: 0000 0000 INT1_THS_ZL (37h) Table 62. THSZ7 Table 63.
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L3G4200D Register description Wait =’1’: if signal crosses the selected threshold, the interrupt falls only after the duration has counted number of samples at the selected data rate, written into the duration counter register. Figure 20. Wait disabled Figure 21.
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Package information 8 L3G4200D Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at www.st.com. ECOPACK is an ST trademark. Figure 22.
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L3G4200D 9 Revision history Revision history Table 66. Document revision history Date Revision Changes 01-Apr-2010 1 Initial release. 03-Sep-2010 2 Complete datasheet review. 22-Dec-2010 3 Inserted Section 6: Output register mapping and Section 7: Register description.
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L3G4200D Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale.