MICROCOMPUTER MN101C00 MN101C115/117 LSI User’s Manual Pub. No.
PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd. The other corporation names,logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations.
How to Read This Manual The MN101C11x incorporates more than one ROM/RAM to meet a variety of applications. An EPROM version as well as a Mask ROM version is available so users can write a program by themselves.
■ Manual Configuration Each section of this manual consists of a title, summary, main text, supplemental information, precautions and warnings. The layout and definition of each section are shown below. Chapter 4 Timer Functions Subtitle Sub-subtitle The smallest block in this manual. 4-3 16-bit Timer Operation (timer 4) Summary Introduction to the section. 4-3-1 Overview Timer 4 is a 16-bit programmable counter that can be used as an event counter.
■ Finding Desired Information This manual provides four methods for finding desired information quickly and easily. (1) (2) (3) (4) Consult the index at the front of the manual to locate the beginning of each section. Consult the table of contents at the front of the manual to locate desired titles. Consult the list of figures at the front of the manual to locate illustrations and charts by title name.
?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@
?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@
Contents Chapter 1 Overview 1-1 Product Overview...........................................................................................................2 1-1-1 Overview ..........................................................................................................2 1-1-2 Product Summary .............................................................................................2 1-2 Hardware Functions .....................................................................................
Chapter 3 Port Functions 3-1 Overview ......................................................................................................................38 3-2 Port Control Registers ..................................................................................................41 3-2-1 Overview ........................................................................................................41 3-2-2 I/O Port Control Registers ...................................................................
Chapter 5 Serial Functions 5-1 Overview ......................................................................................................................92 5-2 Synchronous Serial Interface .......................................................................................94 5-2-1 Overview ........................................................................................................94 5-2-2 Setup and Operation .............................................................................
Appendices 8-1 EPROM Versions .......................................................................................................130 8-1-1 Overview ......................................................................................................130 8-1-2 Cautions on Use............................................................................................131 8-1-3 Erasing Written Data in Windowed Packages ..............................................
?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@
Chapter 1 Overview 1-1 Product Overview 1-1-1 Overview The MN101C00 series of 8-bit single-chip microcomputers incorporate several types of peripheral functions. This chip series is well suited for VCR, MD, TV, CD, LD, printer, telephone, home automation, pager, air conditioner, PPC, remote control, fax machine, musical instrument, and other applications. The MN101C117 has an internal 16 KB of ROM and 512 bytes of RAM.
Chapter 1 Overview 1-2 Hardware Functions ROM/RAM Size: Internal ROM∗2 16,384×8-bit*3 Internal RAM∗2 512×8-bit Machine Cycles: High speed mode 0.10µs/20MHz (4.5V to 5.5V) 0.25µs/8MHz(2.7V to 5.5V) 1.00µs/2MHz(2.0V to 5.5V) Low speed mode 125µs/32KHz(2.0V to 5.
Chapter 1 Overview Timers 2 and 3 can be cascaded. Timer 4 16-bit timer Square wave output, 16-bit PWM output are possible. Clock source: fosc, fs/4, fs/16, TM4IO pin input Input capture function Time base timer Clock source: fosc, fs/4, fx*4, fx/213*4 or fosc/213 XIOat 32kHz, can be set to measure one minute intervals*4 Can operate independently as timer 5 (8-bit timer).
Chapter 1 Overview 1-3 Pins 1-3-1 Pin Diagram 1 42 2 41 3 40 4 39 5 38 7 8 9 10 11 12 13 14 15 16 17 MN101C117/115 6 ４２-ＳＤＩＰ TXD,SBO0,P00 RXD,SBI0,P01 SBT0,P02 BUZZER, P06 RMOUT,P10 P11 TM2IO,P12 TM3IO,P13 TM4IO,P14 IRQ0,P20 IRQ1,P21 IRQ2,P22 P60 P61 P62 P63 P64 P65 P66 P67 NRST, P27 37 36 35 34 33 32 31 30 29 28 27 26 18 25 19 24 20 23 21 22 VSS OSC1 OSC2 VDD PA7,AN7 PA6,AN6 PA5,AN5 PA4,AN4 PA3,AN3 PA2,AN2 PA1,AN1 PA0,AN0 P80,LED0 P81,LED1 P82,LED2 P83,LED3 P84,LED4 P85,LED5 P86,L
P84,LED4 P85,LED5 P86,LED6 P87,LED7 MMOD P27,NRST P70 P67 P66 P65 P64 Chapter 1 Overview 44 43 42 41 40 39 38 37 36 35 34 1 33 2 32 3 31 4 30 5 29 6 28 7 ４４-ＱＦＰ 27 8 26 9 25 10 24 11 23 12 13 14 15 16 17 18 19 20 21 22 MN101C117/115 P63 P62 P61 P60 P22,IRQ2 P21,IRQ1,SENS P20,IRQ0 P14,TM4IO P13,TM3IO P12,TM2IO P11 AN7,PA7 VDD OSC2 OSC1 VSS NC TXD,SBO0,P00 RXD,SBI0,P01 SBT0,P02 BUZZER, P06 RMOUT,P10 LED3,P83 LED2,P82 LED1,P81 LED0,P80 AN0,PA0 AN1,PA1 AN2,PA2 AN3,PA3 AN4,PA4 AN5,PA5 AN6,PA6 Figure 1-3-2
P84,LED4 P85,LED5 P86,LED6 P87,LED7 MMOD P27,NRST P71 P70 P67 P66 P65 P64 Chapter 1 Overview 48 47 46 45 44 43 42 41 40 39 38 37 1 36 2 35 3 34 4 33 5 32 6 31 30 7 ４８-ＱＦＨ 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 MN101C117/115 P63 P62 P61 P60 P23,IRQ3 P22,IRQ2 P21,IRQ1,SENS P20,IRQ0 P14,TM4IO P13,TM3IO P12,TM2IO P11 AN7,PA7 VDD OSC2 OSC1 VSS XI XO TXD,SBO0,P00 RXD,SBI0,P01 SBT0,P02 BUZZER,P06 RMOUT,P10 LED3,P83 LED2,P82 LED1,P81 LED0,P80 NC AN0,PA0 AN1,PA1 AN2,PA2 AN3,PA3 AN4,PA4
Chapter 1 Overview 1-3-2 Pin Function Summary *The pin numbers in the list correspond to the QFH package(Refer to Figure 1-3-3 Pin connection.) Be careful when using SDIP and QFP packages. Table 1-3-1 Pin Function Summary (1/4) Pin No. Name Type Dual Function Function Description 17 14 VSS VDD – Power supply pins Apply 2.0V to 5.5V to VDD and 0V to VSS.
Chapter 1 Overview Table 1-3-1 Pin Function Summary (2/4) Pin No. Name Type Dual Function Function I/O port 1 Description 24 to 28 P10 to P14 I/O RMOUT, TM2IO to TM4IO 29 to 32 P20 to P23 Input IRQ0, Input port 2 IRQ1(SENS), IRQ2 to 3 43 P27 Input RST 33 to 40 P60 to P67 I/O I/O port 6 8-bit CMOS tri-state I/O port. Each bit can be set individually as either an input or output by the P6DIR register. A pull-up resistor for each bit can be selected individually by the P6PLU register.
Chapter 1 Overview Table 1-3-1 Pin Function Summary (3/4) Pin No. Name Type Dual Function 20 TXD Output SBO0(P00) 21 RXD Input SBI0(P01) 20 SBO0 Output 21 SBI0 Input 22 SBT0 I/O 22 Buzzer I/O In the serial interface in UART mode, these pins are configured as the receive data input pin and transmit data output pin. A push-pull or n-channel open-drain configuration can be selected for TXD by the SC0MD1 register. Pull-up resistors can be selected by the P0PLU register.
Chapter 1 Overview Table 1-3-1 Pin Function Summary (4/4) Pin No. Name Type Dual Function Function Description Test mode switch input pin This pin sets the test mode. Must be set to L. P20, P21(SENS), P22,P23 External interrupt input pins The valid edge for these external interrupt input pins can be selected with the IRQnICR registers. IRQ1 is an external interrupt pin that is able to determine AC zero crossings. It can also be used as a normal external interrupt.
Chapter 1 Overview 1-4 Overview of Functions RAM 512 bytes 8-bit timer 2 External interrupt 8-bit timer 3 Serial interface 0 16-bit timer 4 Time base timer 5 A/D conversion Watchdog timer Port 6 ROM 16 KB Port 7 VSS VDD RST MMOD CPU MN101C00 Port 8 Port 1 Port 2 OSC2 OSC1 XO System clock oscillator Sub-clock oscillator Port A TXD,SBO0,P00 RXD,SBI0,P01 SBT0,P02 P06 RMOUT,P10 P11 TM2IO,P12 TM3IO,P13 TM4IO,P14 IRQ0,P20 SENS,IRQ1,P21 IRQ2,P22 IRQ3,P23 RST,P27 AN7,PA7 AN6,PA6 AN5,PA5 AN4
Chapter 1 Overview 1-5 Electrical Characteristics Contents Model MN101C117/115 Classification CMOS integrated circuit Use General purpose Function CMOS, 8-bit, single-chip microcomputer This LSI manual describes standard specifications. Before using the LSI, please obtain product specifications from the sales office. 1-5-1 Absolute Maximum Ratings Parameter Symbol ∗2 ∗3 Rating Unit 1 Supply voltage VDD –0.3 to +7.
Chapter 1 Overview 1-5-2 Operating Conditions Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V Parameter Symbol Rating Conditions MIN TYP Unit MAX Supply voltage 1 VDD1 fosc ≤ 20.0MHz 4.5 5.5 2 VDD2 fosc ≤ 8.39MHz 2.7 5.5 VDD3 fosc ≤ 2.00MHz 2.0 5.5 fx = 32.768kHz 2.0 5.5 STOP mode 1.8 5.5 Supply voltage 3 during operation 4 VDD4 5 Voltage to maintain RAM data VDD5 Operating speed *1 V ∗2 6 7 tc1 VDD=4.5 to 5.5V 0.100 tc2 VDD=2.7 to 5.5V 0.238 VDD=2.0 to 5.5V 1.00 VDD=2.
Chapter 1 Overview Parameter Symbol Rating Conditions MIN TYP Unit MAX External clock input 1 OSC1 (OSC2 is unconnected) 18 Clock frequency fOSC 19 High level pulse width∗ twh 1 ∗1 ∗ 20 Low level pulse width twl 1 21 Rise time twr 1 1.0 20.0 20.0 30.0 20.0 30.0 Fig. 1-5-3 ns 5.0 Fig. 1-5-3 22 Fall time MHz ns twf 1 5.0 External clock input 2 XI (XO is unconnected)*2 23 Clock frequency 24 High level pulse width fx ∗ 32.768 twh 2 twl 2 26 Rise time twr 2 Fig. 1-5-4 µs 3.
Chapter 1 Overview 0.9VDD 0.1VDD twh1 twr1 twl1 twf1 Figure 1-5-3 OSC1 Timing Chart 0.9VDD 0.
Chapter 1 Overview 1-5-3 DC Characteristics Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V Parameter Symbol Rating Conditions MIN Supply current (no load at output) 1 Supply current 2 during operation 3 4 Supply current during HALT mode 5 6 Supply current during STOP mode 7 Notes: ∗1 MAX 25 60 mA IDD2 IDD3 TYP ∗1 fosc=20.0MHz,VDD=5V IDD1 Unit fosc=8.39MHz,VDD=5V *2 IDD5 *2 10 25 fx =32.768kHz,VDD=3V 100 fx =32.
Chapter 1 Overview Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V Parameter Symbol Rating Conditions MIN TYP Unit MAX Input pin 1 MMOD 8 Input high voltage 1 VIH1 9 Input high voltage 2 VIH2 10 Input low voltage 1 VIL1 11 Input low voltage 2 VIL2 VDD=4.5 to 5.5V 12 Input leakage current ILK1 VIN = 0 to VDD VDD=4.5 to 5.5V 0.8VDD VDD V 0.7VDD VDD V 0 0.2VDD V 0 0.3VDD V ±10 µA Input pin 2 P20, P22~P23 (Schmitt trigger input) 13 Input high voltage VIH3 0.
Chapter 1 Overview SENS pin 27 trs Rise time 30 Fig. 1-5-5 28 tfs Fall time µs 30 ← trs→ ← tfs → VDD VDHH VDLH Input voltage level 1→ (Input) VDHL VDLL VSS Input voltage level 2→ (Output) Figure 1-5-5 Operation of AC Zero-Cross Detection Circuit Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V Parameter Symbol Rating Conditions MIN TYP Unit MAX Input pin 4 PA0~PA7 29 Input high voltage 1 VIH5 30 Input high voltage 2 VIH6 31 Input low voltage 1 VIL5 32 Input low voltage 2 VIL6 VDD=4.
Chapter 1 Overview Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V Parameter Symbol Rating Conditions MIN TYP Unit MAX I/O pin 5 P27 (RST) 36 Input high voltage VIH7 0.9VDD VDD V 37 Input low voltage VIL7 0 0.2VDD V 38 Input leakage current ILK7 VIN = 0 to VDD ±10 µA Iih VDD=5V, VIN=1.5V Pull-up resistor built in -300 µA 39 Input high current -30 -100 I/O pin 6 P00 to P06, P10 to P14 (Schmitt trigger input) 40 Input high voltage VIH8 0.8VDD VDD V 41 Input low voltage VIL8 0 0.
Chapter 1 Overview Ta=–40 to +85°C VDD=2.0 to 5.5V VSS=0V Parameter Symbol Rating Conditions MIN TYP Unit MAX I/O pin 9 P80~P87 63 Input high voltage 1 VIH13 64 Input high voltage 2 VIH14 65 Input low voltage 1 VIL113 66 Input low voltage 2 VIL14 VDD=4.5 to 5.5V 67 Input leakage current ILK13 VIN=0 to VDD 68 Input high current IIH13 VDD=5V, VIN=1.5V Pull-up resistor ON –30 69 Output high voltage VOH13 VDD = 5V, IOH = –0.5mA 4.
Chapter 1 Overview 1-6 Option 1-6-1 ROM Option The product equipped with this LSI or an EPROM with this LSI controls the oscillation mode after resetting as well as the runaway-detection watchdog timer, using bits 2 to 0 of the last address of the built-in ROM.
Chapter 1 Overview 1-6-2 Option Form Date: SE No. Model Name MN101C Customer Approval 1. Oscillation mode Type A Type B Note: Type A: Operation begins from the reset cycle in the NORMAL mode. Type B: Operation begins from the reset cycle in the SLOW mode. 2. Watchdog timer period setting Detection Period 16 Selection 3. Package selection Package fs/2 SDIP042-P-0600 fs/218 QFP044-P-1010 20 fs/2 Selection QFH048-P-0707 Not used Contents of mask option are subject to change.
Chapter 1 Overview 1-7 Outline Drawings Package code: SDIP042-P-0600 Unit: mm Body Material: Epoxy Resin Lead Material:Fe Ni Lead Finish Method:Soldering dip Figure 1-7-1 42-SDIP The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office.
Chapter 1 Overview Package code: QFP044-P-1010 Unit: mm Body Material: Epoxy Resin Lead Material:Fe Ni Lead Finish Method:Soldering dip Figure 1-7-2 44-QFP The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office.
Chapter 1 Overview Package code: QFH048-P-0707 Unit: mm Material: Epoxy Resin Lead Material:Fe Ni-42 Alloy Lead Finish Method:Soldering dip Figure 1-7-3 48-QFH The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office.
?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@
Chapter 2 Basic CPU Functions 2-1 Overview Basic CPU functions are in conformance with the MN101C00 series manual (architecture manual). This chapter describes specifications unique to the MN101C117/115.
Chapter 2 Basic CPU Functions 2-2-2 Special Function Registers Memory control register(MEMCTR) is a 4-bit register which set up the base Table 2-2-1 Register Map 1 2 3 4 5 6 7 8 9 A B C D E F CPU mode, memory control Port output 03F1X P0OUT P1OUT P2OUT P6OUT P7OUT P8OUT 03F2X P0IN P1IN P2IN P6IN P7IN P8IN 03F3X P0DIR P1DIR P6DIR P7DIR P8DIR P1OMD PAIMD 03F4X P0PLU P1PLU P2PLU P6PLU P7PLUD P8PLU Port input PAIN I/O mode control I/O ports 0 03F0X CPUM MEMCTR WDCTR DLYCTR Resist
Chapter 2 Basic CPU Functions 2-3 Bus Interface 2-3-1 Overview The MN101C117, unlike other MN101C series microcomputers, does not support memory expansion mode and processor mode. 2-3-2 Control Registers The memory control register is a four-bit register that sets up wait-count at a time of access to a base address of interrupt vector table and a special register zone. (1) Memory control register(MEMCTR) 7 MEMCTR 6 5 IOW1 IOW0 IVBA 4 3 2 1 0 (at reset: 11001011) IRWE Must be set to 11.
Chapter 2 Basic CPU Functions 2-4 Interrupts 2-4-1 Accepting and Returning from Interrupts In the MN101C00 series, when an interrupt is accepted, the hardware pushes the program's return address and the PSW, on to the stack, and branches to the beginning address of the interrupt program specified by the interrupt vector table. ■ Operation when Interrupt is Accepted 1. 2. The stack pointer (SP) contents are update. (SP–6 → SP) The handy address register (HA) is pushed on to the stack. 3.
Chapter 2 Basic CPU Functions ■ Operation when Returning from Interrupt After the program POPs the register and other values saved by the interrupt service routine, an RTI instruction is implemented to return to the program that was being executed when the interrupt was received. The processing sequence for the return from interrupt instruction, RTI, is listed below. 32 Interrupts 1. 2. 3. The processor status word (PSW) is pulled from the stack.
Chapter 2 Basic CPU Functions 2-4-2 Interrupt Sources and Vector Addresses In addition to reset, there are 20 interrupt vectors that indicate the starting addresses of interrupt programs. These vectors are located in the 80-byte ROM address area X'04004' to X'04053'.
Chapter 2 Basic CPU Functions 2-4-3 Interrupt Control Registers Interrupt control registers consist of the following: a non-maskable interrupt control register (NMICR), external interrupt control registers (IRQnICR), and internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR). Be sure to use the MIE flag of the PSW register to write to all interrupt control registers.
Chapter 2 Basic CPU Functions ■ Internal Interrupt Control Registers (TMnICR, TBICR, SCOICR, ATCICR, ADICR) The internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR) control the interrupt levels of internal interrupts, timer interrupts, serial interrupts, A/D conversion complete interrupts, and interrupt request/enable. Be sure to disable all interrupts before writing to these registors.
Chapter 2 Basic CPU Functions 2-5 Reset The CPU contents are reset and registers are initialized when the RST pin is pulled to low. ■ Initiating a Reset There are two methods to initiate a reset. For the reset to be stable, the low pulse must be maintained for at least four clock cycles. However, it is important to minimize noise, since a reset may occur in a smaller number of clock cycles. (1) Drive the RST pin low for at least four clock cycles.
?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@
Chapter 3 Port Functions 3-1 Overview A total of 39 pins on the MN101C117, including those shared with special function pins, are allocated for the 7 ports of P0 to P2, P6 to P8, and PA. Each I/O port is assigned according to the special function register area in memory. I/O ports are operated in byte or bit units in the same way as RAM.
Chapter 3 Port Functions ■ Port 1 (P1) 5-bit CMOS tri-state I/O port. Table 3-1-3 Port 1 Functions Pin Name Type P10 to P14 I/O Dual Function Description RMOUT, Each bit can be set individually as either an input or TM2IO to TM4IO output by the P1DIR register. A pull-up resistor for each bit can be selected individually by the P1PLU register. At reset, the input mode is selected and pull-up resistors are disabled (high impedance output). ■ Port 2 (P2) 4-bit CMOS tri-state input port.
Chapter 3 Port Functions ■ Port 7 (P7) 8-bit CMOS tri-state I/O port. Table 3-1-6 Port 7 Functions Pin Name Type P70 to P71 I/O Dual Function Description Each individual bit can be switched to an input or output by the P7DIR register. A pull-up or pull-down resistor for each bit can be selected individually by the P7PLU register. However, pull-up and pull-down resistors cannot be mixed. At reset, the input mode pull-up resisters are disabled . 42-SDIP has no pins of P70,P71. 44-QFP has no pin of p71.
Chapter 3 Port Functions 3-2 Port Control Registers 3-2-1 Overview 28 registers control the I/O ports. See table 3-2-1.
Chapter 3 Port Functions Table 3-2-1 I/O Port Control Registers (2/2) Name 42 Port Control Registers Address R/W P6DIR X'03F36' R/W Port 6 direction control register P7DIR X'03F37' R/W Port 7 direction control register P8DIR X'03F38' R/W Port 8 direction control register P1OMD X'03F39' R/W Port 1 output mode register PAIMD X'03F3A' R/W Port A input mode register P0PLU X'03F40' R/W Port 0 pull-up control register P1PLU X'03F41' R/W Port 1 pull-up control register P2PLU X'03
Chapter 3 Port Functions 7 6 P0OUT6 P0OUT P1OUT P2OUT P0IN 5 4 3 2 1 0 P0OUT2 P0OUT1 P0OUT0 (at reset: -0---000) P1OUT4 P1OUT3 P1OUT2 P1OUT1 P1OUT0 (at reset: ---00000) (at reset: 1-------) P2OUT7 P0IN6 P0IN2 P0IN1 P0IN0 (at reset: -X---XXX) P1IN P1IN4 P1IN3 P1IN2 P1IN1 P1IN0 P2IN P2IN2 P2IN1 P2IN0 (at reset: ----XXX) P0DIR2 P0DIR1 P0DIR0 (at reset: -0---000) P1DIR P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIR0 (at reset: ---00000) P1OMD P14TCO P13TCO P12TCO P10TCO (at reset: ---00000
Chapter 3 Port Functions 7 6 5 4 3 2 1 0 P7OUT P7OUT1 P7OUT0 (at reset: - - - - - - 00) P8OUT P8OUT7 P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUT0 (at reset: 00000000) P7IN P7IN1 P7IN0 (at reset: - - - - - - XX) P8IN P8IN7 P8IN6 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P8IN0 (at reset: XXXXXXXX) PAIN PAIN7 PAIN6 PAIN5 PAIN4 PAIN3 PAIN2 PAIN1 PAIN0 (at reset: XXXXXXXX) P7DIR P7DIR1 P7DIR0 P8DIR P8DIR7 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIR0 (at reset: 00000000) PAIMD PAAIN7 PAA
Chapter 3 Port Functions 3-2-2 I/O Port Control Registers This section describes the special function registers that control the MN101C117's I/O ports. ■ Data Registers • PnOUT registers Data registers to output to the ports. Data written to these registers is output from the ports. 0 Low (Vss level) is output. 1 High (Vdd level) is output. • PnIN registers Data registers to input data from the ports. The value of data at the pins can be input by reading these registers. These are read-only registers.
Chapter 3 Port Functions ■ Port Output/Input Mode Registers • PnOMD/PnIMD registers These register settings determine whether the port pins(P10 to P14, PA0 to PA5) are used as I/O ports or as special function pins (dual function). If the special (dual) functions used, the PnDIR, PnPLU, PnPLUD, and other registers must be set. Setting the PAIMD register prevents unnecessary current from flowing in a pin when an intermediate voltage (analog voltage) is applied to the pin.
Chapter 3 Port Functions 3-3 I/O Port Configuration and Functions ■ P00,P02,P10 to P14 Reset R D Q Pull-up resistor control Write L Read Reset R D Q Data bus I/O direction control Write L Read Reset R D Q Port output data Write L Read Schmidt trigger input Port input data Read Special function input data Special function output control Special function output data Pull-up resistor control I/O direction control Control bit Register (address) Control bit Register (address) Port output Contr
Chapter 3 Port Functions ■ P01 Reset R D Q Pull-up resistor control Write L Read Reset R D Q I/O direction control Data bus Write L Read Reset R D Q Port output data Write L Read Schmitt trigger input Port input data Read Special function input data Control bit Pull-up resistor Register control (address) Control bit I/O direction Register control (address) Control bit Port output Register (address) Control bit Port input Register (address) Special function input Special function P01 P0PLU1 P
Chapter 3 Port Functions ■ PA0 to PA7 Reset R D Q Pull-up/pull-down resistor control Write L Read R D Q Write L Read Data bus Pull-up/pull-down resistor selection Data bus Reset Read Port input data Reset R D Q Input mode control Write L Read Analog input PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 Control bit PAPLUD0 PAPLUD1 PAPLUD2 PAPLUD3 PAPLUD4 PAPLUD5 PAPLUD6 PAPLUD7 Pull-up resistor Register PAPLUD control (address) (X'03F4A') Pull-up/ PARDWN Control bit pull-down Register FLOAT1 resistor (addre
Chapter 3 Port Functions ■ Pin Configuration for P20, P22 to P23 Reset R D Q Pull-up resistor control L Read Data bus Write Schmitt trigger input Port input data Read Special function input data *P23 is only for 48-pin package.
Chapter 3 Port Functions ■ P21 Reset R D Q Pull-up resistor control Special function input data Data bus Read L Read Reset R D Q Read L Read Port input data Read AC zero-cross detection circuit Special function input data Schmitt trigger input Pull-up resistor control Port input Special function input selection Control bit Register (address) Control bit Register (address) Special function Control bit Register (address) P21 P2PLU1 P2PLU (x'03F42') P2IN1 P2IN (x'03F22') SENS P21IM FLOAT1 (x
Chapter 3 Port Functions ■ P27 Schmitt trigger input Data bus Reset signal input Reset S D Q Port output data Write L Special input Special function output Special function Control bit Register (address) P27 RST Soft reset output P2OUT7 P2OUT (x'03F12') Figure 3-3-6 Configuration and Functions of P27 52 I/O Port Configuration and Functions
Chapter 3 Port Functions ■ P70 to P71 Reset R D Q Pull-up/pull-down resistor control Write L Read Reset R D Q Pull-up/pull-down resistor selection Write L Read I/O direction control Data bus Reset R D Q Write L Read Reset R D Q Port output data Write L Read Port input data Read P70 Pull-up/ Control bit pull-down Register resistor control (address) P7PLUD0 Port input Port output Control bit Register (address) Control bit Register (address) Control bit Register (address) P7PLUD1 P7PLU
Chapter 3 Port Functions ■P60 to P67,P80 to P87 Reset R D Q Pull-up resistor control Write L Read Reset R D Q Data bus I/O direction control Write L Read Reset R D Q Port output data Write L Read Schmidt trigger input Port input data Read Pull-up resistor control Control bit Register (address) I/O direction control Control bit Register (address) Port output Control bit Register (address) Port input Control bit Register (address) P65 P66 P67 P60 P61 P62 P63 P64 P6PLU0 P6PLU1 P6PLU2 P6P
?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@
Chapter 4 Timer Functions 4-1 Overview The MN101C117 contains three 8-bit timers, one 16-bit timer, a watchdog timer, a time base timer, and circuits for remote control output and buzzer output.
TM2IO input fx fs/4 fs MUX MUX TM2CK0 TM2CK1 TM2CK2 TM2PWM TM2EN – – – TM2MD Synchronization 7 0 MUX MUX fosc f s/4 f s/16 TM3IO input MUX Synchronization Read TM2BC R 8-bit counter Match TM2OC Compare register Read/Write MUX MUX TM3CK0 TM3CK1 TM3CK2 TM3PWM TM3EN – – – TM3MD 7 0 MUX RST input Read TM3BC R 8-bit counter Match TM3OC Compare register Read/Write S RQ 1/2 MUX MUX MUX TM3IO output/ PWM2/ Remote control carrier output/ Serial transfer clock output TM2IO
58 Overview TM4IO input fosc fs/4 fs/16 IRQ0 IRQ1 IRQ2 MUX Synchronization MUX MUX Synchronization Read/Write Read Read Read TM4ICH 16-bit capture register TM4ICL MUX RSTIO Pulse-added timing generation TM4BCH R Overflow of lower 8 bits Match TM4OCH 16-bit counter Match TM4BCL R Read TM4OCL 16-bit compare register Read/Write Q TM4CK0 TM4CK1 TM4CK2 T4ICT0 T4ICT1 TM4PWM TM4EN – TM4MD S R Figure 4-1-2 Timer 4 Block Diagram 7 0 1/2 Pulse added MUX TM4PWM MUX TCIO4Ioutput
fx f osc MUX 1/2 13 TM5MD 0 TM5CK0 TM5CK1 TM5CK2 TM5CK3 TM5IR0 TM5IR1 TM5IR2 TM5CLRS 7 1/2 1/2 1/2 1/2 7 8 9 10 MUX fx MUX MUX Synchronization MUX 3.9ms, 7.8ms, 15.6ms, 31.2ms (32kHz) 250ms (32kHz) 0.977ms (8MHz) f osc f s/4 MUX Read MUX TM5BC R TM5IRQ TBIRQ 1min (32kHz),250ms (8.
60 Overview Reset input fs R 1/212 1/211 1/210 1/29 Overflow MUX MUX 1/4 1/4 S ROM option Refer to the aragraph [1-6-1 ROM option] 1/214 1/2 14 fosc 1/2 10 fosc 1/2 6 fosc R 7 0 DLYS0 DLYS1 – – – BUZS0 BUZS1 BUZOE DLYCTR WDEN – – – – – – – WDCTR 7 0 R 1/4 Overflow Buzzer WDIRQ Internal reset release Chapter 4 Timer Functions Figure 4-1-4 Watchdog Timer, Buzzer Block Diagram
Timer 3 output 1/3 duty 1/2 duty MUX – RMDTY0 – RMOEN – – – – RMCTR 7 0 Synchronization circuit Remote control output Chapter 4 Timer Functions Figure 4-1-5 Remote Control Transmission Block Diagram Overview 61
Chapter 4 Timer Functions 4-2 8-bit Timer Operation (timers 2, 3) 4-2-1 Overview Functions for timers 2 and 3 are listed below.
Chapter 4 Timer Functions When servicing an interrupt, reset the timer 2 interrupt request flag before starting timer 2. 4-2-2 Operation During a count operation, be careful if the value set in TM2OC is smaller than the value of binary counter 2, since the count-up operation will continue until overflow occurs. ■ Timer Operation (timers 2, 3) Settings for timer operation are listed below. Timer 2 is used as an example.
Chapter 4 Timer Functions ■ Event Count Function (timers 2, 3) If TM2IO input is selected as the clock source and the value of binary counter 2 is to be read during operation, select synchronized TM2IO input to avoid reading data that may be incomplete during count-up transitions. However, with synchronized TM2IO input, it is not possible to return from STOP/HALT modes. Settings for the event count function are listed below. Timer 2 is used as an example.
Chapter 4 Timer Functions ■ Timer Pulse Output Function (timers 2, 3) Settings for the timer pulse output function are listed below. Timer 2 is used as an example. (1) (2) (3) (4) (5) (6) (7) (8) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2. Set bit 2 of the port 1 output/input mode register (P1OMD) to "1" to set the special function pin. Bit 2 of port 1 will be specified as the pulse output pin.
Chapter 4 Timer Functions If the TM3PWM flag of the TM3MD register is set to "1" and timer 2 PWM output is selected, the PWM output of timer 2 will also be output from the TM3IO pin. If port 1 is to be used as a PWM output pin, the P1DIR and P1PLU registers must be set. ■ PWM Output Function (Timer 2) Settings for the PWM output function are listed below. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2.
Chapter 4 Timer Functions Clock PWM output Figure 4-2-5 PWM Output Timing (when TM2OC register is X'00') Matches TM2OC register Overflow Binary counter 2 PWM output Figure 4-2-6 PWM Output Timing (when TM2OC register is X'FF') 8-bit Timer Operation (timers 2, 3) 67
Chapter 4 Timer Functions The clock source for the serial interface has a frequency that is 1/2 of the overflow output of timer 3. For serial interface settings, refer to the chapter on serial functions. ■ Serial Transfer Clock Function(timer 3) Settings for the serial transfer clock function are listed below. (1) (2) (3) (4) (5) (6) (7) (8) Set the TM3EN flag of the timer 3 mode register (TM3MD) to "0" to stop the count operation of timer 3.
Chapter 4 Timer Functions 4-3 16-bit Timer Operation (timer 4) 4-3-1 Overview Timer 4 is a 16-bit programmable counter that can be used as an event counter. A signal with a frequency of 1/2 of the timer 4 overflow signal can be output from the TM4IO pin. An input capture function and pulse added type PWM output function can also be used. 4-3-2 Operation ■ Timer Operation Settings for timer operation are listed below.
Chapter 4 Timer Functions Clock TM4EN Write to registers TM4OCH, TM4OCL Binary counter 4 04 05 06 07 08 09 00 Figure 4-3-1 Binary Counter 4 (TM4BC) Count Timing If the TM4EN flag of the TM4MD register is changed simultaneously with other bits, the switching operation may cause binary counter 4 to be incremented. If the value of the TM4OCH, TM4OCL register is overwritten while timer 4 has stopped counting, binary counter 4 will be reset to X'0000'.
Chapter 4 Timer Functions ■ Event Count Function Settings for the event count function are listed below. (1) (2) (3) (4) (5) (6) (7) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4. Use the TM4CK2 to 0 flags of the TM4MD register to select TM4IO input or synchronized TM4IO input as the clock source. Set the TM4PWM flag of the TM4MD register to "0" so that 16-bit timer operation is selected. Set a value in compare register 4 (TM4OCH, TM4OCL).
Chapter 4 Timer Functions ■ Timer Pulse Output Function The period of the output signal from the port is 1/2 of the period set in the TM4OCH, TM4OCL register. Settings for the timer pulse output function are listed below. (1) (2) (3) (4) (5) (6) (7) (8) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" so that the count operation of timer 4 is stopped. Set bit 4 of the port 1 output/input mode register (P1OMD) to the special function pin setting.
Chapter 4 Timer Functions ■ Pulse Added Type PWM Output Function If bit 4 of port 1 is to be used as a PWM output pin, set the P1DIR and P1PLU registers. In the pulse added method, a 1-bit output is appended to the basic component of the 8-bit PWM output. Precise control is possible based on the number of PWM repetitions (256 times) to which this bit is appended. Settings for the pulse added type PWM output function are listed below.
Chapter 4 Timer Functions [☞ 5-2-3 "Serial Interface ■ Setting the Added Pulse Position Transfer Timing"] The upper 8 bits of compare register 4 (TM4OCH) set the position of the added pulse. If the TM4OCH register is set to X'00', an additional bit is not appended to the basic PWM component. If the TM4OCH register is set to X'FF', an additional bit is repeatedly appended to the 255 basic PWM components during the period.
Chapter 4 Timer Functions ■ Capture Function Settings for the capture function are listed below. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4. Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the clock source. Use the T4ICTS1 and T4ICTS0 flags of the TM4MD register to select IRQ2, IRQ1, or IRQ0 as the input capture trigger.
Chapter 4 Timer Functions 4-4 8-bit Timer Operation (timer 5) 4-4-1 Overview Timer 5 is an 8-bit timer that can have fosc, fs/4, fx, or time base output as its clock source. 4-4-2 Operation ■ Timer Operation When servicing an interrupt, reset the timer 5 interrupt request flag before starting timer 5. When choosing either time base timer output or time base timer synchronized output for the timer 5 clock source, the time base must be set up.
Chapter 4 Timer Functions 4-5 Time Base Operation 4-5-1 Overview The clock source for the time base timer can be set to fosc or fx. Also, the interrupt period for time base timer (TBIRQ) can be set to 1/27, 1/28, 1/29, 1/210, or 1/213 of the clock source. 4-5-2 Operation ■ Time Base Function Settings for the time base function are listed below. (1) Use the TM5CK0 flag of the timer 5 mode register (TM5MD) to select fosc or fx as the clock source.
Chapter 4 Timer Functions 4-6 Watchdog Timer Operation 4-6-1 Overview The watchdog timer is controlled by the watchdog control register (WDCTR) and can be used for runaway program detection. 4-6-2 Setup and Operation (1) The upper 2 bits of the watchdog timer are cleared when the WDEN flag is set to "0." Therefore, if WDEN flag is set to 0 when an uppermost bit of a watchdog timer is 1, WDT interrupt occurs depending on the timing of this clear the watchdog timer may be reset at 1/4TWD.
Chapter 4 Timer Functions 4-7 Remote Control Output Operation 4-7-1 Overview A remote control carrier pulse can be generated using the overflow of timer 3. Two duty ratios of 1/2 or 1/3 can be selected. 4-7-2 Setup and Operation (1) (2) (3) (4) (5) Set the RMOEN flag of the remote control carrier output control register (RMCTR)to "0" so that the remote control carrier output is switched off.
Chapter 4 Timer Functions 4-8 Buzzer Output 4-8-1 Buzzer Output Setup and Operation The square wave having a frequency 1/29 to 1/212 of the system clock can be output from the P06/BUZZER pin. (1) (2) (3) (4) 80 Buzzer Output Set the BUZOE flag of the oscillation stabilization wait control register (DLYCTR) to "0" so that the buzzer output is turned off. Set the buzzer output frequency with the BUZCK1 and BUZCK0 flags of the DLYCTR.
Chapter 4 Timer Functions 4-9 Timer Function Control Registers 4-9-1 Overview 19 registers control the timers. See table 4-9-1.
Chapter 4 Timer Functions 4-9-2 Programmable Timer/Counters Timers 2~5 all contain a programmable 8-bit timer/counter (16-bit in timer 4). Programmable timer/counters consist of a compare register and a binary counter.
Chapter 4 Timer Functions (5) Compare register 4 (TM4OCL) (lower 8 bits) 7 6 5 4 3 2 1 0 TM4OCL7 TM4OCL6 TM4OCL5 TM4OCL4 TM4OCL3 TM4OCL2 TM4OCL1 TM4OCL0 (at reset: undefined) Figure 4-9-5 Compare Register 4 (TM4OCL: X'03F74', R/W) (6) Compare register 4 (TM4OCH) (upper 8 bits) 7 6 5 4 3 2 1 0 TM4OCH7 TM4OCH6 TM4OCH5 TM4OCH4 TM4OCH3 TM4OCH2TM4OCH1 TM4OCH0 (at reset: undefined) Figure 4-9-6 Compare Register 4 (TM4OCH: X'03F75', R/W) (7) Binary counter 4 (TM4BCL) (lower 8 bits) 7 6 5 4
Chapter 4 Timer Functions (9) Input capture register (TM4ICL) (lower 8 bits) 7 6 5 4 3 2 1 0 TM4ICL7 TM4ICL6 TM4ICL5 TM4ICL4 TM4ICL3 TM4ICL2 TM4ICL1 TM4ICL0 (at reset: undefined) Figure 4-9-9 Input Capture Register (TM4ICL: X'03F66', R) (10) Input capture register (TM4ICH) (upper 8 bits) 7 6 5 4 3 2 1 0 TM4ICH7 TM4ICH6 TM4ICH5 TM4ICH4 TM4ICH3 TM4ICH2 TM4ICH1 TM4ICH0 (at reset: undefined) Figure 4-9-10 Input Capture Register (TM4ICH: X'03F67', R) (11) Compare register 5 (TM5OC) 7 6 5
Chapter 4 Timer Functions 4-9-3 Timer Mode Registers Four readable and writable 6-byte timer mode registers. Control timers 2, 3, 4, 5, and the time base.
Chapter 4 Timer Functions (2) Timer 3 mode register (TM3MD) TM3MD 7 6 5 – – – 4 3 2 TM3EN TM3PWM TM3CK2 1 0 TM3CK1 TM3CK0 (at reset: ---00XXX) TM3CK2 TM3CK1 Clock source selection 0 fosc 1 fs/4 0 fs/16 1 TM3IO input 0 x Cascade connection with timer 2 1 1 Synchronous TM3IO input 0 0 1 1 TM3CK0 TM3PWM P13 output selection during TM2 PWM operation 0 Timer 3 output 1 Timer 2 PWM output TM3EN TM3 count control 0 Halt the count 1 Operate the count Figure 4-9-14 Ti
Chapter 4 Timer Functions (3) Timer 4 mode register (TM4MD) TM4MD 7 6 – TM4EN 5 4 TM4PWM T4ICTS1 3 2 1 0 T4ICTS0 TM4CK2 TM4CK1 TM4CK0 (at reset: -0000XXX) TM4CK2 TM4CK1 0 0 1 TM4CK0 Clock source selection 0 fosc 1 fs/4 0 fs/16 1 1 TM4IO input Synchronous TM4IO input 1 1 T4ICTS1 T4ICTS0 TM4 input capture trigger selection 0 Disable input capture operation 1 IRQ0 0 IRQ1 1 IRQ2 0 1 TM4PWM TM4 operation mode selection 0 16-bit timer operation 1 PWM operation T
Chapter 4 Timer Functions (4) Timer 5 mode register (TM5MD) 7 TM5MD 6 TM5CLRS TM5IR2 5 4 3 2 1 0 TM5IR1 TM5IR0 TM5CK3 TM5CK2 TM5CK1 TM5CK0 (at reset: 0XXXXXX0) TM5CK0 Time base timer clock source selection 0 fosc 1 (Use Prohibited) fx * * 48QFH package only TM5CK3 TM5CK2 X 0 0 1 1 TM5IR2 TM5IR1 0 0 1 1 x TM5CK1 Timer 5 clock source selection 0 fosc 1 fs/4 0 (Use Prohibited) 1 0 Output of time base timer (Use Prohibited) 1 Synchronous time base timer output Time base
Chapter 4 Timer Functions 4-9-4 Timer Control Registers (1) Watchdog timer control register (WDCTR) WDCTR 7 6 5 4 3 2 1 0 – – – – – – – WDEN (at reset: -------0) WDEN Watchdog timer enable 0 Clear watchdog timer/disable operation 1 Enable WDT timer Figure 4-9-17 Watchdog Timer Control Register (WDCTR: X'03F02', R/W) (2) Oscillation stabilization wait control register (DLYCTR) 7 DLYCTR 6 5 BUZOE BUZCK1 BUZCK0 4 3 2 – – – 1 0 DLYS1 DLYS0 (at reset: 0XX---00) DLYS1 DLY
Chapter 4 Timer Functions (3) Remote control carrier output control register (RMCTR) RMCTR 7 6 5 4 3 2 1 0 – – – – RMOEN – RMDTY0 – (at reset: ---00XX0) Must be set to "0." Remote control carrier output duty selection RMDTY0 0 1/2 duty 1 1/3 duty Must be set to "0." RMOEN Enable remote control carrier output 0 Output low level 1 Output remote control carrier Must be set to "0.
?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@
Chapter 5 Serial Functions 5-1 Overview The MN101C117 contains a serial interface that can operate in synchronous and simple UART modes. An overview of serial functions is shown below.
fs/2 fs/4 fs/16 BC3×1/2 1/2 of timer 3 overflow SBT0/P02 SBI0/RXD/P01 SBO0/P00 2 M U X SC0TRI SC0ERE SC0BRKF SC0CK0 SC0CK1 SC0CKM – – SC0MD1 1/8 M U X 7 0 M U X SC0SBTS SC0SBIS SC0SBOS SC0SBTM SC0SBOM SC0IOM – – SC0MD3 M U X SC0LNG0 SC0LNG1 SC0LNG2 SC0STE SC0DIR SC0CE0 SC0CE1 – 8 7 SWAP 8 8 3 Bit counter Receive Append control transmit parity check control parity Shift register 8 SC0TRB Receive buffer SC0RXB 8 SC0MD0 0 Break receive control Stop bit detection Start condition
Chapter 5 Serial Functions 5-2 Synchronous Serial Interface 5-2-1 Overview A serial interface begins operation when data is written to the shift buffer. A bit counter is incremented at each 1-bit transfer. The transfer is complete when the counter overflows. Bit transfers of an arbitrary 1 to 8 bits can be performed. The transfer bit count must be set before performing the transfer.
Chapter 5 Serial Functions When the clock source is an external clock (SBT0 pin input): (7) (8) (9) (10) (11) (12) • Set the SC0SBTM flag of the SC0MD3 register. • Set bit 2 of the P0DIR register to input mode. • Set the P0PLU register, if necessary. Select the SC0SBOM flag of the SC0MD3 register. Select the SC0IOM flag of the SC0MD3 register. Select serial communication by setting the SC0SBOS flag of the SC0MD3 register to "1.
Chapter 5 Serial Functions SBT Clock SBO ts Start condition enabled SBO Start condition disabled Interrupt SC0BSY SC0LNG2 to 0 0 1 2 3 4 5 6 7 0 Figure 5-2-1 Synchronous Serial Interface Transmission Timing (falling edge) Clock SBT SBO Start condition enabled SBO Start condition disabled Interrupt SC0BSY SC0LNG2 to 0 0 1 2 3 4 5 6 7 0 Figure 5-2-2 Synchronous Serial Interface Transmission Timing (rising edge) 96 Synchronous Serial Interface
Chapter 5 Serial Functions ■ Reception (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) Select the synchronous serial interface by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "0." Select the transfer bit count with the SC0LNG2 to 0 flags of the serial interface 0 mode register 0 (SC0MD0). The transfer bit count can be set as 1 to 8 bits. Specify whether the start condition is enabled or disabled with the SC0STE flag of the SC0MD0 register.
Chapter 5 Serial Functions Clock Start condition enabled Start condition disabled Interrupt SC0BSY start condition enabled SC0BSY start condition disabled SC0LNG2 to 0 0 1 2 3 4 5 6 7 0 Figure 5-2-3 Synchronous Serial Interface Reception Timing (reception at rising edge) Clock Start condition enabled Start condition disabled Interrupt SC0BSY start condition enabled SC0BSY start condition disabled SC0LNG2 to 0 0 1 2 3 4 5 6 7 0 Figure 5-2-4 Synchronous Serial Interface Reception
Chapter 5 Serial Functions 5-2-3 Serial Interface Transfer Timing Serial interface 0 uses the SC0CE0 and SC0CE1 flags of serial interface 0 mode register 0 (SC0MD0), to control the edge at which transmission data is output and the edge at which reception data is input. During transmission, when the SCnCE1 flag is "0," data output is synchronized to the falling edge of the clock.
Chapter 5 Serial Functions When serial interface 0 is used for simultaneous transmission and reception, set the SCnCE0 and SCnCE1 flags of the SCnMD0 register to "00" or "01", so that the reception data input edge is opposite in polarity to the transmit data output edge. Also, the polarity of the reception data input edge is opposite polarity of the transmit data output edge of the other device. SBT0 Data is input in synchronization with the rising edge of the clock.
Chapter 5 Serial Functions 5-3 Half-duplex UART Serial Interface 5-3-1 Overview Setup and operation of UART transmission and reception are described below. 5-3-2 Setup and Operation ■ Transmission (1) (2) (3) (4) (5) (6) Select UART by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "1." Specify the first bit to be transferred (MSB first or LSB first) with the SC0DIR flag of the serial interface 0 mode register 0 (SC0MD0).
Chapter 5 Serial Functions (7) (8) (9) Serial interface 0 begins operation when the SC0SBOS flag or the SC0SBIS flag is set to "1." Set the SC0SBOS flag or the SC0SBIS flag after all conditions have been set. (10) (11) (12) (13) (14) (15) (16) If parity is enabled by the SC0NPE flag of the SC0MD2 register, set the SC0PM1~0 flags of the SC0MD2 register to specify the added parity bit. Set the SC0FM1 to 0 flags of the SC0MD2 register to specify the frame mode.
Chapter 5 Serial Functions ■ Reception (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) Select UART by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "1." Specify the first bit to be transferred (MSB first or LSB first) with the SC0DIR flag of the serial interface 0 mode register 0 (SC0MD0). Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the SC0MD0 register.
Chapter 5 Serial Functions RXD Parity enabled Parity bit Stop bit Stop bit Stop bit RXD Parity disabled Interrupt Parity enabled Interrupt Parity disabled SC0BSY Parity enabled SC0BSY Parity disabled Figure 5-3-2 UART Reception Timing 104 Half-duplex UART Serial Interface Stop bit
Chapter 5 Serial Functions 5-3-3 How to Use the Baud Rate Timer Refer to the following when using the baud rate timer to set the UART transfer speed. (1) Specifying the timer clock source The clock source is specified by the TM3CKS3 to 1 flags of the timer 3 mode register (TM3MD). (2) Setting the compare register The compare register value is set in the timer 3 compare register (TM3OC).
Chapter 5 Serial Functions 5-4 Serial Interface Control Registers 5-4-1 Overview 7 registers control the serial interface. See table 5-4-1.
Chapter 5 Serial Functions 5-4-2 Transmit/Receive Shift Registers, Receive Data Buffer (1) Serial interface 0 transmit/receive shift register (SC0TRB) This 8-bit, writable register shifts the transmission data and the reception data. The direction of transfer can be specified as LSB first or MSB first.
Chapter 5 Serial Functions 5-4-3 Serial Interface Mode Registers (1) Serial interface 0 mode register (SC0MD0) 7 SC0MD0 – 6 5 4 3 2 1 0 (at reset: -00XX000) SC0CE0 SC0CE1 SC0DIR SC0STE SC0LNG2 SC0LNG1 SC0LNG0 SC0LNG2 SC0LNG1 SC0LNG0 Transfer bit count 0 0 1 0 1 1 SC0STE 0 8 bit 1 7 bit 0 1 6 bit 5 bit 0 4 bit 1 3 bit 0 2 bit 1 bit 1 Selection of synchronous serial start condition 0 Disable start condition 1 Enable start condition SC0DIR First bit to be transferred 0 MSB fir
Chapter 5 Serial Functions (2) Serial interface 0 mode register 1 (SC0MD1) SC0MD1 7 6 – – 5 4 3 2 1 0 SC0CKM SC0CK1 SC0CK0 SC0BRKF SC0ERE SC0TRI (at reset: --X00000) Transmit/receive interrupt request flag SC0TRI 0 Transmit interrupt request 1 Receive interrupt request Error monitor SC0ERE 0 No error 1 Error Break status receive monitor SC0BRKF 0 Data 1 Break Clock source SC0CK1 SC0CK0 0 0 fs/2 0 1 fs/4 1 0 fs/16 1 1 BC3×1/2(1/2 of timer 3 overflow) SC0CKM Divide
Chapter 5 Serial Functions (3) Serial interface 0 mode register 2 (SC0MD2) SC0MD2 7 6 – – 5 4 3 2 1 0 (at reset: --000XXX) SC0BRKE SC0FM1 SC0FM0 SC0PM1 SC0PM0 SC0NPE SC0NPE Parity enable 0 Parity enabled 1 Parity disabled Added bit specification SC0PM1 SC0PM0 Transmission 0 1 Normally add 0 1 Normally add 1 Check for 1 0 Add odd parity Check for odd parity 1 Add even parity Check for even parity SC0FM1 SC0FM0 0 1 Reception 0 Check for 0 Frame mode specification 0 7 dat
Chapter 5 Serial Functions (4) Serial interface 0 mode register 3 (SC0MD3) SC0MD3 7 6 – – 5 4 3 2 1 0 SC0IOM SC0SBOM SC0SBTM SC0SBOS SC0SBIS SC0SBTS (at reset: --000000) SC0SBTS SBT0 pin function selection 0 Port 1 Serial clock pin SC0SBIS SBI0 input control 0 "1" input 1 Serial input SC0SBOS SBO0 pin function selection 0 Port 1 Serial communication SC0SBTM SBT0 pin configuration selection 0 Push-pull output 1 N-channel open-drain output SC0SBOM SBO0 pin configuration
Chapter 5 Serial Functions 5-4-4 Serial Interface Control Register (1) Serial interface 0 control register (SC0CTR) 7 SC0CTR 6 SC0BSY SC0CMD 5 4 – – 3 2 1 SC0FEF SC0PEK SC0ORE 0 – (at reset: 00XX000X) SC0ORE Overrun error detection 0 No Error 1 Error SC0PEK Parity error detection 0 No Error 1 Error SC0FEF Framing error detection 0 No Error 1 Error SC0CMD Synchronous serial/ UART selection 0 Synchronous serial 1 UART SC0BSY Serial bus status 0 Other use 1 Serial tr
?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@
Chapter 6 A/D Conversion Functions 6-1 Overview The MN101C117 has an internal A/D converter with 10-bit resolution. A sample-and-hold circuit is contained on-chip and software can switch the analog input between channels 0 to 7 (AN0 to AN7). When the A/D converter is stopped, power consumption can be reduced by turning off the internal ladder resistors.
Chapter 6 A/D Conversion Functions 6-2 A/D Conversion The procedures for operating the A/D conversion circuit are listed below. (1) Set the ANCHS2 to ANCHS0 flags of A/D control register 0 (ANCTR0) to specify one of pins AN7 to AN0 (PA7 to PA0) as the analog input. (2) Set the ANCK1 and ANCK0 flags of A/D control register 0 to select the A/D conversion clock. Make this setting such that the period of the conversion clock (TAD), which is based on the oscillator, is greater than 800ns.
Chapter 6 A/D Conversion Functions The following items must be implemented to maintain the accuracy of the A/D converter: 1. Use a maximum input pin impedance, R, of 500kΩ∗1 with an external capacitor, C, that is minimum 1,000pF and maximum 1µF∗1. 2. Take the RC time into consideration when setting the A/D conversion interval. 3.
Chapter 6 A/D Conversion Functions 6-3 A/D Converter Control Registers 6-3-1 Overview Four registers control the A/D converter. See table 6-3-1.
Chapter 6 A/D Conversion Functions 6-3-2 A/D Control Register (ANCTR) This readable and writable 8-bit register controls the operation of the A/D converter.
Chapter 6 A/D Conversion Functions (2) A/D conversion control register 1 (ANCTR1) 7 ANCTR1 6 5 4 3 2 1 0 ANST (at reset: 0-------) ANST A/D conversion status 0 A/D conversion completed or stopped 1 A/D conversion started or in progress Figure 6-3-2 A/D Control Register 1 (ANCTR1: X'03F91', R/W) A/D Converter Control Registers 119
Chapter 6 A/D Conversion Functions 6-3-3 A/D Buffers (ANBUF) These read-only registers store the A/D conversion results. (1) A/D buffer 0 (ANBUF0) This register stores the lower 2 bits of the A/D conversion results. 7 ANBUF0 6 5 4 3 2 1 0 (at reset: XX------) ANBUF07 ANBUF06 Figure 6-3-3 A/D Buffer 0 (ANBUF0: X'03F92', R) (2) A/D buffer 1 (ANBUF1) This register stores the upper 8 bits of the A/D conversion results.
?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@
Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-1 Overview The P21/SENS pin is the input pin for the AC zero-cross detection circuit. The AC zero-cross detection circuit outputs a high level when the input is at an intermediate level, and a low level at all other times. FLOAT1 P7RDWN PARDWN P21IM – – – – – P21/IRQ1/SENS AC zero-cross detection circuit 0 7 MUX P21 input/IRQ1 to noise filter (See figure 7-3-1.
Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-2 AC Zero-Cross Circuit Operation 7-2-1 Setup and Operation Settings for zero-cross circuit operation are listed below. (1) (2) (3) (4) Set the REDG1 flag of the IRQ1ICR register to select the valid edge for IRQ1. Set the NF1EN and NF1CK1 to 0 flags of the NFCTR register to set the noise filter and its sampling clock. With the P21IM flag of the FLOAT1 register, set the P21 pin to zero-cross detection.
Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-3 Noise Filter 7-3-1 Overview External interrupt pins IRQ0 and IRQ1 contain noise filtering circuit. This circuitry can be used for remote control signal reception. Data bus NFCTR IRQ0: External interrupt 0 NF0EN NF0CKS0 NF0CKS1 NF1EN NF1CKS0 NF1CKS1 2 IRQ1: External interrupt 1 2 0 fs/22 7 fs/28 MUX fs/29 fs/210 Noise filter P20/IRQ0 To IRQ0 interrupt MUX fs/22 fs/28 fs/29 MUX 10 fs/2 P21/IRQ1/SENS AC zero-cross circuit (Fig.
Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-3-2 Example Input and Output Waveforms for Noise Filter When the noise filter is used, the waveform input to the IRQ0 pin is sampled based on the clock specified by the NF0CKS0 and NF0CKS1 flags of the noise filter control register (NFCTR). The waveform input to the IRQ1 pin is also sampled based on the clock specified by the NF1CKS0 and NF1CKS1 flags.
Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-4 AC Zero-Cross Control Register 7-4-1 Overview Four registers control the AC zero-cross circuit.
Chapter 7 AC Zero-Cross Circuit/Noise Filter 7-4-2 Noise Filter Control Register (NFCTR) This 6-bit readable and writable register controls the noise filter.
Chapter 7 AC Zero-Cross Circuit/Noise Filter 128
?? @@@?he O26Xe @@Y?e?O26X?e @@@@@@@@@@@@@@@@@@@@@)e ?@@@@@@@@@@@@@@@@@@@)?e ?I'Xg@Xh @Khf?O26X?e N)X?e?J@@h @@@@@@@@@@@@@@@@@@)?e ?@)KeO&Y?eO26Xe @@ @@H?e @@@@@@@@@@@@@@@@@@@@@)e @@ @@f @@@@@@@@@@@@@@@@@@f @@@@@@@@@@@@@@g @@ @@he@@g @@f?@@@e@@@?g @@he@@g @@f?@@He@@Y?O)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @@he@@g @@f?@@?e@@h @@he@@g @@f?@@?e@@eO)X?e @@@@@@@@@@@@@@g @@?@@@@@@?e@@@@@@)?e @0M?e@@e?I4@g ?J@5f?@@?e@@h @@gO26Xe ?7@Hf?@5?e@@h @@@@@@@@@@@@@@@@@@@@@)e ?@5?'@@@@@H?e@@eO26Xe @@hf ?@H?V+MW@5f@@@@@
Chapter 8 Appendices 8-1 EPROM Versions 8-1-1 Overview EPROM version is microcomputer which was replaced with the mask ROM of the MN101C11 with an electronically programmable 16-KB EPROM. Because the MN101CP117**(**=DP,BF,HP) is sealed in plastic, once data is written to the internal PROM it cannot be erased. Because the PX-AP101C11-SDC and PX-AP101C11-FBC are sealed in a ceramic package that has a window, written data can beerased by illumination with ultraviolet light.
Chapter 8 Appendices 8-1-2 Cautions on Use EPROM Versions differs from the MN101C11* in some of its electrical characteristics. The user should be aware of these differences. (1) To prevent data from being erased by ultraviolet light after a program is written, affix seals impermeable to UV rays to the glass sections at the top and side sections of the CPU. (PX-AP101C11-SDC, PX-AP101C11-FBC) (2) Due to device characteristics of the MN101CP11XXX, a writing test cannot be performed on all bits.
Chapter 8 Appendices 8-1-3 Erasing Written Data in Windowed Packages (PX-AP101C11-SDC, PX-AP101C11-FBC) In an internal EPROM with windowed packaging, data is erased("0" → "1") when UV light at 253.7nm permeates the window to irradiate the chip. The recommended exposure is 10W · s/cm2. This coverage can be achieved by using a commercial UV lamp positioned 2 to 3cm above the package for 15-20 minutes(when the illumination intensity of the package surface is12000µ W/cm2).
Chapter 8 Appendices 8-1-4 Characteristics of EPROM Version The MN101C11*(mask ROM version) and the Microcomputer with internal EPROM version have the following differences. Table 8-1-1 Difference between MN101C*(Mask ROM version) and Internal EPROM version) Operating temperature MN101C11＊（ROM ver.） -40 to 85℃ Internal EPROM version -20 to 85℃ Operating voltage 4.5 to 5.5V（0.1μs/20MHz） 2.7 to 5.5v（0.25μs/8MHz） 2.0 to 5.5v（1.
Chapter 8 Appendices 8-1-5 Writing to Microcomputer with Internal EPROM ■ Fit in the writing adapter and position the No.1 pin. No.1 pin must be matched to this position. *The socket of an adapter varies according to the package types. Product name 42-SDIP OTP42SD-101CP11 44-QFP OTP44QF14-101CP11 48-QFH OTP48FH7-101CP11 39 40 1 2 Package type No.1 Pin No.1 Pin No.1 Pin (MN101CP117DP) (MN101CP117BF) (MN101CP117HP) (top view) No.1 Pin 2.297 0.
Chapter 8 Appendices ■ ROM writer Selection The device names should be set up as listed below. Table 8-1-2 Device selection Equip. name Vendor Pecker 30 Avarl Data Hitachi 27C256 1890A Minato Electronics Hitachi 27C256 Lab Site Data I/O Device name Hitachi 27C256 Remarks Do not run ID check and pin connection inspection. The above settings are based on the standard samples. When you use the other equipment than the ones listed, contact the nearest semiconductor design center.
Chapter 8 Appendices 8-1-6 Cautions on Operating the ROM Writer ■ Cautions on operating the ROM writer (1)The Vpp programming voltage for the EPROM versions is 12.5V. Programming with a 21-volt ROM writer can lead to damage. The ROM writer specifications must match those for standard 1-megabit EPROMS:Vpp=12.5V V;tpw=0.2ms. (2)Make sure that the socket adapter matches the ROM writer socket and that the chip is correctly mounted in the socket adapter. Faulty connections can lead to damage.
Chapter 8 Appendices 8-1-7 Option Bit The MN101C117 and the MN101CP117 control the oscillation mode after resetting as well as the runaway-detection watch dog timer, using bit 2 to 0 of the last address (X'7FFF) of the built-in ROM.
Chapter 8 Appendices 8-1-8 Writing Adapter Connection 1 P00 2 P01 VSS 42 OSC1 41 3 P02 4 P06 OSC2 40 5 P10 6 P11 PA7 38 VDD 39 PA6 37 9 P14 10 P20 11 P21 12 P22 13 P60 14 P61 15 P62 16 P63 MN101CP117 7 P12 8 P13 ４２-ＳＤＩＰ VSS VSS NOE VSS A14 VSS VSS VSS VSS VPP VSS NCE A0 A1 A2 A3 A4 A5 A6 A7 VSS PA5 36 PA4 35 PA3 34 PA2 33 PA1 32 PA0 31 P80 30 P81 29 P82 28 P83 27 17 P64 18 P65 P84 26 19 P66 20 P67 P86 24 21 NRST P85 25 P87 23 MMOD 22 VSS VSS VSS VCC VSS VSS A13 A12 A11 A10 A9 A8 D0 D1 D
P70 P67 P66 P65 P64 20 P02 33 32 31 30 29 28 27 26 25 24 23 A3 A2 A1 A0 NCE VSS VPP VSS VSS VSS VSS VSS VDD VSS VSS VSS VSS VSS VSS NOE VSS A14 19 P01 ４４- ＱＦＰ P63 P62 P61 P60 P22 P21 P20 P14 P13 P12 P11 21 P06 22 P10 MN101CP117 17 NC 18 P00 P83 P82 P81 P80 PA0 PA1 PA2 PA3 PA4 PA5 PA6 14 OSC2 15 OSC1 16 VSS 1 2 3 4 5 6 7 8 9 10 11 12 PA7 13 VDD D3 D2 D1 D0 A8 A9 A10 A11 A12 A13 VSS MMOD NRST P84 P85 P86 P87 44 43 42 41 40 39 38 37 36 35 34 D4 D5 D6 D7 VDD VSS VSS A7 A6 A5 A4 Chapter 8 Appen
MN101CP117 36 35 34 33 32 31 30 29 28 27 26 25 A3 A2 A1 A0 VSS NCE VSS VPP VSS VSS VSS VSS 23 P06 24 P10 21 P01 22 P02 20 P00 P63 P62 P61 P60 P23 P22 P21 P20 P14 P13 P12 P11 VSS VSS NOE VSS A14 VSS VDD VSS VSS VSS VSS 19 XO ４８- ＱＦＨ 17 VSS 18 XI 7 8 9 10 11 12 P83 P82 P81 P80 NC PA0 PA1 PA2 PA3 PA4 PA5 PA6 13 PA7 14 VDD A8 A9 A10 A11 A12 A13 VSS 1 2 3 4 5 6 15 OSC2 16 OSC1 D3 D2 D1 D0 P84 P85 P86 P87 MMOD NRST P71 P70 P67 P66 P65 P64 48 47 46 45 44 43 42 41 40 39 38 37 D4 D5 D6 D7 VDD VS
Chapter 10 Appendices 8-2 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag Code Cycle Repeat Expand 1 VF NF CF ZF Size Machine Code 2 3 4 5 6 7 Notes Page 8 9 10 11 Data move instructions MOV MOVW MOV Dn,Dm Dn→Dm – – – – 2 1 1010 DnDm MOV imm8,Dm imm8→Dm – – – – 4 2 1010 DmDm <#8.
Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group PUSH POP EXT Mnemonic Operation Affected Flag CodeCycle Repeat Expand 1 VF NF CF ZF Size Machine Code 2 3 4 5 6 .... .... ...
Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Affected Flag CodeCycle Repeat Expand 1 VF NF CF ZF Size Machine Code 2 3 4 5 6 7 Notes Page 8 9 10 11 NOT NOT Dn _ Dn→Dn 0 3 2 0010 0010 10Dn 89 ASR ASR Dn Dn.msb→temp,Dn.lsb→CF 0 – 3 2 0010 0011 10Dn 90 0 0 3 2 0010 0011 11Dn 91 3 2 0010 0010 11Dn 92 5 5 0011 1000 0bp. >1→Dn,temp→Dn.msb LSR LSR Dn Dn.
Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group Bcc Mnemonic BGT label Operation Affected Flag CodeCycle Repeat Expand 1 VF NF CF ZF Size Machine Code 2 3 4 5 ...H – – – 6 3/4 0010 0011 0001
Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group TBZ Mnemonic TBZ (io8)bp,label Affected Flag CodeCycle Repeat Expand 1 VF NF CF ZF Size Operation if(mem8(IOTOP+io8)bp=0),PC+7+d7(label)+H→PC 0 Machine Code 2 3 4 5 6 7 Notes Page 8 9 10 11 ∗1 123 0 7 6/7 0011 0100 0bp.
Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group RTS Mnemonic RTS Operation mem8(SP)→(PC).bp7∼0 Flag CodeCycle Repeat Expand 1 VF NF CF ZF Size Machine Code 2 3 4 5 6 7 Notes Page 8 9 10 11 − − − − 2 7 0000 0001 133 ● ● ● ● 2 11 0000 0011 134 − − − − 3 2 0010 0001 1rep mem8(SP+1)→(PC).bp15∼8 mem8(SP+2).bp7→(PC).H mem8(SP+2).bp1∼0→(PC).bp17∼16 SP+3→SP RTI RTI mem8(SP)→PSW mem8(SP+1)→(PC).bp7∼0 mem8(SP+2)→(PC).bp15∼8 mem8(SP+3).bp7→(PC).H mem8(SP+3).bp1∼0→(PC).
Chapter 10 Appendices 8-3 Instruction Map MN101C00 SERIES INSTRUCTION MAP 1st nibble\2nd nibble 0 1 RTS 2 3 4 5 6 7 8 9 A B C D E F 0 NOP 1 JSR d12(label) JSR d16(label) MOV #8,(abs8)/(abs12) PUSH An 2 When the extension code is b'0010' 3 When the extension code is b'0011' 4 MOV (abs12),Dm MOV (abs8),Dm MOV (An),Dm 5 MOV Dn,(abs12) MOV Dn,(abs8) MOV Dn,(Am) 6 MOV (io8),Dm MOV (d4,SP),Dm MOV (d8,An),Dm 7 MOV Dn,(io8) MOV Dn,(d4,SP) MOV Dn,(d8,Am) 8 ADD #4,Dm SUB Dn,D
Chapter 10 Appendices Extension code: b'0011' 2nd nibble\3rd nibble 0 1 2 3 4 5 6 7 8 9 A 0 TBZ (abs8)bp,d7 TBZ (abs8)bp,d11 1 TBNZ (abs8)bp,d7 TBNZ (abs8)bp,d11 2 CMP Dn,Dm 3 ADD Dn,Dm 4 TBZ (io8)bp,d7 TBZ (io8)bp,d11 5 TBNZ (io8)bp,d7 TBNZ (io8)bp,d11 6 OR Dn,Dm 7 AND Dn,Dm 8 BSET (io8)bp BCLR (io8)bp 9 JMP abs18(label) JSR abs18(label) A XOR Dn,Dm / XOR #8,Dm B ADDC Dn,Dm C BSET (abs16)bp BCLR (abs16)bp D BTST (abs16)bp cmp #8,(abs16) mov #8,(abs16) E TBZ (a
Chapter 10 Appendices 8-4 Summary of Special Function Registers Bit Symbol Address Register X’3F00’ CPUM X’3F01’ MEMCTR X’3F02’ WDCTR X’3F03’ DLYCTR X’3F0E’ EXADV X’3F10’ P0OUT X’3F11’ P1OUT X’3F12’ P2OUT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 STOP HALT OSC1 OSC0 Must be set STOP HALT transfer request transfer request to "0" IOW1 IOW0 II/0 bus wait value set Oscillation control IRWE IVBA Reference page MN101C00 seriesﾞ LSI Manual 30 Specifies base address of
Chapter 10 Appendices Bit Symbol Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P6IN7 P6IN6 P6IN5 P6IN4 P6IN3 P6IN2 P6IN1 P6IN0 Reference Page X’3F24’ Disables to use X’3F25’ Disables to use X’3F26’ P6IN X’3F27’ P7IN X’3F28’ P8IN X’3F2A’ PAIN X’3F30’ P0DIR P8IN7 P8IN6 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P7IN0 Port 7 input P8IN0 PAIN6 PAIN5 PAIN4 PAIN3 PAIN2 PAIN1 PAIN0 41，45 Port A input P0DIR6 P0DIR2 P0DIR1 P0DIR0 Port 0 I/O direction control P
Chapter 10 Appendices Bit Symbol Address X’3F42’ Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 P2PLU Bit 2 Bit 1 Bit 0 P2PLU2 P2PLU1 P2PLU0 Port 2 pull-up resistor ON/OFF control Reference Page 42，45 X’3F43’ Disables to use X’3F44’ Disables to use X’3F45’ Disables to use P6PLU7 X’3F46’ P6PLU X’3F47’ P7PLUD X’3F48’ P8PLU X’3F4A’ PAPLUD X’3F4B’ FLOAT1 P6PLU6 P6PLU5 P6PLU4 P6PLU3 P6PLU2 P6PLU1 P6PLU0 Port 6 pull-up resistor ON/OFF control 42，45 P7PLUD0 Port pull-up pull down res
Chapter 10 Appendices Bit Symbol Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page X’ 3F59’ Disables to use X’ 3F5A’ Disables to use X’ 3F5B’ Disables to use X’ 3F5C’ Disables to use X’ 3F5D’ Disables to use X’ 3F60’ Disables to use X’ 3F61’ Disables to use − TM2BC7 TM2BC6 X’ 3F62’ TM2BC4 TM2BC3 TM2BC2 TM2BC1 TM2BC0 82 Binary counter2 TM3BC7 TM3BC6 X’ 3F63’ TM2BC5 TM2BC TM3BC5 TM3BC4 TM3BC3 TM3BC TM3BC2 TM3BC1 TM3BC0 Binary counter3 82 TM4BCL7 TM
Chapter 10 Appendices Bit Symbol Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page X’3FE0’ Disables to use X’3FE1’ NMICR X’3FE2’ IRQ0ICR X’3FE3’ IRQ1ICR WDIR 34 Watchdog interrupt request flag IRQ0LV1 IRQ0LV0 REDG0 IRQ0IE IRQ0IR Interrup level flag for external interrupt External interrupt valid edge flag Interrupt enable flag Interrupt request flag IRQ1LV1 IRQ1LV0 REDG1 IRQ1IE IRQ1IR Interrupt level flag for external interrupt External interru
Chapter 10 Appendices Bit Symbol Address Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reference Page X’3FE0’ Disables to use X’3FE1’ NMICR X’3FE2’ IRQ0ICR X’3FE3’ IRQ1ICR WDIR 34 Watchdog interrupt request flag IRQ0LV1 IRQ0LV0 REDG0 IRQ0IE IRQ0IR Interrup level flag for external interrupt External interrupt valid edge flag Interrupt enable flag Interrupt request flag IRQ1LV1 IRQ1LV0 REDG1 IRQ1IE IRQ1IR Interrupt level flag for external interrupt External interru
MN101C115 / 117 LSI User's Manual August,1999 1st Edition 1st Printing Issued by Matsushita Electric Industrial Co., Ltd. Matsushita Electronics Corporation © Matsushita Electric Industrial Co., Ltd.
Semiconductor Company Matsushita Electronics Corporation Nagaokakyo, Kyoto, 617-8520 Japan Tel: (075) 951-8151 http://www.mec.panasonic.co.jp SALES OFFICES ■ HONG KONG SALES OFFICE ■ U.S.A. SALES OFFICE Panasonic Industrial Company [PIC] ● New Jersey Office: 2 Panasonic Way, Secaucus, New Jersey 07094 Tel: 201-392-6173 Fax: 201-392-4652 ● Milpitas Office: 1600 McCandless Drive, Milpitas, California 95035 Tel: 408-945-5630 Fax: 408-946-9063 ● Chicago Office: 1707 N.
