MICROCOMPUTER MN101C MN101C77C/F77G LSI User’s Manual Pub.No.
PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd. The other corporation names, logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations.
About This Manual Organization In this LSI manual, this LSI functions are presented in the following order : overview, basic CPU functions, interrupt functions, port functions, timer functions, serial functions, and other peripheral hardware functions. Each section contains overview of function, block diagram, control register, operation, and setting example.
Finding Desired Information This manual provides three methods for finding desired information quickly and easily. (1) Consult the index at the front of the manual to locate the beginning of each section. (2) Consult the table of contents at the front of the manual to locate desired titles. (3) Chapter names are located at the top outer corner of each page, and section titles are located at the bottom outer corner of each page. Related Manuals Note that the following related documents are available.
1 12 1 Chapter 1 Overview Chapter 2 CPU Basics Chapter 3 Interrupts Chapter 4 I/O Ports 3 3 4 Chapter 5 Prescaler 5 Chapter 6 8-bit Timers 6 Chapter 7 16-bit Timer 7 Chapter 8 Time Base Timer / 8-bit Free-running Timer 8 Chapter 9 Watchdog Timer 9 Chapter 10 Buzzer 10 Chapter 11 Serial Interface 0,1 11 Chapter 12 Serial Interface 3 12 Chapter 13 Serial Interface 4 13 Chapter 14 Automatic Transfer Controller 14 Chapter 15 A/D Converter 15 Chapter 16 D/A Converter
Contents Chapter 1 1-1 1-2 1-3 1-4 1-5 1-6 1-7 Overview ..................................................................................................................... I - 2 1-1-1 Overview .................................................................................................... I - 2 1-1-2 Product Summary ....................................................................................... I - 2 Hardware Functions ......................................................................
2-4 2-5 2-6 2-7 2-8 2-9 2-3-1 Bus Controller ......................................................................................... 2-3-2 Control Registers ..................................................................................... Standby Function ..................................................................................................... 2-4-1 Overview .................................................................................................
3-3-8 Chapter 4 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 iv contents AC Zero-Cross Detector ........................................................................ III - 54 I/O Ports Overview .................................................................................................................. IV - 2 4-1-1 I/O Port Diagram ...................................................................................... IV - 2 4-1-2 I/O Port Status at Reset ..................................
4-11 4-10-1 Registers ................................................................................................ 4-10-2 Operation................................................................................................ Synchronous Output (Port 7) .................................................................................. 4-11-1 Block Diagram ........................................................................................ 4-11-2 Registers .........................................
6-8 6-9 6-10 6-11 6-7-1 Operation................................................................................................ 6-7-2 Setup Example ........................................................................................ Serial Interface Transfer Clock Output .................................................................... 6-8-1 Operation................................................................................................ 6-8-2 Setup Example .............................
7-9 7-8-1 Operation ............................................................................................ 7-8-2 Setup Example .................................................................................... 16-bit Timer Capture ........................................................................................... 7-9-1 Operation ............................................................................................ 7-9-2 Setup Example ...................................................
11-1 11-2 11-3 Overview .................................................................................................................. XI - 2 11-1-1 Functions ................................................................................................ XI - 2 11-1-2 Block Diagram ......................................................................................... XI - 4 Control Registers ......................................................................................................
13-2 13-3 13-1-2 Block Diagram ....................................................................................... XIII - 3 Control Registers .................................................................................................... XIII - 4 13-2-1 Registers List ......................................................................................... XIII - 4 13-2-2 Data Register .........................................................................................
15-2 15-3 15-1-2 Block Diagram ........................................................................................ XV - 3 Control Registers ..................................................................................................... XV - 4 15-2-1 Registers ................................................................................................ XV - 4 15-2-2 Control Registers ....................................................................................
18-4 18-5 18-6 Reprogramming Flow ........................................................................................... XVIII - 9 PROM writer mode ............................................................................................ XVIII - 10 Onboard Serial Programming Mode .................................................................. XVIII - 12 18-6-1 Overview ............................................................................................
Chapter 1 Overview 1
Chapter 1 Overview 1-1 Overview 1-1-1 Overview The MN101C series of 8-bit single-chip microcontroller incorporates multiple types of peripheral functions. This chip series is well suited for camera, VCR, MD, TV, CD, LD, printer, telephone, home automation products, pager, air conditioner, PPC remote control, fax machine, musical instrument, and other applications.
Chapter 1 Overview 1-2 Hardware Functions CPU Core MN101C Core - LOAD-STORE architecture (3-stage pipeline) - Half-byte instruction set / Handy addressing - Memory addressing space is 256 KB - Minimum instructions execution time (3.0 V to 3.6 V for Flash version) High speed oscillation [normal] 0.10 µs / 20 MHz (2.5 V to 3.6 V) 0.20 µs / 10 MHz (2.1 V to 3.6 V) 0.50 µs / 4 MHz (1.8 V to 3.6 V) [2x-speed] 0.119 µs / 8.39 MHz (2.5 V to 3.6 V) Low speed oscillation 61.04 µs / 32.768 kHz (1.8 V to 3.
Chapter 1 Overview < Serial interface interrupts > - Serial interface 0 reception interrupt (Full-Duplex UART) - Serial interface 0 transmission interrupt (synchronous + Full-Duplex UART) - Serial interface 1 reception interrupt (Full-Duplex UART) - Serial interface 1 transmission interrupt (synchronous + Full-Duplex UART) - Serial interface 3 interrupt (synchronous + single master IIC) - Serial interface 4 interrupt (slave IIC) < A/D interrupt > - A/D converter interrupt < Automatic transfer controller(AT
Chapter 1 Overview Timer 4 ( 8-Bit timer for general use or UART baud rate timer ) - Square wave output ( Timer pulse output ), PWM output, Event count Simple pulse width measurement, Serial interface transfer clock - Clock source fosc, fosc/4, fosc/16, fosc/32, fosc/64, fs/2, fs/4, fx, external clock Timer 5 ( 8-Bit timer for general use or UART baud rate timer ) - Square wave output ( Timer pulse output ), PWM output, Event count, Remote control carrier output, Simple pulse width measurement, Serial inte
Chapter 1 Overview Watchdog timer - Watchdog timer frequency can be selected from fs/216, fs/218 or fs/220. Remote control output Based on the timer 0, and timer 3 output, a remote control carrier with duty cycle of 1/2 or 1/3 can be output. Synchronous output Timer synchronous output, Interrupt synchronous output - Port 6 outputs the latched data, on the event timing of the synchronous output signal of timer 1, 5, or 7, or of the external interrupt 2 (IRQ 2).
Chapter 1 Overview Serial interface 1 ( Full-Duplex UART / Synchronous serial interface ) ❑ Synchronous serial interface - Transfer clock source fosc/2, fosc/4, fosx/16, fosc/64, fs/2, fs/4 1/2 of UART baud rate timer ( timer 4 ) output - MSB/LSB can be selected as the first bit to be transferred. Any transfer size 1 to 8 bits can be selected. - Sequence transmission, sequence reception or both are available.
Chapter 1 Overview On Flash version MN101CF77G, NC pin cannot be used as user pin as it is used as VPP pin. Refer to chapter 18 Flash EEPROM when designing your board for compatibility with Flash version. Set VREF+ to VDD, VREF- to VSS even when A/D converter is not used.
1-3-1 Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P77/TCIO5 P76/TCIO1 P75/SBT1B P74/SBI1B/RXD1B Pin Description PA2/AN2 PA1/AN1/DA1 PA0/AN0/DA0 VREFP80/LED0 P81/LED1 P82/LED2 P83/LED3 P84/LED4 P85/LED5 1-3 P86/LED6 P87/LED7 Chapter 1 Overview MN101C77C - 64 pin for general use - 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P73/SBO1B/TXD1B P72/SBT0B P71/SBI0B/RXD0B P70/SBO0B/TXD0B P67/SDO7/KEY7 P66/SDO6/KEY6 P65/SDO5/KEY5 P64/SDO4/KEY4 P63/SDO3/KEY3 P62/SDO2/KEY2 P61/SDO1/
Chapter 1 Overview 1-3-2 Pin Specification Table 1-3-2 Pin P00 P01 Function Input/output Direction control Pin control P02 P03 in/out in/out P0DIR2 P0DIR3 P0PLU2 P0PLU3 SBO1A : Serial Interface 1 transmission data output SBI1A : Serial Interface 1 reception data input SDA4B : Serial Interface 4 data I/O SBT1A : Serial 1 clock I/O SBO0A : Serial 0 transmission data output P04 P05 P06 P10 P11 P12 SBI0A in/out SBT0A in/out BUZZER in/out TCO0A RMOUTA in/out TCIO0B RMOUTB in/out TCO4A in/out P0DIR
Chapter 1 Overview 1-3-3 Pin Functions Table 1-3-3 Name No. I/O Function Pin Function Summary (1/6) Other Function Description Power supply pin Supply 1.8 V to 3.6 V to VDD and 0 V to VSS. Input Output Clock input pin Clock output pin Connect these oscillation pins to ceramic or crystal oscillators for high-frequency clock operation. If the clock is an external input, connect it to OSC1 and leave OSC2 open.
Chapter 1 Overview Table 1-3-4 Name No.
Chapter 1 Overview Table 1-3-5 Name No.
Chapter 1 Overview Table 1-3-6 Name No.
Chapter 1 Overview Table 1-3-7 Name No. I/O Function Pin Function Summary (5/6) Other Function Description BUZZER 21 Output Buzzer output P06 Piezoelectric buzzer driver pin. The driving frequency can be selected by the DLYCTR register. Select output mode by the P0DIR register and select P06 buzzer output by the DLYCTR register. When not used for buzzer output, this pin can be used as a normal I/O pin.
Chapter 1 Overview Table 1-3-8 Nam e No. I/O I/O Function Key interrupt input pins Pin Function Summary (6/6) Other Function KEY0 37 KEY1 38 KEY2 39 P62, SDO2 KEY3 40 P63, SDO3 KEY4 41 P64, SDO4 KEY5 42 P65, SDO5 KEY6 KEY7 43 44 P66, SDO6 P67, SDO7 MMOD 17 I - 16 Pin Description Input Mem ory m ode s witching input pins P60, SDO0 P61, SDO1 Des cription Input pins for interrupt bas ed on ORed res ult of pin inputs .
XO Low Speed oscillator High Speed oscillator CPU MN101C ROM 48KB RAM 3KB 8-Bit Timer 0 External Interrupt 8-Bit Timer 1 Serial Interface 0 8-Bit Timer 4 Serial Interface 1 8-Bit Timer 5 Serial Interface 3 16-Bit Timer 7 Serial Interface 4 Port A Port 0 TXD1A,SBO1A,P00 SDA4B,RXD1A,SBI1A,P01 SCL4B,SBT1A,P02 TXD0A,SBO0A,P03 RXD0A,SBI0A,P04 SBT0A,P05 BUZZER,P06 MMOD Block Diagram VSS VDD 1-4-1 OSC1 Block Diagram XI 1-4 OSC2 Chapter 1 Overview RMOUTA,TCO0A,P10 TCIO7,P14 Time Base
Chapter 1 Overview 1-5 Electrical Characteristics This LSI user's manual describes the standard specification. System clock ( fs ) is 1/2 of high speed oscillation at NORMAL mode, or 1/4 of low speed oscillation at SLOW mode. Please ask our sales offices for its own product specifications.
Chapter 1 Overview 1-5-2 Operating Conditions [ NORMAL mode : fs=fosc/2, SLOW mode : fs=fx/2 ] Ta=-40 oC to +85 oC VDD=1.8 V to 3.6 V, VSS=0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Power supply voltage 1 VDD1 VDD2 2 Power supply voltage 3 VDD3 4 VDD4 fosc < 20.00 MHz fs = fosc/2 fosc < 10.00 MHz fs = fosc/2 fosc < 4.00 MHz fs = fosc/2 fx = 32.768 kHz fs = fosc/2 2.5 3.6 2.1 3.6 1.8 3.6 1.8 3.6 3.6 VDD5 During STOP mode 1.8 tc1 VDD = 2.5 V to 3.6 V 0.
Chapter 1 Overview Ta=-40 oC to +85 oC VDD=1.8 V to 3.6 V VSS=0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX External clock input 1 OSC1 (OSC2 is opened) 18 Clock frequency fosc 19 High level pulse width twh1 1.0 20.0 MHz 20.0 *1 Figure 1-5-3 20 Low level pulse width twl1 21 Rising time twr1 22 Falling time twf1 20.0 ns 5.0 Figure 1-5-3 5.0 External clock input 2 XI (XO is opened) 23 Clock frequency 24 High level pulse width fx 32.768 3.
Chapter 1 Overview 0.9VDD 0.1VDD twh1 twl1 twr1 twf1 twc1 Figure 1-5-3 OSC1 Timing Chart 0.9VDD 0.
Chapter 1 Overview 1-5-3 DC Characteristics Ta=-40 oC to +85 oC VDD=1.8 V to 3.6 V VSS=0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX 6 12 Power supply current (not load at output pin) *1 IDD1 1 2 IDD2 Power supply current 3 IDD3 4 IDD4 5 IDD5 Supply current during HALT1 mode 6 IDD6 7 IDD7 Supply current during STOP mode 8 *1 I - 22 IDD8 fosc=20.00 MHz,VDD=3.3 V [fs = fosc/2] fosc=8.39 MHz,VDD=3.3 V [fs = fosc/2] fx=32.768 kHz,VDD=3.
Chapter 1 Overview Ta = -40 oC to +85 oC VDD=1.8 V to 3.6 V VSS=0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX Input pin 1 MMOD VIH1 0.8VDD VDD 10 Input low voltage VIL1 0 0.
Chapter 1 Overview Ta=-40 oC to +85 oC VDD =1.8 V to 3.6 V VSS=0 V Rating Param eter Sym bol Conditions Unit MIN TYP MAX Input pin 3 P27 (NRST) 19 Input high voltage VIH3 0.8VDD VDD 20 Input low voltage VIL3 0 0.2VDD 21 Input high current IIH3 V VDD=3.3 V,VIN =VSS Pull-up res is tor is built-in -30 -100 -300 µA I/O pin 4 PA0 to PA6 22 Input high voltage VIH4 0.8VDD VDD 23 Input low voltage VIL4 0 0.
Chapter 1 Overview Ta=-40 oC to +85 oC VDD=1.8 V to 3.6 V VSS=0 V Rating Parameter Symbol Conditions Unit MIN I/O pin 7 TYP MAX P80 to P87 42 Input high voltage VIH7 0.8VDD VDD 43 Input low voltage VIL7 0 0.2VDD 44 Input leakage current ILK7 VIN=0 V to VDD 45 Input high current IIH7 VDD=3.3 V,VIN=VSS Pull-up resistor is ON -30 46 Output high voltage VOH7 VDD=3.3 V, IOH=-2.0 mA 2.7 47 Output low voltage VOL7 VDD=3.3 V, IOL=2.0 mA 0.
Chapter 1 Overview 1-5-4 A/D Converter Characteristics *2 Ta=-40 oC to +85 oC VDD = 3.3 V VSS=0 V Rating Param eter Sym bol Conditions Unit MIN 1 Res olution 2 Non-linearity error 1 3 Differential non-linearity error 1 4 Non-linerarity error 5 Differential non-linearity error 2 6 Zero trans ition voltage 7 Full-s cale trans ition voltage TYP MAX 10 VDD = 3.3 V,VSS = 0 V VREF+ = 3.3 V,VREF- = 0 V TAD = 800 ns ±3 VDD = 3.3 V,VSS = 0 V VREF+ = 3.3 V,VREF- = 0 V TAD = 15.
Chapter 1 Overview 1-5-5 D/A Converter Characteristics *2 Ta = -40 oC to +85 oC VDD = 3.3 V VSS = 0 V Rating Parameter Symbol Conditions Unit MIN TYP MAX 1 Resolution *1 8 2 Reference voltage low level VREF- 0 0.5 3 Reference voltage high level VREF+ 2.
Chapter 1 Overview 1-6 Precautions 1-6-1 General Usage Connection of VDD pin, and VSS pin All VDD pins should be connected directly to the power supply and all Vss pins should be connected to ground in the external. The following shows the correct connections and the incorrect connections. Please consider the LSI chip orientation before mounting it on the printed circuit board. Incorrect connection may lead a fusion and break a micro controller.
Chapter 1 Overview 1-6-2 Unused Pins Unused Pins (only for input) Insert 10 kΩ to 100 kΩ resistor to unused pins (only for input) for pull-up or pull-down. If the input is unstable, Pch transistor and Nch transistor of input inverter are on, and through current goes to the input circuit. That increases current consumption and causes power supply noise.
Chapter 1 Overview Unused pins (for I/O) Unused I/O pins should be set according to pins' condition at reset. If the output is high impedance (Pch / Nch transistor : output off) at reset, to stabilize input, set 10 kΩ to 100 kΩ resistor to be pull-up or pulldown. If the output is on at reset, set them open.
Chapter 1 Overview 1-6-3 Power Supply The Relation between Power Supply and Input Pin Voltage Input pin voltage should be supplied only after power supply is on. If the input pin voltage is applied supplies before power supply is on, a latch up occurs and causes the destruction of micro controller by a large current flow.
Chapter 1 Overview 1-6-4 Power Supply Circuit Cautions for Setting Power Supply Circuit The CMOS logic microcontroller is high speed and high density. So, the power circuit should be designed, taking into consideration of AC line noise, ripple caused by LED driver. Figure 1-6-6 shows an example for emitter follower type power supply circuit. An example for Emitter Follower Type Power Supply Circuit Set condensors for noise-filter near microcontroller power pins.
Chapter 1 Overview 1-7 Package Dimension Package Code : LQFP064-P-1414 Units : mm Package Dimension I - 33
Chapter 1 Overview Package Code : TQFP064-P-1010C Units : mm I - 34 Precautions
Chapter 2 CPU Basics 12 1
Chapter 2 CPU Basics 2-1 Overview The MN101C CPU has a flexible optimized hardware configuration. It is a high speed CPU with a simple and efficient instruction set. Specific features are as follows: 1. Minimized code sizes with instruction lengths based on 4-bit increments The series keeps code sizes down by adopting a basic instruction length of one byte and variable instruction lengths based on 4-bit increments. 2. Minimum execution instruction time is one system clock cycle. 3.
Chapter 2 CPU Basics 2-1-1 Block Diagram Data registers D0 Processor status word Address registers D1 PSW Stack pointer A0 D2 SP A1 D3 T1 T2 Clock generator Source oscillation Instruction execution controller ABUS BBUS Instruction decoder Program counter Incrementer ALU Instruction queue Interrupt controller Operand address Program address Interrupt bus Bus controller ROM bus Internal ROM RAM bus Peripheral expansion bus Internal peripheral functions Internal RAM Clock gener
Chapter 2 CPU Basics 2-1-2 CPU Control Registers This LSI locates the peripheral circuit registers in memory space (x'03F00' to x'03FFF') with memorymapped I/O. CPU control registers are also located in this memory space.
Chapter 2 CPU Basics 2-1-3 Instruction Execution Controller The instruction execution controller consists of four blocks: memory, instruction queue, instruction registers, and instruction decoder. Instructions are fetched in 1-byte units, and temporarily stored in the 2-byte instruction queue. Transfer is made in 1-byte or half-byte units from the instruction queue to the instruction register to be decoded by the instruction decoder.
Chapter 2 CPU Basics 2-1-4 Pipeline Process Pipeline process means that reading and decoding are executed at the same time on different instructions, then instructions are executed without stopping. Pipeline process makes instruction execution continual and speedy. This process is executed with instruction queue and instruction decoder. Instruction queue is buffer that fetches the second instruction in advance.
Chapter 2 CPU Basics Address Registers (A0, A1) These registers are used as address pointers specifying data locations in memory. They support the operations involved in address calculations (i.e. addition, subtraction and comparison). Those pointers are 2 bytes data. Transfers between these registers and memory are always in 16-bit units. Either odd or even address can be transferred. At reset, the value of address register is undefined.
Chapter 2 CPU Basics 2-1-7 Processor Status Word Processor status word (PSW) is an 8-bit register that stores flags for operation results, interrupt mask level, and maskable interrupt enable. PSW is automatically pushed onto the stack when an interrupt occurs and is automatically popped when return from the interrupt service routine. 7 PSW Reserved 6 5 4 3 2 1 0 MIE IM1 IM0 VF NF CF ZF ( At reset : 0 0 0 0 0 0 0 0 ) ZF 0 1 CF 0 1 NF 0 1 VF 0 1 Zero flag Operation result is not "0".
Chapter 2 CPU Basics Zero Flag (ZF) Zero flag (ZF) is set to "1", when all bits are '0' in the operation result. Otherwise, zero flag is cleared to "0". Carry Flag (CF) Carry flag (CF) is set to "1", when a carry from or a borrow to the MSB occurs. Carry flag is cleared to "0", when no carry or borrow occurs. Negative Flag (NF) Negative flag (NF) is set to "1" when MSB is '1' and reset to "0" when MSB is '0'. Negative flag is used to handle a signed value.
Chapter 2 CPU Basics 2-1-8 Addressing Modes The MN101C77G series supports the nine addressing modes. Each instruction uses a combination of the following addressing modes. 1) Register direct 2) Immediate 3) Register indirect 4) Register relative indirect 5) Stack relative indirect 6) Absolute 7) RAM short 8) I/O short 9) Handy These addressing modes are well-suited for C language compilers. All of the addressing modes can be used for data transfer instructions.
Chapter 2 CPU Basics Table 2-1-4 Addressing mode Register direct Immediate Register indirect Effective address Explanation Dn/DWn An/SP PSW - Directly specifies the register. Only internal registers can be specified. imm4/imm8 imm16 - Directly specifies the operand or mask value appended to the instruction code. (An) (d8, An) (d16, An) Register relative indirect Addressing Modes (d4, PC) 15 0 Specifies the address using an address register.
Chapter 2 CPU Basics 2-2 Memory Space 2-2-1 Memory Mode ROM is the read only area and RAM is the memory area which contains readable/writable data. In addition to these, peripheral resources such as memory-mapped special registers are allocated. The MN101C series supports single chip mode in its memory model. Table 2-2-1 Memory Mode Setup Memory mode MMOD pin EXMEM flag in (MEMCTR register) EXADV3 to 1 flag in (EXADV register) Single chip mode L 0 - MMOD pin should be fixed to "L" level.
Chapter 2 CPU Basics 2-2-2 Single-chip Mode In single-chip mode, the system consists of only internal memory. This is the optimized memory mode and allows construction of systems with the highest performance. The single-chip mode uses only internal ROM and internal RAM. The MN101C series devices offer up to 12 KB of RAM and up to 240 KB of ROM. This LSI offers 3 KB of RAM and 48 KB of ROM.
II - 14 Memory Space P0PLU TM0BC TM4BC 03F3X 03F4X 03F5X 03F6X TM5BC TM1BC P1PLU P1DIR P1IN P1OUT 1 MEM CTR 2 3 4 5 6 7 8 9 A B C D E F P5PLU P5DIR P5IN P5OUT P7DIR P7IN P7OUT P8DIR P8IN P8OUT TM4OC TM5OC TM4MD TM5MD CK4MD CK5MD TM6BC P6PLU P7PLUD P8PLU P6DIR P6IN P6OUT TM0OC TM1OC TM0MD TM1MD CK0MD CK1MD P2PLU P2DIR P2IN P2OUT PAIN TM6OC TM6MD PAPLUD PADIR TBCLR KEYCNT RMCTR PSCMD Reserved Reserved NFCTR1 NFCTR0 EDGDT DACTR DADR01 03FBX ANCTR0 ANC
Chapter 2 CPU Basics 2-3 Bus Interface 2-3-1 Bus Controller The MN101C series provides separate buses to the internal memory and internal peripheral circuits to reduce bus line loads and thus realize faster operation. There are three such buses: ROM bus, RAM bus, and peripheral expansion bus (I/O bus). They connect to the internal ROM, internal RAM, and internal peripheral circuits respectively. The bus control block controls the parallel operation of instruction read and data access.
Chapter 2 CPU Basics 2-3-2 Control Registers Bus interface is controlled by these 8 bytes of registers : the memory control register (MEMCTR), memory area control register (AREACTR) and bus mode control register (CSMDn).
Chapter 2 CPU Basics Memory Area Control Register (AREACTR) 7 AREACTR 6 5 4 3 2 1 0 CS8EXT CS7EXT CS6EXT CS5EXT CS4EXT CS3EXT CS2EXT CS1EXT ( At reset : 1 1 1 1 1 1 1 1 ) CS1EXT Set always to "0" CS8 to 2EXT Internal memory / External memory selection Figure 2-3-3 0 Internal memory 1 External memory Don't care Memory Area Control Register (AREACTR : x'03F03', R/W) In CS0 area, MMOD pin selects internal ROM/external memory.
Chapter 2 CPU Basics Bus Mode Control Register (CSMDn) 7 6 5 4 3 2 1 0 CSMD01 (X'03F05') CS1MD CS1W2 CS1W1 CS1W0 CS0W2 CS0W1 CS0W0 (At reset: 0110-110) CSMD23 (X'03F06') CS3MD CS3W2 CS3W1 CS3W0 CS2MD CS2W2 CS2W1 CS2W0 (At reset: 01100110) CSMD45 (X'03F07') CS5MD CS5W2 CS5W1 CS5W0 CS4MD CS4W2 CS4W1 CS4W0 (At reset: 01100110) CSMD67 (X'03F08') CS7MD CS7W2 CS7W1 CS7W0 CS6MD CS6W2 CS6W1 CS6W0 (At reset: 01100110) CSMD89 (X'03F09') RESERVED CS9W2 CS9W1 CS9W0 CS8MD CS8W2 CS8W1 CS8W0 (At r
Chapter 2 CPU Basics 2-4 Standby Function 2-4-1 Overview This LSI has two sets of system clock oscillator (high speed oscillation, low speed oscillation) for two CPU operating modes (NORMAL and SLOW), each with two standby modes (HALT and STOP). Power consumption can be decreased with using those modes.
Chapter 2 CPU Basics HALT Modes (HALT0, HALT1) − The CPU stops operating. But both of the oscillators remain operational in HALT0 and only the highfrequency oscillator stops operating in HALT1. − An interrupt returns the CPU to the previous CPU operating mode that is, to NORMAL from HALT0 or to SLOW from HALT1. STOP Modes (STOP0, STOP1) − The CPU and both of the oscillators stop operating.
Chapter 2 CPU Basics 2-4-2 CPU Mode Control Register Transition from one mode to another mode is controlled by the CPU mode control register (CPUM).
Chapter 2 CPU Basics 2-4-3 Transition between SLOW and NORMAL This LSI has two CPU operating modes, NORMAL and SLOW. Transition from SLOW to NORMAL requires passing through IDLE mode. A sample program for transition from NORMAL to SLOW mode is given below. Program 1 MOV x'3', D0 ; Set SLOW mode. MOV D0, (CPUM) Transition from NORMAL to SLOW mode, when the low-frequency clock has fully stabilized, can be done by writing to the CPU mode control register.
Chapter 2 CPU Basics 2-4-4 Transition to STANDBY Modes The program initiates transitions from a CPU operating mode to the corresponding STANDBY (HALT/ STOP) modes by specifying the new mode in the CPU mode control register (CPUM). Interrupts initiate the return to the former CPU operating mode.
Chapter 2 CPU Basics Transition to HALT modes The system transfers from NORMAL mode to HALT0 mode, and from SLOW mode to HALT1 mode. The CPU stops operating, but the oscillators remain operational. There are two ways to leave a HALT mode: a reset or an interrupt. A reset produces a normal reset; an interrupt, an immediate return to the CPU state prior to the transition to the HALT mode. The watchdog timer, if enabled, resumes counting. Program 4 MOV x'4', D0 MOV NOP D0, (CPUM) ; Set HALT mode.
Chapter 2 CPU Basics 2-5 Clock Switching This LSI can select the best operation clock for system by switching clock cycle division factor by program. Division factor is determined by both flags of the CPU mode control register (CPUM) and the Oscillator frequency control register (OSCMD). At the highest-frequency, CPU can be operated in the same clock cycle to the external clock hence providing wider operating frequency range.
Chapter 2 CPU Basics CPU High-frequency 4 . fosc . 0 0 11 1 Low-frequency . 2 . 1 fx 0 .. 11 2 1 00 4 01 16 1* System Clock OSCDBL OSC0 2 0 1 SOSC2DS .
Chapter 2 CPU Basics 2-6 Bank Function 2-6-1 Overview CPU of MN101C00 series has basically 64 KB memory address space. On this LSI, address space can be expanded up to 4 banks (256 KB) based on units of 64 KB, by bank function. 2-6-2 Bank Setting Bank function can be used by setting the proper bank area to the bank register for source address (SBNKR) or the bank register for destination address (DBNKR). At reset, both of the SBNKR register and the DBNKR register indicate bank 0.
Chapter 2 CPU Basics Bank Register for Source Address The SBNKR register is used to specify bank area for loading instruction from memory to register. Once this register is specified, bank control is valid for all addressing modes except I/O short instruction and stack relative indirect instruction. [ SBNKR Chapter 2 2-1-8.
Chapter 2 CPU Basics 2-6-3 Bank Memory Space When bank function is used, the memory space, where CPU can access as data, shows as the following hatched part.
Chapter 2 CPU Basics 2-7 ROM Correction 2-7-1 Overview This LSI can correct and change max. 3 parts in a program on mask ROM with ROM correction function. The correct program is read from the external to the RAM space by using the external EEPROM or by using the serial transmission. This function is valid to the system with the external EEPROM. 2-7-2 Correction Sequence Program is corrected as following steps. (1) The instruction execution address is compared to the correction address.
Chapter 2 CPU Basics The ROM correction setup procedure is as follows. (1) Set the head address of the program to be corrected to the ROM correction address setting register (RCnAPH/M/L). (2) Set the correct program at RAM area. (3) Set the head address of the correct program to RC vector table (RCnV(L), RCnV(H)). (4) Set the RCnEN flag of ROM correction control register (RCCTR) to enable the ROM correction.
Chapter 2 CPU Basics 2-7-3 ROM Correction Control Register ROM correction control register (RCCTR) and ROM correction address setting register (RCnAPL, RCnAPM, RCnAPH) control the ROM correction. ROM correction control register (RCCTR) enables/disables the ROM correction function to 3 parts of the program to be corrected. When the RCnEN flag is set, the ROM correction is activated.
Chapter 2 CPU Basics This register set the head address, which instructions to be corrected are stored to. Once the instruction execution address reaches to the set value to this register, program counter branches indirectly to the set address to the RC vector table (RCnV(L), RCnV(H)). When the ROM correction should be valid, set the RCnEN flag of the ROM correction control register (RCCTR) after setting the address to this register.
Chapter 2 CPU Basics ROM Correction Address 2 Setting Register (RC2AP) 7 6 5 4 3 2 1 0 RC2APL RC2APL7 RC2APL6 RC2APL5 RC2APL4 RC2APL3 RC2APL2 RC2APL1 RC2APL0 ( At reset : X X X X X X X X) Figure 2-7-9 7 6 ROM Correction Address 2 Setting Register (lower 8 bits) (RC2APL : x'03FCD', R/W) 5 4 3 2 1 0 RC2APM RC2APM7 RC2APM6 RC2APM5 RC2APM4 RC2APM3 RC2APM2 RC2APM1 RC2APM0 ( At reset : X X X X X X X X ) Figure 2-7-10 RC2APH ROM Correction Address 2 Setting Register (middle 8 bits) (RC2APM :
Chapter 2 CPU Basics 2-7-4 ROM Correction Setup Example Initial Routine with ROM Correction The following routine should be set to correct the program. Also store the ROM correction setup and the correct program to the external EEPROM, in advance. Here is the steps for ROM correction execution.
Chapter 2 CPU Basics ROM Correction Setup Example The setup procedure with ROM correction to correct 2 parts of the program is shown below. For the step to execute the ROM correction, refer to figure 2-7-12. Initial Routine for ROM correction on the previous page. (STEP 1) Develop the correct program of the external EEPROM to RAM area.
Chapter 2 CPU Basics [Setup for the second correction] Set the head address of the program to be corrected at second to the ROM correction address 1 setting register (RC1AP). RC1APL = x'FD' RC1APM = x'08' RC1APH = x'01' Set the internal RAM address x'06BC' that stored the second correct program to the RC vector table address (RC1V(L), RC1V(H).
Chapter 2 CPU Basics 2-8 Reset 2-8-1 Reset operation The CPU contents are reset and registers are initialized when the NRST pin is pulled to low. Initiating a Reset There are two methods to initiate a reset. (1) Drive the NRST pin low. NRST pin should be held "low" for more than OSC 4 clock cycles (200 ns at 20 MHz). NRST pin 4 clock cycles (200 ns at 20 MHz) Figure 2-8-1 (2) Minimum Reset Pulse Width Setting the P2OUT7 flag of the P2OUT register to "0" outputs low level at P27 (NRST) pin.
Chapter 2 CPU Basics Sequence at Reset (1) When reset pin comes to high level from low level, the innternal 14-bit counter (It can be used as watchdog timer, too.) starts its operation by system clock. The period from starting its count from its overflow is called oscillation stabilization wait time. (2) During reset, internal register and special function register are initiated.
Chapter 2 CPU Basics 2-8-2 Oscillation Stabilization Wait time Oscillation stabilization wait time is the period from the stop of oscillation circuit to the stablization for oscillation. Oscillation stabilization wait time is automatically inserted at releasing from reset and at recovering from STOP mode. At recovering from STOP mode the oscillation stabilization wait time control register (DLYCTR) is set to select the oscillation stabilization wait time.
Chapter 2 CPU Basics Oscillation Stabilization Wait Time Control Register 7 DLYCTR 6 5 4 3 2 1 BUZOE BUZS2 BUZS1 BUZS0 DLYS2 DLYS1 DLYS0 0 (At reset: 0 0 0 0 0 0 0 -) - DLYS2 DLYS1 DLYS0 0 0 1 0 1 1 0 Oscillation stabilization wait period selection fs/214 1 fs/212 0 fs/210 1 0 fs/28 fs/26 1 fs/24 0 1 fs/22 Reserved Note : After reset is released, the oscillation stabilization wait period is fixed at fs/214.
Chapter 2 CPU Basics 2-9 Register Protection 2-9-1 Overview This LSI features a function to protect important register data. When this function is enabled, data is rewritten only when write is done for several times to a register and other write is disabled. Registers with this function are as follows.
Chapter 3 Interrupts 3
Chapter 3 Interrupts 3-1 Overview This LSI speeds up interrupt response with circuitry that automatically loads the branch address to the corresponding interrupt service routine from an interrupt vector table : reset, non-maskable interrupts (NMI), 16 maskable peripheral interrupts, and 5 external interrupts. For interrupts other than reset, the interrupt processing sequence consists of interrupt request, interrupt acceptance, and hardware processing.
Chapter 3 Interrupts 3-1-1 Functions Table 3-1-1 3 Interrupt Functions Interrupt type Reset (interrupt) Non-maskable interrupt Maskable interrupt Vector number 0 1 2 to 28 Table address x'04000' x'04004' x'04008' to x'04070' Address specified by vector address Starting address Interrupt level - - Interrupt factor External RST pin input Errors detection, PI interrupt Generated operation Direct input to CPU core Accept operation Always accepts Always accepts Machine cycles until a
Chapter 3 Interrupts 3-1-2 Block Diagram PSW 7 6 5 4 3 2 1 0 MIE IM1 IM0 Level determined Interrupt CPU core Vector 1 IRQNM1 7 IRQLVL 2-0 6 5 4 3 2 1 0 NMICR PI WDOG Vector 2 7 6 IRQ0ICR xxxLV1-0 5 4 3 2 1 0 xxxIE xxxIR Peripheral function xxxLV : Interrupt Level xxxIE : Interrupt Enable xxxIR : Interrupt Request 0 1 I/O DEC 2 Vector N Vector 28 7 6 5 4 xxxICR xxxLV1-0 III - 4 Overview 1 0 xxxIE xxxIR DEC 2 Figure 3-1-1 2 xxxLV : Interrupt Level xxxIE : I
Chapter 3 Interrupts 3-1-3 Operation ■Interrupt Processing Sequence For interrupts other than reset, the interrupt processing sequence consists of interrupt request, interrupt acceptance, and hardware processing. The program counter (PC) and processor status word (PSW) and handy addressing data (HA) are saved onto the stack, and execution branches to the address specified by the corresponding interrupt vector.
Chapter 3 Interrupts ■Interrupt Sources and Vector Addresses Here is the list of interrupt vector address and interrupt group.
Chapter 3 Interrupts ■Interrupt Level and Priority This LSI allocated vector numbers and interrupt control registers (except reset interrupt) to each interrupt. The interrupt level (except reset interrupt, non-maskable interrupt) can be set by software, per each interrupt group. There are three hierarchical interrupt levels. If multiple interrupts have the same priority, the one with the lowest vector number takes priority.
Chapter 3 Interrupts ■Determination of Interrupt Acceptance The following is the procedure from interrupt request input to acceptance. (1) The interrupt request flag (xxxIR) in the corresponding external interrupt control register(IRQnICR) or internal interrupt control register (xxxICR) is set to '1'. (2) An interrupt request is input to the CPU, If the interrupt enable flag (xxxIE) in the same register is '1'. (3) The interrupt level (IL) is set for each interrupt.
Chapter 3 Interrupts MIE='0' and interrupts are disabled when: - MIE in the PSW is reset to '0' by a program Reset is detected MIE='1' and interrupts are enabled when: MIE in the PSW is set to '1' by a program The interrupt mask level (IM=IM1 - IM0) in the processor status word (PSW) changes when: - The program alters it directly, A reset initializes it to 0 (00b), The hardware accepts and thus switches to the interrupt level (IL) for a maskable interrupt, or Execution of the RTI instruction at the end
Chapter 3 Interrupts ■Interrupt Acceptance Operation When accepting an interrupt, this LSI hardware saves the handy address register, the return address from the program counter, and the processor status word (PSW) to the stack and branches to the interrupt handler using the starting address in the vector table. The following is the hardware processing sequence after by interrupt acceptance. 1. The stack pointer (SP) is updated. (SP-6 → SP) 2.
Chapter 3 Interrupts ■Maskable Interrupt Figure 3-1-6 shows the processing flow when a second interrupt with a lower priority level (xxxLV1xxxLV0='10') arrives during the processing of one with a higher priority level (xxxLV1-xxxLV0='00').
Chapter 3 Interrupts ■Multiplex Interrupt When an MN101C77 series device accepts an interrupt, it automatically disables acceptance of subsequent interrupts with the same or lower priority level. When the hardware accepts an interrupt, it copies the interrupt level (xxxLVn) for the interrupt to the interrupt mask (IM) in the PSW. As a result, subsequent interrupts with the same or lower priority levels are automatically masked. Only interrupts with higher priority levels are accepted.
Chapter 3 Interrupts Figure 3-1-7 shows the processing flow for multiple interrupts (interrupt 1: xxxLV1-xxxLV0='10', and interrupt 2: xxxLV1-xxxLV0='00').
Chapter 3 Interrupts 3-1-4 Interrupt Flag Setup ■ Interrupt request flag (IR) setup by the software The interrupt request flag is operated by the hardware. That is set to "1" when any interrupt factor is generated, and cleared to "0" when the interrupt is accepted. If you want to operate it by the software, the IRWE flag of MEMCTR should be set to "1".
Chapter 3 Interrupts 3-2 Control Registers 3-2-1 Registers List Table 3-2-1 Register Interrupt Control Registers Address R/W Functions Page NMICR x'03FE1' R/W Non-maskable interrupt control register III - 16 IRQ0ICR x'03FE2' R/W External interrupt 0 control register III - 17 IRQ1ICR x'03FE3' R/W External interrupt 1 control register III - 18 IRQ2ICR x'03FE4' R/W External interrupt 2 control register III - 19 IRQ3ICR x'03FE5' R/W External interrupt 3 control register III -
Chapter 3 Interrupts 3-2-2 Interrupt Control Registers The interrupt control registers include the maskable interrupt control registers (xxxICR) and the nonmaskable interrupt control register (NMICR). ■Non-Maskable Interrupt Control Register (NMICR address: x'03FE1') The non-maskable interrupt control register (NMICR) stores the non maskable interrupt request. When the non-maskable interrupt request is generated, the interrupt is accepted regardless of the interrupt mask level (IMn) of PSW.
Chapter 3 Interrupts ■External Interrupt 0 Control Register (IRQ0ICR) The external interrupt 0 control register (IRQ0ICR) controls interrupt level of the external interrupt 0, active edge, interrupt enable and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■External Interrupt 1 Control Register (IRQ1ICR) The external interrupt 1 control register (IRQ1ICR) controls interrupt level of external interrupt 1, active edge, interrupt enable and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■External Interrupt 2 Control Register (IRQ2ICR) The external interrupt 2 control register (IRQ2ICR) controls interrupt level of external interrupt 2, active edge, interrupt enable and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■External Interrupt 3 Control Register (IRQ3ICR) The external interrupt 3 control register (IRQ3ICR) controls interrupt level of external interrupt 3, active edge, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■External Interrupt 4 Control Register (IRQ4ICR) The external interrupt 4 control register (IRQ4ICR) controls interrupt level of external interrupt 4, active edge, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■Timer 0 Interrupt Control Register (TM0ICR) The timer 0 interrupt control register (TM0ICR) controls interrupt level of timer 0 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■Timer 1 Interrupt Control Register (TM1ICR) The timer 1 interrupt control register (TM1ICR) controls interrupt level of timer 1 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■Timer 4 Interrupt Control Register (TM4ICR) The timer 4 interrupt control register (TM4ICR) controls interrupt level of timer 4 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■Timer 5 Interrupt Control Register (TM5ICR) The timer 5 interrupt control register (TM5ICR) controls interrupt level of timer 5 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■Timer 6 Interrupt Control Register (TM6ICR) The timer 6 interrupt control register (TM6ICR) controls interrupt level of timer 6 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■Time Base Interrupt Control Register (TBICR) The time base interrupt control register (TBICR) controls interrupt level of time base interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts Timer 7 Interrupt Control Register (TM7ICR) The timer 7 interrupt control register (TM7ICR) controls interrupt level of timer 7 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■Timer 7 Compare Register 2-match Interrupt Control Register (TOC2ICR) The timer 7 compare register 2-match interrupt control register (TOC2ICR) controls interrupt level of timer 7 compare register 2-match interrupt , interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■Serial Interface 0 Reception Interrupt Control Register (SC0RICR) The serial Interface 0 reception interrupt control register (SC0RICR) controls interrupt level of serial Interface 0 reception interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■Serial Interface 0 Transmission Interrupt Control Register (SC0TICR) The serial Interface 0 transmission interrupt control register (SC0TICR) controls interrupt level of serial Iinterface 0 transmission interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■Serial Interface 1 Reception Interrupt Control Register (SC1ICR) The serial Interface 1 reception interrupt control register (SC1ICR) controls interrupt level of serial Interface 1 reception interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■Serial Interface 1 Transmission Interrupt Control Register (SC1TICR) The serial Interface 1 transmission interrupt control register (SC1TICR) controls interrupt level of serial Iinterface 1 transmission interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■Serial Interface 3 Interrupt Control Register (SC3ICR) The serial interface 3 interrupt control register (SC3ICR) controls interrupt level of serial interface 3 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■Serial Interface 4 Interrupt Control Register (SC4ICR) The serial interface 4 interrupt control register (SC4ICR) controls interrupt level of serial interface 4 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■A/D Converter Interrupt Control Register (ADICR) The A/D converter interrupt control register (ADICR) controls interrupt level of A/D converter interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts ■ATC 1 Interrupt Control Register (ATC1ICR) The ATC 1 interrupt control register (ATC1ICR) controls interrupt level of ATC 1 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".
Chapter 3 Interrupts 3-3 External Interrupts There are 5 external interrupts in this LSI. The circuit (external interrupt interface) for the external interrupt input signal, is built-in between the external interrupt input pin and the interrupt controller block. This external interrupt interface can manage to do with any kind of external interrupts. 3-3-1 Overview Table 3-3-1 shows the list of functions which external interrupts 0 to 4 can be used.
Chapter 3 Interrupts 3-3-2 Block Diagram ■External Interrupt 0 Interface, External Interrupt 1 Interface, Block Diagram PSCMD PSCEN - Standby mode signal 0 NFCTR0 NF0EN NF0SCK0 NF0SCK1 NF1EN NF1SCK0 NF1SCK1 P21IM 7 3-bit prescaler S fosc/2 7 1/2 (Prescaler output signal) S S 1/2 1/2 IRQ0ICR fosc/210 fosc/2 9 fosc/2 8 IRQ0IR IRQ0IE - M U X P20/IRQ0 Noise filter 0 REDG0 IRQ0LV0 IRQ0LV1 M U X Polarity Inversion M U X M U X Edge detection 0 M U X IRQ1IR IRQ1IE REDG1 IRQ1LV0 IRQ1LV1
Chapter 3 Interrupts ■External Interrupt 2 Interface, External Interrupt 3 Interface, Block Diagram IRQ2ICR 0 EDGDT IRQ2IR IRQ2IE - EDGSEL0 EDGSEL1 EDGSEL2 REDG2 IRQ2LV0 IRQ2LV1 7 EDGSEL3 EDGSEL4 Reserved 7 0 P22/IRQ2 Noise filter2 Polarity Inversion M U X M U X IRQ2 interrupt request/ 16-bit timer Edge detection IRQ3ICR 0 IRQ3IR IRQ3IE REDG3 IRQ3LV0 IRQ3LV1 7 P23/IRQ3 Noise filter3 Polarity Inversion M U X M U X IRQ3 interrupt request/ 16-bit timer Edge detection Figure 3-3-2 III - 4
Chapter 3 Interrupts ■External Interrupt 4 Interface Block Diagram IRQ4ICR IRQ4IR IRQ4IE REDG4 IRQ4LV0 IRQ4LV1 P24/IRQ4 Noise filter 4 Polarity Inversion Edge detection M U X EDGDT 0 EDGSEL0 EDGSEL1 EDGSEL2 EDGSEL3 EDGSEL4 Reserved - 7 0 7 M U X P60/KEY0 P61/KEY1 P62/KEY2 M U X P63/KEY3 P64/KEY4 IRQ4 Interrupt request P65/KEY5 P66/KEY6 P67/KEY7 P6IMD P6KYEN1 P6KYEN2 P6KYEN3 P6KYEN4 IRQ4SEL Figure 3-3-3 0 7 External Interrupt 4 Interface Block Diagram External Interrupts III - 41
Chapter 3 Interrupts 3-3-3 Control Registers The external interrupt input signal, which operated in each external interrupt 0 to 4 interface generate interrupt requests. External interrupt 0 to 4 interface are controlled by the external interrupt control register (IRQnICR) and the both edges interrupt control register (EDGDT).
Chapter 3 Interrupts ■Noise Filter Control Register 0 (NFCTR0) The noise filter control register (NFCTR0) sets the noise remove function for IRQ0 and IRQ1 and also selects the sampling cycle of noise remove function. And this register also set the AC zero cross detection function for IRQ1.
Chapter 3 Interrupts ■Noise Filter Control Register 1 (NFCTR1) The noise filter control register (NFCTR1) sets the noise remove function for IRQ2 to IRQ4. NFCTR1 7 6 5 4 3 - - - - - 2 1 0 NF4EN NF3EN NF2EN ( At reset : - - - - - 0 0 0) NF2EN IRQ2/ noise filter setup 0 Noise filter OFF 1 Noise filter ON NF3EN IRQ3/noise filter setup 0 Noise filter OFF 1 Noise filter ON NF4EN IRQ4/noise filter setup 0 Noise filter OFF 1 Noise filter ON * Sampling cycle is fosc only.
Chapter 3 Interrupts ■Both Edges Interrupt Control Register (EDGDT) The both edges interrupt control register (EDGDT) selects interrupt edges of IRQ0 to IRQ4. Interrupts are generated at both edges, or at single edge. The external interrupt control register (IRQ0ICR to IRQ4ICR) specifies whether interrupts are generated.
Chapter 3 Interrupts ■Port 6 Key Interrupt Control Register (P6IMD) The port 6 key interrupt control register (P6IMD) selects if key interrupt is approved, and if external interrupt IRQ4 is approved. Also, this register selects, by 2 bits, which pin on port 6 approved key interrupt.
Chapter 3 Interrupts 3-3-4 Programmable Active Edge Interrupt ■Programmable Active Edge Interrupts (External interrupts 0 to 4) Through register settings, external interrupts 0 to 5 can generate interrupt at the selected edge either rising or falling edge. ■Programmable Active Edge Interrupt Setup Example (External interrupt 0 to 4) External interrupt 4 (IRQ4) is generated at the rising edge of the input signal from P24. The table below provides a setup example for IRQ4.
Chapter 3 Interrupts 3-3-5 Both Edges Interrupt ■Both Edges Interrupt (External interrupts 0 to 4) Both edges interrupt can generate interrupt at both the falling edge and the rising edge by the input signal from external input pins. CPU also can be returned from standby mode by both edges interrupt. ■Both Edges Interrupt Setup Example (External interrupts 0 to 4) External interrupt 2 (IRQ2) is generated at the both edges of the input signal from P22 pin.
Chapter 3 Interrupts 3-3-6 Key Input Interrupt ■Key Input Interrupt (External interrupt 4) This LSI can set port 6 pin (P60 to P67) by 2 bits to key input pin. Key input interrupt can generate an interrupt at the falling edge, if at least 1 key input pin outputs low level. Key input pin should be pull-up in advance. When key input interrupt is used, set the IRQ4SEL flag of the port6 key interrupt control register (P6IMD) to "1".
Chapter 3 Interrupts ■Key Input Interrupt Setup Example (External interrupt 4) After P60 to P63 of port 6 are set to key input pins and key is input (low level), the external interrupt 4 (IRQ4) is generated. An example setup procedure, with a description of each step is shown below. Setup Procedure Description (1) Set the key input pin to input.
Chapter 3 Interrupts 3-3-7 Noise Filter ■Noise Filter (External interrupts 0 to1) Noise filter reduce noise by sampling the input waveform from the external interrupt pins (IRQ0, IRQ1). Its sampling cycle can be selected from 4 types (fosc, fosc/28, fosc/29, fosc/210). ■Noise Remove Selection (External interrupts 2 to 4) Noise filter reduce noise by sampling the input waveform from the external interrupt pins (IRQ2 to IRQ4). Its sampling cycle is fosc.
Chapter 3 Interrupts ■Noise Remove Function Operation (External interrupts 0 to 4) After sampling the input signal to the external interrupt pins ( IRQ0 to IRQ4) by the set sampling time, if the same level comes continuously three times, that level is sent to the inside of LSI. If the same level does not come continuously three times, the previous level is sent.
Chapter 3 Interrupts ■Noise Filter Setup Example (External interrupt 0 and 1) Noise remove function is added to the input signal from P20 pin to generate the external interrupt 0 (IRQ0) at the rising edge. The sampling clock is set to fosc, and the operation state is fosc = 20 MHz. An example setup procedure, with a description of each step is shown below. Setup Procedure Description (1) Specify the interrupt active edge.
Chapter 3 Interrupts 3-3-8 AC Zero-Cross Detector This LSI has AC zero-cross detector circuit. The P21 / ACZ pin is the input pin of AC zero-cross detector circuit. AC zero-cross detector circuit output the high level when the input level is at the middle, and outputs the low level at other level. ■AC Zero-Cross Detector (External interrupt 1) AC zero-cross detector sets the IRQ1 pin to the high level when the input signal (P21/ACZ pin) is at intermediate range.
Chapter 3 Interrupts ■AC Zero-Cross Detector Setup Example (External interrupt 1) AC zero-cross detector generates the external interrupt 1 (IRQ1) by using P21/ACZ pin. An example setup procedure, with a description of each step is shown below. Setup Procedure Description (1) Select the AC zero-cross detector signal.
Chapter 4 I/O Ports 4
Chapter 4 I/O Ports 4-1 Overview 4-1-1 I/O Port Diagram A total of 54 pins on this LSI, including those shared with special function pins, are allocated for the 8 I/O ports of ports 0 to 2, ports 5 to 8 and port A. Each I/O port is assigned to its corresponding special function register area in memory. I/O ports are operated in byte or bit units in the same way as RAM.
Chapter 4 I/O Ports 4-1-2 I/O Port Status at Reset Table 4-1-1 Port Name I/O mode I/O Port Status at Reset (Single chip mode) Pull-up / Pull-down resistor I/O port, special functions Port 0 Input mode No pull-up resistor I/O port Port 1 Input mode No pull-up resistor I/O port Port 2 Input mode P27 : Pull-up resistor 4 I/O port Others : No pull-up resistor Port 5 Input mode No pull-up resistor I/O port Port 6 Input mode No pull-up resistor I/O port Port 7 Input mode No pull-up /
Chapter 4 I/O Ports 4-1-3 Control Registers Ports 0 to 2, ports 5 to 8 and port A are controlled by the data output register (PnOUT), the data input register (PnIN), the I/O direction control register (PnDIR), the pull-up resistor control register (PnPLU) and the pull-up / pull-down resistor control resister (PnPLUD) and registers (P1OMD, P1TCNT, PAIMD, FLOAT) that control special function pin.
Chapter 4 I/O Ports Table 4-1-3 I/O Port Control Registers List (2/2) Register Port 7 Port 8 Port A Pin Control Address R/W Function Page P7OUT x'03F17' R/W Port 7 output register IV-31 P7IN x'03F27' R Port 7 input register IV-31 P7DIR x'03F37' R/W Port 7 direction control register IV-31 P7PLUD x'03F47' R/W Port 7 pull-up / pull-down resistor control register IV-31 P8OUT x'03F18' R/W Port 8 output register IV-38 P8IN x'03F28' R Port 8 input register IV-38 P8DIR x'03F
Chapter 4 I/O Ports 4-2 Port 0 4-2-1 Description General Port Setup Each bit of the port 0 control I/O direction register (P0DIR) can be set individually to set each pin as input or output. The control flag of the port 0 direction control register (P0DIR) should be set to "1" for output mode, and "0" for input mode. To read input data of pin, set the control flag of the port 0 direction control register (P0DIR) to "0" and read the value of the port 0 input register (P0IN).
Chapter 4 I/O Ports 4-2-2 Registers 7 P0OUT - 6 5 4 3 2 1 0 P0OUT6 P0OUT5 P0OUT4 P0OUT3 P0OUT2 P0OUT1 P0OUT0 ( At reset : - 0 0 0 0 0 0 0 ) P0OUT Output data 0 L(VSS level) 1 H(VDD level) Port 0 output register (P0OUT : x'03F10', R/W) P0IN 7 6 5 4 3 2 1 0 - P0IN6 P0IN5 P0IN4 P0IN3 P0IN2 P0IN1 P0IN0 ( At reset : - X X X X X X X ) P0IN Input data 0 Pin is low(VSS level). 1 Pin is high(VDD level).
Chapter 4 I/O Ports 4-2-3 Block Diagram Reset P0PLU0 R D Q Pull-up resistor control Write L Read Reset Write L Read P00 Data bus Port output data P0DIR0 R D Q I/O direction control Reset R D Q Write P0OUT0 L Read 0 M 1 U X P0IN0 Port input data Read Serial interface 1 transmission data output/ UART transmission data output SC1MD1 register SC1SBOS flag Figure 4-2-2 Block diagram (P00) Reset R D Q Nch open-drain control Write SC4ODC00 L Read Reset R D Q Pull-up resistor c
Chapter 4 I/O Ports Reset SC4ODC01 R D Q Nch open-drain control Write L Read Reset P0PLU2 R D Q Pull-up resistor control Write L Read Reset Write L Read P02 Data bus Port output data P0DIR2 R D Q I/O direction control Reset P0OUT2 R D Q Write L Read 0 M 1 U X P0IN2 Port input data Read Serial interface 1 clock input Serial interface 4 clock input Serial interface 1 clock output Serial interface 4 clock output SC1MD1 register SC1SBTS flag SC4AD1 register SELI2C flag Figure
Chapter 4 I/O Ports Reset R D Q Pull-up resistor control Write P0PLU4 L Read Reset R D Q I/O direction control Write L Read P04 Data bus Port output data P0DIR4 Reset R D Q Write P0OUT4 L Read 0 M 1 U X P0IN4 Port input data Read Serial interface 0 reception data input UART reception data input Figure 4-2-6 Block Diagram (P04) Reset R D Q Nch open-drain control Write SC0ODC1 L Read Reset R D Q Pull-up resistor control Write P0PLU5 L Read Reset R D Q I/O direction contr
Chapter 4 I/O Ports Reset R D Q Pull-up resistor control Write P0PLU6 L Read Reset R D Q I/O direction control Write P0DIR6 L Read P06 Data bus Port output data Reset R D Q Write P0OUT6 Read L 0 M 1 U X P0IN6 Port input data Read Buzzer output DLYCTR register bp7 Figure 4-2-8 Block Diagram (P06) Port 0 IV - 11
Chapter 4 I/O Ports 4-3 Port 1 4-3-1 Description General Port Setup Each bit of the port 1 control I/O direction register (P1DIR) can be set individually to set pins as input or output. The control flag of the port 1 direction control register (P1DIR) should be set to "1" for output mode, and "0" for input mode. To read input data of pin, set the control flag of the port 1 direction control register (P1DIR) to "0" and read the value of the port 1 input register (P1IN).
Chapter 4 I/O Ports 4-3-2 P1OUT Registers 7 6 5 - - - 4 3 2 1 0 P1OUT4 P1OUT3 P1OUT2 P1OUT1 P1OUT0 ( At reset : - - - 0 0 0 0 0 ) P1OUT Output data 0 Low (VSS level) 1 High (VDD level) Port 1 output register (P1OUT : x'03F11', R/W) P1IN 7 6 5 4 3 2 1 0 - - - P1IN4 P1IN3 P1IN2 P1IN1 P1IN0 ( At reset : - - - X X X X X ) P1IN Input data 0 Pin is low(VSS level). 1 Pin is high(VDD level).
Chapter 4 I/O Ports 7 P1OMD 6 5 4 3 2 1 0 P1OMD6 P1OMD5 P1OMD4 P1OMD3 P1OMD2 P1OMD1 P1OMD0 ( At reset : - 0 0 0 0 0 0 0 ) P1OMD0 P10 output mode selection 0 I/O port 1 Timer 0 output / Remote control output P1OMD1 P11 output mode selection 0 I/O port 1 Timer 0 output / Remote control output P1OMD2 P12 output mode selection 0 I/O port 1 Timer 4 output P1OMD3 0 1 P1OMD4 P13 output mode selection I/O port Timer 4 output P14 output mode selection 0 I/O port 1 Timer 7 output P1
Chapter 4 I/O Ports 7 P1TCNT 6 5 4 3 2 1 0 P1CNT5 P1CNT4 P1CNT3 P1CNT2 P1CNT1 P1CNT0 (At reset : - - 0 0 0 0 0 0 ) P1CNT1P1CNT0 P10 Output Control 0 1 0 I/O port 1 High output 0 Low output 1 Hi-z output P1CNT3P1CNT2 P12 Output Control 0 1 0 I/O port 1 High output 0 Low output 1 Hi-z output P1CNT5P1CNT4 P14 Output Control 0 1 0 I/O port 1 High output 0 Low output 1 Hi-z output P10 Output Control register ( P1TCNT : X'03F7E', R/W) Figure 4-3-3 Port 1 Registers (3/3) Por
Chapter 4 I/O Ports 4-3-3 Block Diagram Edge event Hold function External interrupt 0 (IRQ0) Reset P1PLU0,2,4 R D Q Pull-up resistor control Write CK Read M Reset Write U X P1DIR0,2,4 R D Q I/O direction control CK Read P10, P12, P14 Data bus Port output data D Q Write P1OUT0,2,4 0 M M 1 U X U X CK Read Reset P1OMD0,2,4 R D Q Output mode control Write CK Read Reset 2 Output control Write 2 P1TCNT0-5 R D Q CK Read P1IN0,2,4 Port input data Read Timer input Timer
Chapter 4 I/O Ports 4-4 Port 2 4-4-1 Description General Port Setup Each bit of the port 2 control I/O direction register (P2DIR) can be set individually to set pins as input or output. The control flag of the port 2 direction control register (P2DIR) should be set to "1" for output mode, and "0" for input mode. To read input data of pin, set the control flag of the port 2 direction control register (P2DIR) to "0" and read the value of the port 2 input register (P2IN).
Chapter 4 I/O Ports 4-4-2 Registers 7 P2OUT 6 5 4 2 2 1 0 P2OUT4 P2OUT3 P2OUT2 P2OUT1 P2OUT0 P2OUT7 ( At reset : 1 - - 0 0 0 0 0 ) P2OUT Output data 0 Low (VSS level) 1 High (VDD level) Port 2 output register(P2OUT : x'02F12', R/W) 7 P2IN 6 5 P2IN7 4 2 2 1 0 P2IN4 P2IN2 P2IN2 P2IN1 P2IN0 ( At reset : 1 - - X X X X X ) P2IN Input data 0 Pin is Low (VSS level). 1 Pin is High (VDD level).
Chapter 4 I/O Ports 4-4-3 Block Diagram Reset R D Q Pull-up resistor control Write P2PLU0,2-4 L Read Reset P2DIR0,2-4 R D Q I/O direction control Data bus Write L Read P20,P22-P24 Reset P2OUT0,2-4 R D Q Port outut data Write L Read P2IN0,2-4 Port input data Schmitt trigger input Read External interrupt Figure 4-4-2 Block Diagram (P20, P22 to P24) Reset R D Q Pull-up resistor control Write P2PLU1 L Read Reset R D Q I/O direction control Data bus Write P2DIR1 L Read P21
Chapter 4 I/O Ports Reset R D Q Port output data Data bus Write P2OUT7 LS Reset Read Port 2 Schmitt trigger input Noise filter Figure 4-4-4 IV - 20 P27 P2IN7 Port input data Reset Read Block Diagram (P27)
Chapter 4 I/O Ports 4-5 Port 5 4-5-1 Description General Port Setup Each bit of the port 5 control I/O direction register (P5DIR) can be set individually to set pins as input or output. The control flag of the port 5 direction control register (P5DIR) is set to "1" for output mode, and "0" for input mode. To read input data of pin, set the control flag of the port 5 direction control register (P5DIR) to "0" and read the value of the port 5 input register (P5IN).
Chapter 4 I/O Ports 4-5-2 Registers 7 6 5 P5OUT 4 3 2 1 0 P5OUT4 P5OUT3 P5OUT2 P5OUT1 P5OUT0 ( At reset : - - - 0 0 0 0 0 ) P5OUT Output data 0 Low (VSS level) 1 High (VDD level) Port 5 output register (P5OUT : x'03F15', R/W) 7 6 5 P5IN 4 3 2 1 0 P5IN4 P5IN3 P5IN2 P5IN1 P5IN0 ( At reset : - - - X X X X X ) P5IN Input data 0 Pin is Low (VSS level). 1 Pin is High (VDD level).
Chapter 4 I/O Ports 4-5-3 Block Diagram Reset R D Q Pull-up resistor control Write P5PLU0 L Read Reset R D Q I/O direction control Write L Read P50 Data bus Port output data P5DIR0 Reset R D Q Write P5OUT0 L Read P5IN0 Port input data Read Serial interface 3 reception data input Figure 4-5-2 Block Diagram (P50) Reset R D Q Nch open-drain control Write SC3ODC0 L Read Reset R D Q Pull-up resistor control Write P5PLU1 L Read Reset R D Q I/O direction control Write Read P5
Chapter 4 I/O Ports Reset R D Q Nch open-drain control Write SC3ODC1 L Read Reset R D Q Pull-up resistor control Write P5PLU2 L Read Reset R D Q I/O direction control Write L Read P52 Data bus Port output data P5DIR2 Reset R D Q Write P5OUT2 L Read 0 M 1 U X P5IN2 Port input data Read Serial interface 3 clock input Serial interface 3 clock output SC3MD1 register SC3SBTS flag Figure 4-5-4 Block Diagram (P52) Reset R D Q Nch open-drain control Write SC4ODC10 L Read Reset
Chapter 4 I/O Ports Reset R D Q Nch open-drain control Write SC4ODC11 L Read Reset R D Q Pull-up resistor control Write P5PLU4 L Read Reset R D Q I/O direction control Write L Read P54 Data bus Port output data P5DIR4 Reset R D Q Write P5OUT4 L Read 0 M 1 U X P5IN4 Port input data Read Serial interface 4 clock input Serial interface 4 clock output SC4AD1 register SELI2C flag Figure 4-5-6 Block Diagram (P54) Port 5 IV - 25
Chapter 4 I/O Ports 4-6 Port 6 4-6-1 Description General port Setup Each bit of the port 6 control I/O direction register (P6DIR) can be set individually to set pins as input or output. The control flag of the port 6 direction control register (P6DIR) is set to "1" for output mode, and "0" for input mode. To read input data of pin, set the control flag of the port 6 direction control register (P6DIR) to "0" and read the value of the port 6 input register (P6IN).
Chapter 4 I/O Ports 4-6-2 Registers 7 P6OUT 6 5 4 3 2 1 0 P6OUT7 P6OUT6 P6OUT5 P6OUT4 P6OUT3 P6OUT2 P6OUT1 P6OUT0 ( At reset : 0 0 0 0 0 0 0 0 ) P6OUT Output data 0 Low (VSS level) 1 High (VDD level) Port 6 output register (P6OUT : x'03F16', R/W) P6IN 7 6 5 4 3 2 1 0 P6IN7 P6IN6 P6IN5 P6IN4 P6IN3 P6IN2 P6IN1 P6IN0 ( At reset : X X X X X X X X ) P6IN Input data 0 Pin is Low (VSS level). 1 Pin is High (VDD level).
Chapter 4 I/O Ports 7 P6SYO 6 5 4 3 2 1 0 P6SYO7 P6SYO6 P6SYO5 P6SYO4 P6SYO3 P6SYO2 P6SYO1 P6SYO0 ( At Reset: 0 0 0 0 0 0 0 0 ) I/O port, Synchronous output pin selection P6SYO 0 I/O port selection 1 Synchronous output selection Port 6 Synchronous Output Control Register (P6SYO:X'03F1E', R/W) 7 FLOAT 6 PARDWN 5 4 3 P7RDWN 2 1 0 SYOEVS1SYOEVS0 ( At Reset: - 0 - 0 - - 0 0 ) SYOEVS1 SYOEVS0 0 1 P6 Synchronous output event selection 0 External interrupt IRQ2 1 Timer 7 interrupt
Chapter 4 I/O Ports 4-6-3 Block Diagram Reset R D Q Pull-up resistor control Write P6PLU0-7 L Read Reset R D Q I/O direction control Write P6DIR0-7 L Read P60-P67 Data bus Port output data Reset R D Q Write Reset 0 M R D Q 1 U X P6OUT0-7 L L Read S Set P6IN0-7 Port input data Schmitt input Read Syncronous output event Reset R D Q Syncronous output control Write L P6SYO0-7 Read Figure 4-6-3 Block Diagram (P60 to P67) Port 6 IV - 29
Chapter 4 I/O Ports 4-7 Port 7 4-7-1 Description General Port Setup Each bit of the port 7 control I/O direction register (P7DIR) can be set individually to set pins as input or output. The control flag of the port 5 direction control register (P7DIR) is set to "1" for output mode, and "0" for input mode. To read input data of pin, set the control flag of the port 7 direction control register (P7DIR) to "0" and read the value of the port 7 input register (P7IN).
Chapter 4 I/O Ports 4-7-2 Registers 7 P7OUT 6 5 4 3 2 1 0 P7OUT7 P7OUT6 P7OUT5 P7OUT4 P7OUT3 P7OUT2 P7OUT1 P7OUT0 ( At reset : 0 0 0 0 0 0 0 0 ) P7OUT Output data 0 Low (VSS level) 1 High (VDD level) Port 7 output register (P7OUT : x'03F17', R/W) P7IN 7 6 5 4 3 2 1 0 P7IN7 P7IN6 P7IN5 P7IN4 P7IN3 P7IN2 P7IN1 P7IN0 ( At reset : X X X X X X X X ) P7IN Input data 0 Pin is Low (VSS level). 1 Pin is High (VDD level).
Chapter 4 I/O Ports 7 FLOAT 6 PARDWN 5 4 P7RDWN 3 2 1 0 SYOEVS1 SYOEVS0 ( At reset : - 0 - 0 - - 0 0 ) SYOEVS1 SYOEVS0 P7 Synchronous output event selection 0 0 External interrupt IRQ2 0 1 Timer 7 interrupt 1 0 Timer 5 interrupt 1 1 Timer 1 interrupt P7RDWN P7 pull-up / pull-down resistor selection 0 Pull-up resistor 1 Pull-down resistor PARDWN PA pull-up / pull-down resistor selection 0 Pull-up resistor 1 Pull-down resistor Pull-up / Pull-down resistor selection, Pin con
Chapter 4 I/O Ports 4-7-3 Block Diagram Reset R D Q Nch open-drain control Write SC0ODC2 L Read Reset R D Q Pull-up/down resistor control Write P7PLUD0 L Read Reset R D Q Pull-up/down resistor selection Write FLOAT(bp4) L Read Reset Data bus I/O direction control R D Q Write P7DIR0 L Read P70 Reset R D Q Port output data Write P7OUT0 L Read 0 M 1 U X P7IN0 Port input data Read Serial interface 0 transmission data output UART transmission data output SC0MD1 register SC0SBOS
Chapter 4 I/O Ports Reset R D Q Nch open-drain control Write SC0ODC3 L Read Reset R D Q Pull-up/down resistor control Write P7PLUD2 L Read Reset R D Q Pull-up/down resistor selection Write FLOAT(bp4) L Read Reset Data bus I/O direction control R D Q Write P7DIR2 L Read P72 Reset R D Q Port output data Write P7OUT2 L Read 0 M 1 U X P7IN0 Port input data Read Serial interface 0 clock input Serial interface 0 clock output SC0MD1 register SC0SBOS flag Figure 4-7-5 Block Diagr
Chapter 4 I/O Ports Reset R D Q Pull-up/down resistor control Write P7PLUD4 L Read Reset R D Q Pull-up/down resistor selection Write FLOAT(bp4) L Read Reset Data bus I/O direction control R D Q Write P7DIR4 L Read P74 Reset R D Q Port output data Write P7OUT4 L Read P7IN4 Port input data Read Serial interface 1 reception data output UART reception data output Figure 4-7-7 Block Diagram (P74 ) Reset R D Q Pull-up/down resistor control Write P7PLUD5 L Read Reset R D Q Pull-u
Chapter 4 I/O Ports Reset R D Q Pull-up/down resistor control Write P7PLUD6,7 L Read Reset R D Q Pull-up/down resistor selection Write FLOAT(bp4) L Read Reset Data bus I/O direction control R D Q Write P7DIR6,7 L Read P76,P77 Reset R D Q Port output data Write P7OUT6,7 L Read 0 M 1 U X Reset R D Q Output mode control Write P1OMD6,7 L Read P7IN6,7 Port input data Read Timer input Timer output Figure 4-7-9 IV - 36 Port 7 Block Diagram (P76, P77 )
Chapter 4 I/O Ports 4-8 Port 8 4-8-1 Description General Port Setup Each bit of the port 8 control I/O direction register (P8DIR) can be set individually to set each pin as input or output. The control flag of the port 8 direction control register (P8DIR) is set to "1" for output mode, and "0" for input mode. To read input data of pin, set the control flag of the port 8 direction control register (P8DIR) to "0" and read the value of the port 8 input register (P8IN).
Chapter 4 I/O Ports 4-8-2 Registers 7 P8OUT 6 5 4 3 2 1 0 P8OUT7 P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUT0 ( At reset : 0 0 0 0 0 0 0 0 ) P8OUT Output data 0 Low (VSS level) 1 High (VDD level) Port 8 output register (P8OUT : x'03F18', R/W) P8IN 7 6 5 4 3 2 1 0 P8IN7 P8IN6 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P8IN0 ( At reset : X X X X X X X X ) P8IN Input data 0 Pin is Low (VSS level). 1 Pin is High (VDD level).
Chapter 4 I/O Ports 7 P8LED 6 5 4 3 2 1 0 P8LED7 P8LED6 P8LED5 P8LED4 P8LED3 P8LED2 P8LED1 P8LED0 ( At reset : 0 0 0 0 0 0 0 0 ) P8LED Transistor selection 0 Normal output 1 LED output Port 8 LED Control register (P8LED : x'03F1D', R/W) Figure 4-8-2 Port 8 Registers (2/2) Port 8 IV - 39
Chapter 4 I/O Ports 4-8-3 Block Diagram Reset R D Q Pull-up resistor control Write P8PLU0-7 L Read Reset R D Q I/O direction control Write P8DIR0-7 L Read P80-P87 Data bus Port output data Reset R D Q Write P8OUT0-7 L Read Reset R D Q Function switching output buffer Write P8LED0-7 L Read P8IN0-7 Port input data Read Figure 4-8-3 IV - 40 Port 8 Block Diagram (P80 to P87)
Chapter 4 I/O Ports 4-9 Port A 4-9-1 Description General Port Setup Each bit of the port A control I/O direction register (PADIR) can be set individually to set each pin as input or output. The control flag of the port A direction control register (PADIR) should be set to "1" for output mode, and "0" for input mode. To read input data of pin, set the control flag of the port A direction control register (PADIR) to "0" and read the value of the port 0 input register (P0IN).
Chapter 4 I/O Ports 4-9-2 Registers 7 6 PAOUT 5 4 3 2 1 0 PAOUT6 PAOUT5 PAOUT4 PAOUT3 PAOUT2 PAOUT1 PAOUT0 ( At reset : - 0 0 0 0 0 0 0 ) PAOUT Output data 0 Low (Vss level) 1 High (Vdd level) Port A output register (PAOUT: X'03F1A', R/W) 7 PAIN 6 5 4 3 2 1 0 PAIN6 PAIN5 PAIN4 PAIN3 PAIN2 PAIN1 PAIN0 ( At reset : X X X X X X X X ) PAIN Input data 0 Pin is low (Vss level) 1 Pin is high (Vdd level) Port A intput register (PAIN: X'03F2A', R) 7 PADIR 6 5 4 3 2 1 0 PA
Chapter 4 I/O Ports 7 PAIMD 6 5 4 3 2 1 0 PAIMD6 PAIMD5 PAIMD4 PAIMD3 PAIMD2 PAIMD1 PAIMD0 ( At reset: - 0 0 0 0 0 0 0 ) I/O port / special function pin selection PAIMD 0 I/O port 1 Special function pin Port A Input control register (PAIMD: X'03F3C', R/W) 7 FLOAT 6 PARDWN 5 4 P7RDWN 3 2 1 0 SYOEVS1SYOEVS0 ( At reset: - 0 - 0 0 - 0 0 ) SYOEVS1SYOEVS0 0 1 P6 synchronous output event selection 0 External interrupt IRQ2 1 Timer 7 interrupt 0 Timer 5 interrupt 1 Timer 1 interr
Chapter 4 I/O Ports 4-9-3 Block Diagram Reset PAPLUD0-1 R D Q Pull-up/down resistor control Write L Read Reset FLOAT(bp6) R D Q Pull-up/down resistor selection Write L Read Reset Data bus I/O direction control PADIR0-1 R D Q Write L Read PA0-PA1 Reset PAOUT0-1 R D Q Port output data Write L Read Reset R D Q Write PAIMD0-1 L Read PAIN0-1 Port input data Read Analog input Read DA output Figure 4-9-3 Block Diagram (PA0 to PA1) Reset PAPLUD2-6 R D Q Pull-up/down resistor
Chapter 4 I/O Ports 4-10 Real Time Output Control (Port 1) P10 , P12 and P14 has a real time output function that can switch pin's output at the falling edge of the external interrupt 0 pin (P20/IRQ0). Real time control can change timer output signal (PWM output, timer pulse output, remote control carrier output), without setting on the program, in synchronization with external event. Output levels to be switched at event generation are 3 ; "0", "1" and "high impedance (Hi-z)".
Chapter 4 I/O Ports 4-10-2 Operation Real Time Output Pin Setup The real time output pin is set by the port 1 output control register(P1TCNT). The selectable pins are P10, P12 and P14. Those can be specified by each pin. Select the output mode by the port 1 direction control register (P1DIR). There are 3 output levels ; "0", "1" and "High impedance(Hi-z)". Those are switched at the falling edge of the external interrupt 0 pin (P20/IRQ0). At high impedance, port becomes input mode.
Chapter 4 I/O Ports Timing P1n output (n=0, 2, 4) : Timer output P1TCNT set level : "0" (Low) output Timer output External interrupt 0 (IRQ0) PITCNT set value="0" P1n output (n=0,2,4) Writing to P1OUT register Figure 4-10-1 Real Time Output Control Timing Real Time Output Control (Port 1) IV - 47
Chapter 4 I/O Ports 4-11 Synchronous output (Port 6) Port 6 has the synchronous output function that outputs the any set data to pins, in synchronization with the generation of the specified event. Synchronous event is selected from the external interrupt 2 (P22/ IRQ2), timer 1 interrupt, timer 5 interrupt or timer 7 interrupt signal.
Chapter 4 I/O Ports 4-11-2 Registers Table 4-11-1 shows the synchronous output control registers of port 6.
Chapter 4 I/O Ports 4-11-3 Operation Synchronous Output Setup The synchronous output control register (P6SYO) selects the synchronous output pin of the port 6, in each bit. The synchronous output event is selected by the pin control register (FLOAT).
Chapter 4 I/O Ports Port 6 Synchronous Output (External interrupt 2 IRQ2)) The synchronous output timing when the synchronous output event is set at the falling edge of the external interrupt 2, is shown below. The latched data on port 6 is output in synchronization with the falling edge of the IRQ2.
Chapter 4 I/O Ports 4-11-4 Setup Example A setup example of the port 6 synchronous output by the external interrupt 2 (IRQ2) is shown as follows. As it is operated, the initial output data of port 6 is "55", the synchronous output data is "AA", and the rising edge of the IRQ2 is selected at the synchronous event. An example setup procedure, with description of each step is shown below. Setup Procedure Description (1) Select the synchronous output event.
Chapter 5 Prescaler 5
Chapter 5 Prescaler 5-1 Overview This LSI has 2 prescalers that can be used by its peripheral functions at the same time. Each of them count with fosc or fs as a base clock. Its hardware is constructed as follows ; Prescaler 0 (fosc count) Prescaler 1 (fs count) 7 bit prescaler 3 bit prescaler Prescaler 0 outputs fosc/2, fosc/4, fosc/16, fosc/32, fosc/64, fosc/128 as cycle clock. Prescaler 1 outputs fs/2, fs/4, fs/8 as cycle clock.
Chapter 5 Prescaler 5-1-1 Peripheral Functions Table 5-1-1 shows several kinds of clock source that can be selected by each peripheral functions from prescaler output.
Chapter 5 Prescaler 5-1-2 Block Diagram PSCMD PSCEN bp0 fosc 7bit Prescaler PSC0 ck S fs CK0MD bp0 TM0BAS TM0PSC0 TM0PSC1 2 4 bp7 CK1MD bp0 TM1BAS TM1PSC0 TM1PSC1 - CK4MD bp0 TM4BAS TM4PSC0 TM4PSC1 - 2 4 CK5MD bp0 TM5BAS TM5PSC0 TM5PSC1 - 2 4 M U X Timer 4 M U X Timer 5 bp7 3 2 Timer5 Out SC1CKS bp0 SC1PSC0 SC1PSC1 SC1PSC2 2 4 Timer4 Out SC3CKS bp0 SC3PSC0 SC3PSC1 SC3PSC2 2 4 Timer5 Out M U X Serial interface 1 M U X Serial interface 3 bp7 Figure 5-1-1 Overview Serial int
Chapter 5 Prescaler 5-2 Control Register 5-2-1 Registers List Table 5-2-1 shows registers to control prescaler.
Chapter 5 Prescaler 5-2-2 Control Registers Registers that select prescaler outputs cycle clock and prescaler operation control, consists of the prescaler control register (PSCMD), the timer prescaler selection register (CKnMD) and the serial transfer clock selection register (SCnCKS). The prescaler control register controls if counting of prescaler is permitted or not.
Chapter 5 Prescaler The timer prescaler selection register selects the count clock that used in 8-bit timer.
Chapter 5 Prescaler Timer 4 Prescaler Selection Register (CK4MD) 7 6 5 4 3 2 1 0 TM4PSC1 TM4PSC0 TM4BAS CK4MD ( At reset : - - - - - X X X ) TM4PSC1 TM4PSC0 TM4BAS Clock source selection 0 1 - Figure 5-2-4 0 1 0 fosc/4 0 1 fosc/32 fosc/64 1 0 fosc/16 1 fs/2 fs/4 Timer 4 Prescaler Selection Register (CK4MD : x'03F66', R/W) Timer 5 Prescaler Selection Register (CK5MD) 7 6 5 4 3 2 1 0 TM5PSC1 TM5PSC0 TM5BAS CK5MD ( At reset : - - - - - X X X ) TM5PSC1 TM5PSC0 TM5BAS Clock
Chapter 5 Prescaler The serial interface transfer clock selection register (SCnCKS) selects the transfer clock used for serial data transfer.
Chapter 5 Prescaler Serial Interface 3 Transfer Clock Selection Register (SC3CKS) 7 6 5 4 3 2 1 0 ( At reset : - - - - 0 X X X ) Reserved SC3PSC2 SC3PSC1 SC3PSC0 SC3CKS SC3PSC2 SC3PSC1 SC3PSC0 Clock source selection 0 0 1 1 0 1 Reserved Figure 5-2-8 V - 10 0 1 fosc/2 0 fosc/16 1 fosc/32 0 fs/2 1 X fs/4 fosc/4 Timer 5 output Set always to "0" Serial Interface 3 Transfer Clock Selection Register (SC3CKS : x'03FAF', R/W) Control Registers
Chapter 5 Prescaler 5-3 Operation 5-3-1 Operation Prescaler Operation (Prescaler 0 to 1) Prescaler 0 is a 7-bit and prescaler 1 is a 3-bit free-running counter that divides the base clock. This prescaler can be started or stopped by the PSCEN flag of the prescaler control register (PSCMD). Count Timing of Prescaler Operation (Prescaler 0 and 1) Prescaler 0 counts up at the falling edge of fosc. Prescaler 1 counts up at the falling edge of fs.
Chapter 5 Prescaler 5-3-2 Setup Example Prescaler Setup Example (Timer 0 count clock) Select the clock of fosc/16 that is output from the prescaler 0, to the count clock of the timer 0. An example setup procedure , with a description of each step is shown below. Setup Procedure (1) (2) Select the prescaler output. CK0MD (x'3F56') bp2-1 : TM0PSC1-0 = 01 bp0 : TM0BAS =0 Enable the prescaler output.
Chapter 6 8-bit Timers 6
Chapter 6 8-bit Timers 6-1 Overview This LSI contains two general purpose 8-bit timers (Timers 0 and 1) and two 8-bit timers (Timers 4 and 5) that can be also used as baud rate timer. The general purpose 8-bit timers can be used as 16-bit timers with cascade connection. In a cascade connecion, timers 0, 4 and 5 form the "timer 0", or the lower 8 bits of 16-bit counter, and timers 1 form the "timer 1", or the upper 8 bits. Timers 4 and 5 cannot be cascaded.
Figure 6-1-1 TM0CK0 TM0CK1 TM0CK2 TM0EN TM0PWM TM0MOD - TM0MD 7 0 P22/IRQ2 M U X fosc Synchronization tm0psc M U X TM1IO input fx Read/Write M U X Read M U X OVF 8-bit counter TM0BC RST Match Compare register TM0OC Synchronization IRQ2=H : Count Stop M U X fosc tm1psc RST input M U X S R Q 1/2 R Read M U X M U X 8-bit counter TM1BC Match TM1IO output TM1IRQ / Synchronous output event 1/2 TM0IRQ TM0IO output / PWM0 / Remote control carrier output RST Compare register T
VI - 4 Overview Figure 6-1-2 7 Timer 4 and 5 Block Diagram TM4CK2 TM4EN TM4PWM TM4MOD - TM4CK0 TM4CK1 7 TM4MD 0 M U X fx M U X Prescaler block TM4IO input TM5CK0 TM5CK1 TM5CK2 TM5EN TM5PWM TM5MOD - TM5MD 0 TM5IO input fx Prescaler block P24/IRQ4 P23/IRQ3 fosc Synchronization tm4psc fosc Synchronization tm5psc M U X M U X IRQ4=H: Count Stop IRQ3=H: Count Stop RST Read TM4BC 8-bit counter RST Match TM4OC Compare register Read/Write Read TM5BC 8-bit counter Match TM5O
Timer 3 output Timer 0 output MUX 1/3 duty 1/2 duty MUX RMBTMS RMDTY0 RMOEN TM0RM - RMCTR 7 0 Synchronizing circuit MUX P10/ TM0IO output / Remote control carrier ouput Chapter 6 8-bit Timers Remote Control Carrier Output Block Diagram Figure 6-1-3 Remote Control Carrier Output Block Diagram Overview VI - 5
Chapter 6 8-bit Timers 6-2 Control Registers Timers 0, 1, 4 and 5 consist of the binary counter (TMnBC) and the compare register (TMnOC). And they are controlled by the mode register (TMnMD). When the prescaler output is selected as the count clock source of timers 0, 1 4 and 5, they should be controlled by the prescaler control register (PSCMD) and the prescaler selection register (CKnMD). Remote control carrier output is controlled by the remote control carrier output control register (RMCTR).
Chapter 6 8-bit Timers Timer 4 Timer 5 Remote control carrier output Register Address R/W TM4BC x'03F60' R TM4OC x'03F62' R/W Timer 4 compare register VI-8 TM4MD x'03F64' R/W Timer 4 mode register VI-12 CK4MD x'03F66' R/W Timer 4 prescaler selection register V-8 PSCMD x'03F6F' R/W Prescaler control register V-6 TM4ICR x'03FED' R/W Timer 4 interrupt control register III-24 P1OMD x'03F2F' R/W Port 3 output mode register IV-14 P1DIR x'03F31' R/W Port 1 direction control regi
Chapter 6 8-bit Timers 6-2-2 Programmable Timer Registers Each of timers 0, 1, 4 and 5 has 8-bit programmable timer registers. Programmable timer register consists of compare register and binary counter. Compare register is 8-bit register which stores the value to be compared to binary counter.
Chapter 6 8-bit Timers Binary counter is 8-bit up counter. If any data is written to compare register during counting is stopped, binary counter is cleared to x'00'.
Chapter 6 8-bit Timers 6-2-3 Timer Mode Registers Timer mode register is readable/writable register that controls timers 0, 1, 4 and 5.
Chapter 6 8-bit Timers Timer 1 Mode Register (TM1MD) TM1MD 7 6 5 - - - 4 3 2 1 0 ( At reset : - - - 0 0 0 0 0 ) TM1CAS TM1EN TM1CK2 TM1CK1 TM1CK0 TM1CK2 TM1CK1 - 0 0 1 1 TM1EN Figure 6-2-10 TM1CK0 Clock source 0 fosc 1 tm1psc (Prescaler output) 0 fx 1 Synchronous fx 0 1 Synchronous TM1IO input TM1IO input Timer 1 count control 0 Disable the count 1 Enable the count TM1CAS Timer 1 operation mode 0 Normal timer operation 1 Cascade connection Timer 1 Mode Register (
Chapter 6 8-bit Timers Timer 4 Mode Register (TM4MD) TM4MD 7 6 - - 5 4 3 2 1 0 ( At reset : - - 0 0 0 0 0 0 ) TM4MOD TM4PWM TM4EN TM4CK2 TM4CK1 TM4CK0 TM4CK2 TM4CK1 - 0 0 1 1 TM4EN VI - 12 Control Registers 0 fosc 1 tm4psc(Prescaler output) 0 fx 1 Synchronous fx 0 1 TM4IO input Synchronous TM4IO input Timer 4 count control 0 Disable the count 1 Enable the count TM4PWM Timer 4 operation mode 0 Normal timer operation 1 PWM operation TM4MOD Figure 6-2-11 Clock source
Chapter 6 8-bit Timers Timer 5 Mode Register (TM5MD) TM5MD 7 6 - - 5 4 3 2 1 0 ( At reset : - - 0 0 0 0 0 0 ) TM5MOD TM5PWM TM5EN TM5CK2 TM5CK1 TM5CK0 TM5CK2 TM5CK1 - 0 0 1 TM5EN fosc 1 tm5psc(Prescaler output) 0 fx 1 Synchronous fx TM5IO input Synchronous TM5IO input Timer 5 count control 0 Disable the count 1 Enable the count TM5PWM Timer 5 operation mode 0 Normal timer operation 1 PWM operation TM5MOD Figure 6-2-12 0 0 1 1 Clock source TM5CK0 Pulse width measur
Chapter 6 8-bit Timers Remote Control Carrier Output Control Register (RMCTR) RMCTR 7 6 5 - - - 4 3 TM0RM RMOEN 2 - 1 0 RMDTY0 RMBTMS ( At reset : - - - 0 0 - 0 0 ) RMBTMS Remote control carrier base timer selection 0 Timer 0 output selection 1 Timer 5 output selection RMDTY0 Remote control carrier output duty selection 0 1/2 duty 1 1/3 duty RMOEN Enable remote control carrier output 0 Output low level 1 Output remote control carrier TM0RM P10/P11 special function output
Chapter 6 8-bit Timers 6-3 8-bit Timer Count 6-3-1 Operation The timer operation can constantly generate interrupts. 8-bit Timer Operation (Timers 0, 1, 4 and 5) The generation cycle of timer interrupts is set by the clock source selection and the setting value of the compare register (TMnOC), in advance.
Chapter 6 8-bit Timers Count Timing of Timer Operation (Timers 0, 1, 4 and 5) Binary counter counts up with selected clock source as a count clock.
Chapter 6 8-bit Timers 6-3-2 Setup Example Timer Operation Setup Example (Timers 0, 1, 4 and 5) Timer function can be set by using timer 0 that generates the constant interrupt. By selecting fs/4 (at fosc = 20 MHz) as a clock source, interrupt is generated every 250 clock cycles (100 µs). An example setup procedure, with a description of each step is shown below. Setup Procedure (1) Stop the counter.
Chapter 6 8-bit Timers Setup Procedure (7) (8) Enable the interrupt. TM0ICR (x'3FE9') bp1 :TM0IE Description (7) Set the TM0IE flag of the TM0ICR register to "1" to enable the interrupt. (8) Set the TM0EN flag of the TM0MD register to "1" to start the timer 0. =1 Start the timer operation. TM0MD (x'3F54') bp3 :TM0EN =1 The TM0BC starts to count up from 'x00'.
Chapter 6 8-bit Timers 6-4 8-bit Event Count 6-4-1 Operation Event count operation has 2 types ; TMnIO input and synchronous TMnIO input can be selected as the count clock. 8-bit Event Count Operation Event count means that the binary counter (TMnBC) counts the input signal from external to the TMnIO pin. If the value of the binary counter reaches the setting value of the compare register (TMnOC), interrupts can be generated at the next count clock.
Chapter 6 8-bit Timers Count Timing of Synchronous TMnIO Input (Timers 0, 1, 4 and 5) If the synchronous TMnIO input is selected, the synchronizing circuit output signal is input to the timer n count clock. The synchronizing circuit output signal is changed at the falling edge of the system clock after TMnIO input signal is changed.
Chapter 6 8-bit Timers 6-4-2 Setup Example Event Count Setup Example (Timers 0, 1, 4 and 5) If the falling edge of the TM0IO input pin signal is detected 5 times with using timer 0, an interrupt is generated. An example setup procedure, with a description of each step is shown below. Setup Procedure (1) (2) Stop the counter. TM0MD (x'3F54') bp3 :TM0EN Description (1) Set the TM0EN flag of the timer 0 mode register (TM0MD) to "0" to stop timer 0 counting.
Chapter 6 8-bit Timers Setup Procedure (7) Enable the interrupt. TM0ICR (x'3FE9') bp1 :TM0IE (8) Start the event counting. TM0MD (x'3F54') bp3 :TM0EN Description (7) Set the TM0IE flag of the TM0ICR register to "1" to enable the interrupt. (8) Set the TM0EN flag of the TM0MD register to 1 to start timer 0. =1 =1 Every time TM0BC detects the falling edge of TM0IO input , TM0BC counts up from 'x00'.
Chapter 6 8-bit Timers 6-5 8-bit Timer Pulse Output 6-5-1 Operation The TMnIO pin can output a pulse signal with any cycle. Operation of Timer Pulse Output (Timers 0, 1, 4 and 5) The timers can output 2 x cycle signal, compared to the setting value in compare register (TMnOC).
Chapter 6 8-bit Timers 6-5-2 Setup Example Timer Pulse Output Setup Example (Timers 0, 1, 4 and 5) TM0IO (P10) pin outputs 50 kHz pulse by using timer 0. For this, select fosc as clock source, and set a 1/ 2 cycle (100 kHz) for the timer 0 compare register (at fosc=20 MHz). An example setup procedure, with a description of each step is shown below. Description Setup Procedure (1) (2) Stop the counter.
Chapter 6 8-bit Timers TM0BC counts up from x'00'. If TM0BC reaches the setting value of the TM0OC register, then TM0BC is cleared to x'00', TM0IO output signal is inverted and TM0BC restarts to count up from x'00'. At TMnOC = x'00', timer pulse output has the same waveform to at x'01'. If any data is written to compare register binary counter is stopped, timer output is reset to "L". Set the compare register value as follows.
Chapter 6 8-bit Timers 6-6 8-bit PWM Output The TMnIO pin outputs the PWM waveform, which is determined by the match timing for the compare register and the overflow timing of the binary counter. 6-6-1 Operation Operation of 8-bit PWM Output (Timers 0, 4 and 5) The PWM waveform with any duty cycle is generated by setting the duty cycle of PWM "H" period to the compare register (TMnOC). The cycle is the period from the full count to the overflow of the 8-bit timer.
Chapter 6 8-bit Timers Count Timing of PWM Output (when the compare register is x'00') (Timers 0, 4 and 5) Here is the count timing when the compare register is set to x'00' ; Count clock TMnEN flag Compare register 00 Binary counter TMnIO output (PWM output) 00 01 N-1 N N+1 N+2 FE FF 00 01 N N-1 N+1 H L Figure 6-6-2 Count Timing of PWM Output (when compare register is x'00') When TMnEN flag is stopped ("0") PWM output is "H".
Chapter 6 8-bit Timers 6-6-2 Setup Example PWM Output Setup Example (Timers 0, 4 and 5) The 1/4 duty cycle PWM output waveform is output from the TM0IO output pin at 128 Hz by using timer 0 (at fx=32.768 kHz). Cycle period of PWM output waveform is decided by the overflow of the binary counter. "H" period of the PWM output waveform is decided by the setting value of the compare register. An example setup procedure, with a description of each step is shown below.
Chapter 6 8-bit Timers Description Setup Procedure (5) Set the period of PWM "H" output. TM0OC (x'3F52') = x'40' (5) Set the "H" period of PWM output to the timer 0 compare register (TM0OC). The setting value is set to 256 / 4 = 64 (x'40'), because it should be the 1/4 duty of the full count (256). At that time, the timer 0 binary counter (TM0BC) is initialized to x'00'. (6) Start the timer operation.
Chapter 6 8-bit Timers 6-7 8-bit Timer Synchronous Output 6-7-1 Operation When the binary counter of the timer reaches the set value of the compare register, the latched data is output from port 6 at the next count clock. Synchronous Output Operation by 8-bit timer (Timer 1, Timer 5) The port 6 latched data is output from the output pin at the interrupt request generation by the match of the binary counter and the compare register.
Chapter 6 8-bit Timers 6-7-2 Setup Example Synchronous Output Setup Example (Timer 1, Timer 5) Setup example that latch data of port 6 is output constantly (100 µs) by using timer 1 from the synchronous output pin is shown below. The clock source of timer 1 is selected fs/8 (at fosc=8 MHz). An example setup procedure, with a description of each step is shown below. Setup Procedure (1) Start the counter.
Chapter 6 8-bit Timers Setup Procedure Description (7) Set the synchronous output event generation cycle. TM1OC (x'3F53') = x'63' (7) Set the synchronous output generation cycle to the timer 1 compare register (TM1OC). The setting value is set to 100-1=99(x'63'), because 1 MHz is divided by 10 kHz. At that time, the timer 1 binary counter (TM1BC) is initialized to x'00'. (8) Start the timer operation.
Chapter 6 8-bit Timers 6-8 Serial Interface Transfer Clock Output 6-8-1 Operation Serial interface transfer clock can be created by using the timer output signal. Serial InterfaceTransfer Clock Operation by 8-bit Timer (Timers 4 and 5) Timer 4 output can be used as a transfer clock source for serial interface 1. Timer 5 output can be used as a transfer clock source for serial interface 0.
Chapter 6 8-bit Timers 6-8-2 Setup Example Serial Interface Transfer Clock Setup Example (Timer 4) How to create a transfer clock for half duplex UART (Serial interface 1) using with timer 4 is shown below. The baud rate is selected to be 300 bps, the source clock of timer 4 is selected to be fs/4 (at fosc=8 MHz). An example setup procedure, with a description of each step is shown below. Setup Procedure (1) Stop the counter.
Chapter 6 8-bit Timers TM4BC counts up from x'00'. Timer 4 output is the clock of the serial interface 1 at transmission and reception. For the compare register setup value and the serial operation setup, refer to chapter 11. Serial Interface 0,1.
Chapter 6 8-bit Timers 6-9 Simple Pulse Width Measurement 6-9-1 Operation Timer measures the "L" duration of the pulse signal input from the external interrupt pin. Simple Pulse Width Measurement Operation by 8-bit Timer (Timers 0, 4 and 5) During the input signal of the external interrupt pin (simple pulse width) is "L", the binary counter of the timer counts up. Pulse width "L" period can be measured by reading the count of timer.
Chapter 6 8-bit Timers 6-9-2 Setup Example Set up Example of Simple Pulse Width Measurement by 8-bit Timer (Timers 0, 4 and 5) The pulse width of 'L" period of the external interrupt 2 (IRQ2) input signal is measured by timer 0. The clock source of timer 0 is selected to fosc. An example setup procedure, with a description of each step is shown below. Description Setup Procedure (1) (2) Stop the counter.
Chapter 6 8-bit Timers Setup Procedure (7) Enable the interrupt. IRQ2ICR (x'3FE4') bp1 :IRQ2IE (8) Description (7) Set the IRQ2IE flag of the IRQ2ICR register to "1" to enable the interrupt. (8) Set the TM0EN flag of the TM0MD register to "1" to enable timer 0 operation. =1 Enable the timer operation. TM0MD (x'3F54') bp3 :TM0EN =1 TM0BC starts to count up with negative edge of the external interrupt 2 (IRQ2) input as a trigger.
Chapter 6 8-bit Timers 6-10 Cascade Connection 6-10-1 Operation Cascading timers 0 and 1 form a 16-bit timer. 8-bit Timer Cascade Connection Operation (Timer 0 + Timer 1) Timer 0 and timer 1 are combined to be a 16-bit timer. Cascading timer is operated at clock source of timer 0 which is lower 8 bits.
Chapter 6 8-bit Timers At cascade connection, the binary counter and the compare register are operated as a 16 bit register. At operation, set the TMnEN flag of the upper and lower 8-bit timers to "1" to be operated. Also, the clock source is the one which is selected in the lower 8-bit timer. Other setup and count timing is the same to the 8-bit timer at independently operation. When timer 0 and timer 1 are used in cascade connection, timer 1 interrupt request flag is used.
Chapter 6 8-bit Timers 6-10-2 Setup Example Cascade Connection Timer Setup Example (Timer 0 + Timer 1) Setting example of timer function that an interrupt is constantly generated by cascade connection of timer 0 and timer 1, as a 16-bit timer is shown. An interrupt is generated in every 2500 cycles (1 ms) by selecting source clock to fs/4 (fosc=20 MHz at operation). An example setup procedure, with a description of each step is shown below.
Chapter 6 8-bit Timers Setup Procedure Description (7) Disable the lower timer interrupt. TM0ICR (x'3FE9') bp1 :TM0IE =0 (7) Set the TM0IE flag of the timer 0 interrupt control register (TM0ICR) to "0" to disable the interrupt. (8) Set the level of the upper timer interrupt. TM1ICR (x'3FEA') bp7-6 :TM1LV1-0 = 10 (8) Set the interrupt level by the TM1LV1-0 flag of the timer 1 interrupt control register (TM1ICR). If any interrupt request flag may be already set, clear all request flags.
Chapter 6 8-bit Timers 6-11 Remote Control Carrier Output 6-11-1 Operation Carrier pulse for remote control can be generated. Operation of Remote Control Carrier Output (Timer 0, Timer 5) Remote control carrier pulse is based on output signal of timer 0 or timer 5. Duty cycle is selected from 1/ 2, 1/3. RMOUT (P10/P11) outputs remote control carrier output signal.
Chapter 6 8-bit Timers 6-11-2 Setup Example Remote Control Carrier Output Setup Example (Timer 0, Timer 5) Here is the setting example that the RMOUT pin outputs the 1/3 duty carrier pulse signal with "H" period of 36.7 kHz, by using timer 0. The source clock of timer 0 is set to fosc (at 8 MHz). An example setup procedure, with a description of each step is shown below. Base period set by timer 0 (36.
Chapter 6 8-bit Timers Setup Procedure Description (6) Select the normal timer operation. TM0MD (x'3F54') bp4 : TM0PWM = 0 bp5 : TM0MOD = 0 (6) Set both of the TM0MOD flag and TM0PWM flag of the TM0MD register to "0" to select normal timer operation. (7) Select the count clock source. TM0MD (x'3F54') bp2-0 : TM0CK2-0 = 000 (7) Select fosc to clock source by the TM0CK2-0 flag of the TM0MD register. (8) Set the base cycle of remote control carrier.
Chapter 7 16-bit Timer 7
Chapter 7 16-bit Timer 7-1 Overview This LSI contains a general-purpose 16-bit timer (Timer 7). Its compare register is double buffer type. Timer 7 (high function 16-bit timer) has 2 sets of compare registers with double buffering. Also, as an independent interrupt it has a timer 7 interrupt and a timer 7 compare register 2 match interrupt. 7-1-1 Functions Table 7-1-1 shows the functions of timer 7.
Figure 7-1-1 TM7CK0 TM7CK1 TM7PS0 TM7PS1 TM7EN TM7CL Reserved Reserved 7 TM7MD1 0 M U X TM7IO input Synchronization M U X fosc M U X S 1/2 S 1/2 4-bit prescaler S 1/4 Capture trigger 1 1/2 1/4 1/16 M U X Capture operation enable / disable T7ICEN TM7MD2(bp2) M U X TM7ICH Match TM7OC1H RST Match TM7BCH TM7OC2H TM7PR2L RST Read TM7PR2H M U X M U X T7PWMSL TM7MD2(bp6) OVF Read/Write Read Data Load signal 16-Bit preset register 2 TM7OC2L 16-Bit output, compare register 2
Chapter 7 16-bit Timer 7-2 Control Registers Timer 7 contains the binary counter (TM7BC), the compare register 1 (TM7OC1), and its double buffer preset register (TM7PR1), the compare register 2 (TM7OC2) and its double buffer preset register 2 (TM7PR2), the capture register (TM7IC). The mode register 1 (TM7MD1) and the mode register 2 (TM7MD2) controls timer 7. 7-2-1 Registers Table 7-2-1 shows the registers that control timer 7.
Chapter 7 16-bit Timer 7-2-2 Programmable Timer Registers Timer 7 has a 16-bit programmable timer register. It contains a compare register, a preset register, a binary counter and a capture register. Each register has 2 sets of 8-bit register. Operate by 16-bit access. Compare register is a 16-bit register stores the value that compared to binary counter. The compared value that written to the preset register in advance is loaded.
Chapter 7 16-bit Timer The timer 7 preset register 1 and 2 are buffer registers of the timer 7 compare register 1 and 2. If the set value is written to the timer 7 preset register 1 and 2 when the counting is stopped, the same set value is loaded to the timer 7 compare register 1 and 2.
Chapter 7 16-bit Timer Binary counter is a 16-bit up counter. If any data is written to a preset register when the counting is stopped, the binary counter is cleared to x'0000'.
Chapter 7 16-bit Timer 7-2-3 Timer Mode Registers This is a readable / writable register that controls timer 7.
Chapter 7 16-bit Timer Timer 7 Mode Register 2 (TM7MD2) 7 TM7MD2 6 5 4 3 T7ICEDG T7PWMSL TM7BCR TM7PWM TM7IRS1 2 1 0 T7ICEN T7ICT1 T7ICT0 ( At reset : 0 0 0 0 0 0 0 0 ) T7ICT1 T7ICT0 0 1 0 IRQ0 (External interrupt 0) 1 IRQ1 (External interrupt 1) 0 IRQ2 (External interrupt 2) 1 IRQ3 (External interrupt 3) T7ICEN Input capture operation enable flag 0 Disable capture operation 1 Enable capture operation TM7IRS1 Timer 7 interrupt source selection 0 Counter clear 1 Match of
Chapter 7 16-bit Timer 7-3 16-bit Timer Count 7-3-1 Operation The timer operation can constantly generate interrupts. 16-bit Timer Operation (Timer 7) The generation cycle of an timer interrupt is set by the clock source selection and the set value of the compare register 1 (TM7OC1), in advance. When the binary counter (TM7BC) reaches the set value of the compare register 1, the timer 7 interrupt request is generated at the next count clock.
Chapter 7 16-bit Timer Table 7-3-2 shows the clock source that can be selected. Table 7-3-2 Clock Source at Timer Operation(Timer 7) Clock source 1 count time fosc 50 ns fosc/2 100 ns fosc/4 200 ns fosc/16 800 ns fs 100 ns fs/2 200 ns fs/4 400 ns fs/16 1.6 µs Notes : as fosc = 20 MHz fx = 32.768 kHz fs = fosc/2 = 10 MHz Count Timing of Timer Operation (Timer 7) The binary counter counts up with the selected clock source as the count clock.
Chapter 7 16-bit Timer (C) Even if the preset register is rewritten as the TM7EN flag is "1", the binary counter is not changed. (D) If the binary counter reaches the value of the compare register 1, the set value of the preset register is loaded to the compare register at the next count clock. And the interrupt request flag is set at the next count clock, and the binary counter is cleared to x'0000' to restart counting up. (E) If the TM7EN flag is"0", the binary counter is stopped.
Chapter 7 16-bit Timer 7-3-2 Setup Example Timer Operation Setup Example (Timer 7) Timer 7 generates an interrupt constantly for timer function. Fosc/2 (fosc=20 MHz) is selected as a clock source to generate an interrupt every 1000 cycles (100 µs). An example setup procedure, with a description of each step is shown below. Description Setup Procedure (1) Stop the counter. TM7MD1 (x'3F78') bp4 : TM7EN (1) Set the TM7EN flag of the timer 7 mode register 1 (TM7MD1) to "0" to stop timer 7 counting.
Chapter 7 16-bit Timer Setup Procedure (7) Start the timer operation. TM7MD1 (x'3F78') bp4 : TM7EN =1 Description (7) Set the TM7EN flag of the TM7MD1 register to "1" to start timer 7. TM7BC counts up from x'0000'. When TM7BC reaches the set value of the TM7OC1 register, the timer 7 interrupt request flag is set to "1" at the next count clock and the TM7BC becomes x'0000' and counts up, again.
Chapter 7 16-bit Timer 7-4 16-bit Event Count 7-4-1 Operation Event count operation has 2 types ; TM7IO input and synchronous TM7IO input can be selected as the count clock. Each type can select 1/1, 1/2, 1/4 or 1/6 as a count clock source. 16-bit Event Count Operation (Timer 7) Event count means that the binary counter (TM7BC) counts the input signal from external to the TM7IO pin.
Chapter 7 16-bit Timer Count Timing of Synchronous TM7IO Input (Timer 7) If the synchronous TM7IO input is selected, the synchronizing circuit output signal is input to the count clock. The synchronizing circuit output signal is changed at the falling edge of the system clock after the TM7IO input signal is changed. The binary counter counts up at the falling edge of the synchronizing circuit output signal or the synchronizing circuit output signal that passed through the divide-by circuit.
Chapter 7 16-bit Timer 7-4-2 Setup Example Event Count Setup Example (Timer 7) If the falling edge of the TM7IO input pin signal is detected 5 times with using timer 7, an interrupt is generated. An example setup procedure, with a description of each step is shown below. Setup Procedure (1) (2) Stop the counter. TM7MD1 (x'3F78') bp4 : TM7EN Description (1) Set the TM7EN flag of the timer 7 mode register 1 (TM7MD1) to "0" to stop timer 7 counting.
Chapter 7 16-bit Timer Setup Procedure (6) Description Set the interrupt level. TM7ICR (x'3FF1') bp7-6 :TM7LV1-0 = 10 (6) Set the interrupt level by the TM7LV1-0 flag of the timer 7 interrupt control register (TM7ICR). If any interrupt request flag may be already set, clear those request flags. [ (7) Enable the interrupt. TM7ICR (x'3FF1') bp1 : TM7IE (8) Start the event count. TM7MD1 (x'3F78') bp4 : TM7EN Chapter 3 3-1-4.
Chapter 7 16-bit Timer 7-5 16-bit Timer Pulse Output 7-5-1 Operation TM7IO pin can output a pulse signal with an arbitrary frequency. 16-bit Timer Pulse Output Operation (Timer 7) The timers can output 2 x cycle signal, compared to the setting value to the compare register 1 (TM7OC1) or 1/2 the frequency of the 16-bit full count. Output pin are as follows.
Chapter 7 16-bit Timer Count Timing of Timer Pulse Output (Timer 7) Count clock TM7EN flag Compare register 1 Binary counter N 0000 0001 N-1 N 0000 0001 N-1 N 0000 0001 N-1 N 0000 Interrupt request flag TM7IO output Figure 7-5-1 Count Timing of Timer Pulse Output (Timer 7) The TM7IO pin outputs 2 x cycle, compared to the value in the compare register 1.
Chapter 7 16-bit Timer 7-5-2 Setup Example Timer Pulse Output Setup Example (Timer 7) TM7IO pin outputs 50 kHz pulse by using timer 7. For this, select fosc as clock source, and set a 1/2 cycle (100 kHz) for the timer 7 compare register (at fosc=20 MHz). An example setup procedure, with a description of each step is shown below. Setup Procedure (1) (2) Stop the counter.
Chapter 7 16-bit Timer Setup Procedure Description (6) Set the timer pulse output cycle. TM7PR1 (X'3F75', X'3F74')=x'00C7' (6) (7) Release the reset of the timer pulse output. TM7MD1 (x'3F78') bp5 : TM7CL =0 Start the timer operation. TM7MD1 (x'3F78') bp4 : TM7EN =1 (7) Set the TN7CL flag of the TM7MD 1 register to "0" to enable the timer pulse output. (8) Set the TM7EN flag of the TM7MD1 register to "1" to start timer 7.
Chapter 7 16-bit Timer 7-6 16-bit Standard PWM Output (Only duty can be changed consecutively) The TM7IO pin outputs the standard PWM output, which is determined by the over flow timing of the binary counter, and the match timing of the timer binary counter and the compare register. 7-6-1 Operation 16-bit Standard PWM Output (Timer 7) PWM waveform with an arbitrary duty is generated by setting a duty of PWM "H" period to the compare register 1 (TM7OC1).
Chapter 7 16-bit Timer Count Timing of Standard PWM Output (when Compare Register 1 is x'0000')(Timer 7) Here is the count timing at setting x'0000' to the compare register 1. Count clock TM7EN flag Compare regsiter 1 0000 Binary counter 0000 0001 TM7IO output (PWM output) Figure 7-6-2 N N-1 FFFE FFFF 0000 0001 N+1 N+2 N N-1 N+1 H L Count Timing of Standard PWM Output (when Compare Register 1 is x'0000') PWM output shows "H ", when TM7EN flag is stopped (at "0").
Chapter 7 16-bit Timer 7-6-2 Setup Example Standard PWM Output Setup Example (Timer 7) The TM7IO output pin outputs the 1/4 duty PWM output waveform at 305.18 Hz with timer 7. The high frequency oscillation (fosc) is set to be operated at 20 MHz. One cycle of the PWM output waveform is decided by the overflow of a binary counter. "H" period of the PWM output waveform is decided by the set value of a compare register 1. An example setup procedure, with a description of each step is shown below.
Chapter 7 16-bit Timer Setup Procedure Description (5) Select the count clock source. TM7MD1 (x'3F78') bp1-0 : TM7CK1-0 = 00 bp3-2 : TM7PS1-0 = 00 (5) Select fosc at clock source by the TM7CK1-0 flag of the TM7MD1 register. Also, select 1/1 frequency (no division) at count clock source by the TM7PS1-0 flag. (6) Set "H" period of the PWM output. TM7PR1 (x'3F75', x'3F74')=x'4000' (6) Set "H" period of the PWM output to the timer 7 preset register 1 (TM7PR1).
Chapter 7 16-bit Timer 7-7 16-bit High Precision PWM Output (Cycle/Duty can be changed consecutively) The TM7IO pin outputs high precision PWM output, which is determined by the match timing of the timer binary counter and the compare register 1 and the match timing of the binary counter and the compare register 2.
Chapter 7 16-bit Timer Count Timing of High Precision PWM Output (When compare register 2 is x'0000'l) (Timer 7) Here is the count timing as the compare register 2 is set to x'0000' ; Count clock TM7EN flag Compare register 1 N Compare register 2 0000 Binary counter 0000 0001 TM7IO output (PWM output) N-1 N 0000 0001 H L Figure 7-7-2 Count Timing of High Precision PWM Output (When compare register 2 is x'0000') When the TM7EN flag is stopped (at "0"), the PWM output signal is "H".
Chapter 7 16-bit Timer 7-7-2 Setup Example High Precision PWM Output Setup Example (Timer 7) The TM7IO output pin outputs the 1/4 duty PWM output waveform at 400 Hz with timer 7. Select fosc/2 (at fosc = 20 MHz) as a clock source. One cycle of the PWM output waveform is decided by the set value of a compare register 1. "H" period of the PWM output waveform is decided by the set value of a compare register 2. An example setup procedure, with a description of each step is shown below.
Chapter 7 16-bit Timer Setup Procedure Description (5) Select the count clock source. TM7MD1 (x'3F78') bp1-0 : TM7CK1-0 = 00 bp3-2 : TM7PS1-0 = 01 (5) Select fosc as clock source by the TM7CK1-0 flag of the TM7MD1 register. Also, select 1/2 dividing as count clock source by the TM7PS10 flag. (6) Set the PWM output cycle. TM7PR1 (x'3F75',x'3F74') = x'61a7' (6) Set the PWM output cycle to the timer 7 preset register 1 (TM7PR1).
Chapter 7 16-bit Timer 7-8 16-bit Timer Synchronous Output 7-8-1 Operation When the binary counter of the timer reaches the set value of the compare register, the latched data is output from port 6 at the next count clock. Synchronous Output Operation by 16-bit Timer (Timer 7) The port 6 latched data is output from the output pin at the interrupt request generation by the match of the binary counter (TM7OC1) or by the full count overflow.
Chapter 7 16-bit Timer 7-8-2 Setup Example Synchronous Output Setup Example (Timer 7) Setup example that latched data of port 6 is output constantly (100 µs) by using timer 7 from the synchronous output pin is shown below. The clock source of timer 7 is selected fs/4 (at fosc=8 MHz). An example setup procedure, with a description of each step is shown below. Setup Procedure (1) Stop the counter.
Chapter 7 16-bit Timer Setup Procedure (7) Start the timer operation. TM7MD1 (x'3F78') bp4 : TM7EN =1 Description (7) Set the TM7EN flag of the TM7MD1 register to "1" to start timer 7. TM7BC counts up from x'0000'. If any data is written to the port 6 output register (P6OUT), TM7BC reaches the set value of TM7OC1 register and the synchronous output pin outputs data of port 7 in every time an interrupt request is generated.
Chapter 7 16-bit Timer 7-9 16-bit Timer Capture 7-9-1 Operation The value of a binary counter is stored to register at the timing of the external interrupt input signal, or the timing of writing operation with an arbitrary value to the capture register. Capture Operation with External Interrupt Signal as a Trigger (Timer 7) Capture trigger of input capture function is generated at the external interrupt signal that passed through the external interrupt interface block.
Chapter 7 16-bit Timer with the automatic data transfer function (ATC1). In the transfer mode 5 of ATC1, set the address of the input capture register TM7ICL to the memory pointer 1. The "H" period and "L" period of the input signal can be measured by transferring the value of the input capture register (TM7ICL, TM7ICH) to memory in every generation of a capture trigger.
Chapter 7 16-bit Timer In the initial state after releasing the reset, the generation of trigger by the external interrupt signal is disabled. Set the T7ICEN flag of the TM7MD2 register to "1" to enable the trigger generation.
Chapter 7 16-bit Timer 7-9-2 Setup Example Capture Function Setup Example (Timer 7) Pulse width measurement is enabled by storing the value of the binary counter to the capture register at the interrupt generation edge of the external interrupt 0 input signal with timer 7. The interrupt generation edge is specified to be the rising edge. An example setup procedure, with a description of each step is shown below.
Chapter 7 16-bit Timer Setup Procedure Description (6) Select the capture trigger generation edge. TM7MD2 (x'3F79') bp7 : T7ICEDG = 1 (6) Set the T7ICEDG flag of the TM7MD2 register to "1" to select the external interrupt valid edge as a generation source of capture trigger. (7) Set the compare register. TM7PR1(x'3F75',x'3F74') = x'FFFF' (7) Set the timer 7 preset register 1 (TM7PR1) to x'FFFF'.
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-1 Overview This LSI has a time base timer and a 8-bit free-running timer (timer 6). Time base timer is a 15-bit timer counter. These timers can stop the timer counting only at stand-by mode (STOP mode). 8-1-1 Functions Table 8-1-1 shows the clock sources and the interrupt generation cycles that timer 6 and time base timer can select.
Figure 8-1-1 fx fosc M U X 7 ST 1/2 15 1/2 13 1/2 12 1/2 10 1/2 9 1/2 8 1/2 7 TBCLR( Write only ) TM6CK3 TM6IR0 TM6IR1 TM6IR2 TM6CLRS TM6CK0 TM6CK1 TM6CK2 TM6MD 0 fx M U X Synchronous fs fosc M U X M U X RST TBIRQ Time base timer Read TM6BC 8-Bit counter match detection TM6OC Compare register Read/Write TM6IRQ 8-1-2 Timer 6 (8-Bit free-running timer) Chapter 8 Time Base Timer / 8-bit Free-running Timer Block Diagram Timer 6, Time Base Timer Block Diagram Block Diagram (Ti
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-2 Control Registers Timer 6 consists of binary counter (TM6BC), compare register (TM6OC), and is controlled by mode register (TM6MD). Time base timer is controlled by mode register (TM6MD) and time base timer clear register (TBCLR), too. 8-2-1 Control Registers Table 8-2-1 shows the registers that control timer 6, time base timer.
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-2-2 Programmable Timer Registers Timer 6 is a 8-bit programmable counter. Programmable counter consists of compare register (TM6OC) and binary counter (TM6BC). Binary counter is a 8-bit up counter. When the TM6CLRS flag of the timer 6 mode register (TM6MD) is "0" and the interrupt cycle data is written to the compare register (TM6OC), the timer 6 binary counter (TM6BC) is cleared to x'00'.
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-2-3 Timer Mode Registers This is a readable / writable register that controls timer 6 and time base timer.
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-3 8-bit Free-running Timer 8-3-1 Operation 8-bit Free-running Timer (Timer 6) The generation cycle of the timer interrupt is set by the clock source selection and the setting value of the compare register (TM6OC), in advance. If the binary counter (TM6BC) reaches the setting value of the compare register, an interrupt is generated at the next count clock, then the binary counter is cleared and counting is restarted from x'00'.
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-bit Free-running Timer as a 1 minute-timer, a 1 second-timer Table 8-3-2 shows the clock source selection and the TM6OC register setup, when a 8-bit free-running timer is used as a 1 minute-timer, a 1 second-timer. Table 8-3-2 1 minute-timer, 1 second-timer Setup (Timer 6) Interrupt Generation Cycle Clock Source TM6OC Register 1 min fx x 1/213 X'EF' fx x 1/212 X'07' fx x 1/213 X'03' 1s fx = 32.768(kHz) When the 1 minute-timer (1 min.
Chapter 8 Time Base Timer / 8-bit Free-running Timer Count Timing of Timer Operation (Timer 6) Binary counter counts up with the selected clock source as a count clock.
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-3-2 Setup Example Timer Operation Setup (Timer 6) Timer 6 generates an interrupt constantly for timer function. Fs(fosc = 20 MHz) is selected as a clock source to generate an interrupt every 250 cycles (25 µs). An example setup procedure, with a description of each step is shown below. Setup Procedure Description (1) Enable the binary counter initialization.
Chapter 8 Time Base Timer / 8-bit Free-running Timer If the TM6CLRS flag of the TM6MD register is set to "0", TM6BC can be initialized in every rewriting of TM6OC register, but in that state the timer 6 interrupt is disabled. If the timer 6 interrupt should be enabled, set the TM6CLRS flag to "1" after rewriting the TM6OC register. On the timer 6 clock source selection, either the time base timer output or the time base timer synchronous output is selected, the clock setup of time base timer is needed.
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-4 Time Base Timer 8-4-1 Operation Time Base Timer (Time Base Timer) The Interrupt is constantly generated. Table 8-4-1 shows the interrupt generation cycle in combination with the clock source ; Table 8-4-1 Time Base Timer Interrupt Generation Cycle Selected clock source Interrupt generation cycle fosc X 1/27 6.4 µs fosc X 1/28 12.8 µs fosc X 1/29 25.6 µs fosc X 1/210 51.2 µs fosc X 1/213 409.6 µs fosc X 1/215 1.64 ms fx X 1/27 3.
Chapter 8 Time Base Timer / 8-bit Free-running Timer Count Timing of Timer Operation (Time Base Timer) The counter counts up with the selected clock source as a count clock. 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fosc MUX fx 1/2 15 13 1/2 10 9 8 7 1/2 1/2 1/2 1/2 Figure 8-4-1 Count Timing of Timer Operation (Time Base Timer) When the selected interrupt cycle has passed, the interrupt request flag of the time base interrupt control register (TBICR) is set to "1".
Chapter 8 Time Base Timer / 8-bit Free-running Timer 8-4-2 Setup Example Timer Operation Setup (Time Base Timer) An interrupt can be generated constantly with time base timer in the selected interrupt cycle. The interrupt generation cycle is as fosc × 1/213 (as 0.977 ms : fosc = 8.38 MHz) for generation interrupts. An example setup procedure, with a description of each step is shown below.
Chapter 9 Watchdog Timer 9
Chapter 9 Watchdog Timer 9-1 Overview This LSI has a watchdog timer. This timer is used to detect software processing errors. It is controlled by the watchdog timer control register (WDCTR). And, once an overflow of watchdog timer is generated, a watchdog interrupt (WDIRQ) is generated. If the watchdog interrupt is generated twice, consecutively, it is regarded to be an indication that the software cannot execute in the intended sequence; thus, a system reset is initiated by the hardware.
Chapter 9 Watchdog Timer 9-2 Control Registers The watchdog timer is controlled by the watchdog timer control register (WDCTR).
Chapter 9 Watchdog Timer 9-3 Operation 9-3-1 Operation The watchdog timer counts system clock (fs) as a clock source. If the watchdog timer is overflowes, the watchdog interrupt (WDIRQ) is generated as an non maskable interrupt (NMI). At reset, the watchdog timer is stopped, but once the operation is enabled, it cannot be stopped except at reset. The watchdog timer control register (WDCTR) sets when the watchdog timer is released or how long the time-out period should be.
Chapter 9 Watchdog Timer How to Clear Watchdog Timer The watchdog timer can be cleared by writing to the watchdog timer control register (WDCTR). The watchdog timer can be cleared regardless of the writing data to the register. The bit-set (BSET) that does not change the value is recommended. Watchdog Timer Period The watchdog timer period is decided by the bp2, 1 (WDTS1-0) of the watchdog timer control register (WDCTR) and the system clock (fs).
Chapter 9 Watchdog Timer Watchdog Timer and CPU Mode The relation between this watchdog timer and CPU mode features are as follows ; (1) In NORMAL, IDLE, SLOW mode, the system clock is counted. (2) The counting is continued regardless of switching at NORMAL, IDLE, SLOW mode. (3) In HALT mode, the watchdog timer is stopped. (4) In STOP mode, the watchdog timer is cleared automatically by hardware. (5) In STOP mode, the watchdog interrupt cannot be generated.
Chapter 9 Watchdog Timer 9-3-2 Setup Example The watchdog timer detects errors. On the following example, the watchdog timer period is set to 218 × system clock, the lowest value for watchdog timer clear is set to 29 × system clock. An example setup procedure, with a description of each step is shown below. Initial Setup Program (Watchdog Timer Initial Setup Example) Description Setup Procedure (1) Set the time-out period.
Chapter 9 Watchdog Timer Interrupt Service Routine Setup Description Setup Procedure (1) Set the watchdog interrupt service routine. NMICR (x'03FE1') TBNZ (NMICR) WDIR, WDPRO ....... ....... ....... (1) If the watchdog timer overflows, the non maskable interrupt is generated. Confirm that the WDIR flag of the non maskable interrupt control register (NMICR) is "1" on the interrupt service routine, and manage the suitable execution. The operation, just before the WDOG interrupt may be executed wrongly.
Chapter 10 Buzzer 10
Chapter 10 Buzzer 10-1 Overview This LSI has a buzzer. It can output the square wave, having a frequency 1/29 to 1/214 of the high speed oscillation clock, or by 1/23 to 1/24 of the low speed oscillation clock.
Chapter 10 10-2 Buzzer Control Register Oscillation Stabilization Wait Timer Control Register 7 DLYCTR 6 5 4 3 2 1 BUZOE BUZS2 BUZS1 BUZS0 DLYS2 DLYS1 DLYS0 0 (At reset : 0 0 0 0 0 0 0 - ) - DLYS2 DLYS1 DLYS0 0 0 1 0 1 1 0 Oscillation stabilization wait period selection fs/214 1 fs/212 0 fs/210 1 fs/28 0 fs/26 1 fs/24 0 fs/22 Reserved 1 Note : After reset is released, the oscillation stabilization 14 wait period is fixed at 2 / fs.
Chapter 10 Buzzer 10-3 Operation 10-3-1 Operation Buzzer Buzzer outputs the square wave, having a frequency 1/29 to 1/214 of the high speed oscillation clock (fosc), or by 1/23 to 1/24 of the low speed oscillation clock (fx). The BUZS 2, 1, 0 flag of the oscillation stabilization wait control register (DLYCTR) set the frequency of buzzer output. The BUZOE flag of the oscillation stabilization wait control register (DLYCTR) sets buzzer output ON / OFF.
Chapter 10 10-3-2 Buzzer Setup Example Buzzer outputs the square wave of 2 kHz from P06 pin. It is used 8.38 MHz as the high oscillation clock (fosc). An example setup procedure, with a description of each step is shown below. Setup Procedure Description (1) Set the buzzer frequency. DLYCTR (x'3F4D') bp6-4 : BUZS2-0 = 010 (1) Set the BUZS2-0 flag of the oscillation stabilization wait control register (DLYCTR) to "010" to select fosc/212 to the buzzer frequency.
Chapter 11 Serial Interface 0,1 11
Chapter 11 Serial Interface 0, 1 11-1 Overview This LSI contains a serial interface 0 and 1 that can be used for both communication types of clock synchronous and UART (duplex). Also, the pins are changable to A (port 0) or B (port 7).
Chapter 11 Serial Interface 0, 1 11-1-1 Functions Table 11-1-1 shows functions of serial interface 0, 1.
Figure 11-1-1 Overview SBT0B/P72 SBT0A/P05 M U X SCOSBTS SBO0B/P70 SBO0A/P03 SBI0B/P71 SBI0A/P04 Serial Interface 0 Block Diagram 1/8 Clocl control circuit SC0STE SC0CKM P O L SC0CE1 MUX SC0SBIS SB0IOM M U X sc0psc (prescaler output) SCOSEL M U X SC0SEL M U X M U X M U X SC0MST SC0CKM SC0SBOS SC0SBIS SC0SBTS SC0IOM SC0MD1 SC0CMD 7 0 Received buffer RXBUF0 3 SC0FM0 SC0FM1 SC0RDB Reception shift register Transmission bit counter match match Reception bit counter BUSY gener
Figure 11-1-2 SBT1B/P75 SBT1A/P02 SCISBTS SBO1B/P73 SBO1A/P00 SBI1B/P74 M U X SC1CKM P O L Clock control circuit 1/8 MUX SC1STE SC1CE1 SB1IOM M U X SC1SBIS sc1psc (prescaler output) SC1SEL U X M SCISEL M U X M U X M U X SC1MST SC1CKM SC1SBOS SC1SBIS SC1SBTS SC1IOM 7 0 Transmission bit counter match Reception bit counter match SC1MD1 SC1CMD TXBUF1 Transmission buffer 3 SC1FM0 SC1FM1 SC1CE1 SC1REN SC1TRN SC1STE SC1DIR SC1LNG2 SC1MD0 SC1LNG0 SC1LNG1 IRQ control circuit
Chapter 11 Serial Interface 0, 1 11-2 Control Registers 11-2-1 Registers Table 11-2-1 shows registers to control serial interface 0, 1.
Chapter 11 Serial Interface 0, 1 11-2-2 Serial Interface 0 Data Buffer Registers Serial Interface 0 has each 8-bit data buffer register for transmission, and for reception.
Chapter 11 Serial Interface 0, 1 11-2-3 Serial Interface 0 Mode Registers Serial Interface 0 Mode Register 0 (SC0MD0) 7 SC0MD0 6 5 4 3 2 1 0 (At reset : 0 0 0 0 0 1 1 1 ) SC0CE1 SC0REN SC0TRN SC0DIR SC0STE SC0LNG2 SC0LNG1 SC0LNG0 SC0LNG2 SC0LNG1 SC0LNG0 0 0 1 0 1 1 SC0STE 2bit 0 3bit 1 4bit 0 5bit 1 6bit 0 1 8bit 7bit Synchronous serial transfer start condition Disable start condition Enable start condition First bit to be transferred 0 MSB first 1 LSB first Transmission dat
Chapter 11 Serial Interface 0, 1 Serial Interface 0 Mode Register 1 (SC0MD1) 7 SC0MD1 6 5 4 3 2 SC0IOM SC0SBTS SC0SBIS SC0SBOS SC0CKM SC0MST 1 0 - SC0CMD (At reset : 0 0 0 0 0 0 - 0 ) SC0CMD 0 Synchronous serial 1 Duplex UART SC0MST Clock master / slave selection 0 Clock slave 1 Clock master SC0CKM 1/8 dividing of transfer clock selection 0 Do not divide by 8 1 Divide by 8 SC0SBOS SBO0(TXD0) pin function selection 0 Port 1 Serial data output SC0SBIS Serial input control
Chapter 11 Serial Interface 0, 1 Serial Interface 0 Mode Register 2 (SC0MD2) SC0BRKF flag is only for reading. SC0MD2 4 7 6 5 SC0FM1 SC0FM0 SC0PM1 3 SC0PM0 SC0NPE 2 - 1 0 (At reset : 0 0 0 0 0 - 0 0 ) SC0BRKF SC0BRKE SC0BRKE Break status transmit control 0 Data transmission 1 Break transmission SC0BRKF Break status receive monitor (*) 0 Data tramsmission 1 Break transmission (*) Only read access is available.
Chapter 11 Serial Interface 0, 1 Serial Interface 0 Mode Register 3 (SC0MD3) All flags are only for reading.
Chapter 11 Serial Interface 0, 1 Serial Interface 0 Port Control Register (SC0ODC) 7 SC0ODC SC0SEL 6 5 4 Reseved - - 3 2 1 0 SC0ODC3 SC0ODC2 SC0ODC1 SC0ODC0 (At reset : 0 0 - - 0 0 0 0 ) SC0ODC0 0 Push-pull 1 Nch open-drain SC0ODC1 0 1 SC0ODC2 0 1 SC0ODC3 Figure 11-2-7 XI - 12 Control Registers PO3Nch open-drain control PO5Nch open-drain control Push-pull Nch open-drain P70Nch open-drain control Push-pull Nch open-drain P72Nch open-drain control 0 Push-pull 1 Nch open-drain
Chapter 11 Serial Interface 0, 1 Serial Interface 0 Transfer Clock Selection Register (SC0CKS) SC0CKS 7 6 5 4 3 - - - - - 2 1 0 (At reset : - - - - - X X X ) SC0PSC2 SC0PSC1 SC0PSC0 SC0PSC2 SC0PSC1 SC0PSC0 Clock selection 0 fosc/2 1 fosc/4 0 fosc/16 1 fosc/64 0 0 1 fs/2 1 X Timer 5 output 0 0 1 1 Figure 11-2-8 fs/4 Serial Interface 0 Tranfer Clock Selection Register (SC0CKS : x'03F97', R/W) Control Registers XI - 13
Chapter 11 Serial Interface 0, 1 11-2-4 Serial Interface 1 Data Buffer Registers Serial Interface 1 has each 8-bit data buffer register for transmission, and for reception.
Chapter 11 Serial Interface 0, 1 11-2-5 Serial Interface 1 Mode Registers Serial Interface1 Mode Register 0 (SC1MD0) 7 SC1MD0 6 5 4 3 2 1 0 (At reset : 0 0 0 0 0 1 1 1 ) SC1CE1 SC1REN SC1TRN SC1DIR SC1STE SC1LNG2 SC1LNG1 SC1LNG0 SC1LNG2 SC1LNG1 SC1LNG0 0 0 1 0 1 1 SC1STE 0 1bit 1 2bit 0 3bit 1 4bit 0 5bit 1 6bit 0 1 8bit 7bit Synchronous serial transfer start condition 0 Disable start condition 1 Enable start condition SC1DIR First bit to be transferred 0 MSB first 1
Chapter 11 Serial Interface 0, 1 Serial Interface 1 Mode Register 1 (SC1MD1) 7 SC1MD1 6 5 4 3 2 SC1IOM SC1SBTS SC1SBIS SC1SBOS SC1CKM SC1MST 1 0 - SC1CMD (At reset : 0 0 0 0 0 0 - 0 ) SC1CMD 0 Synchronous serial 1 Duplex UART SC1MST Clock master / slave selection 0 Clock slave 1 Clock master SC1CKM Do not divide by 8 1 Divide by 8 Port 1 Serial data output SC1SBIS Serial input control 0 "1" input 1 Serial input SBT0 pin function selection 0 Port 1 Transfer clock I/O
Chapter 11 Serial Interface 0, 1 Serial Interface 1 Mode Register 2 (SC1MD2) SC1BRKF flag is only for reading. 7 SC1MD2 6 5 4 3 SC1FM1 SC1FM0 SC1PM1 SC1PM0 SC1NPE 2 - 1 0 (At reset : 0 0 0 0 0 - 0 0 ) SC1RKF SC1BRKE SC1BRKE Break status transmit control 0 Data transmission 1 Break transmission SC1BRKF Break status receive monitor (*) 0 Data tramsmission 1 Break transmission (*) Only read access is available.
Chapter 11 Serial Interface 0, 1 Serial Interface 1 Mode Register 3 (SC1MD3) All flags are only for reading.
Chapter 11 Serial Interface 0, 1 Serial Interface 1 Port Control Register (SC1ODC) SC1ODC 7 6 5 4 SC1SEL Reseved - - 3 2 1 0 SC1ODC3 SC1ODC2 SC1ODC1 SC1ODC0 (At reset : 0 0 - - 0 0 0 0 ) SC1ODC0 0 Push-pull 1 N ch open-drain SC1ODC1 P02 N ch open-drain control 0 Push-pull 1 N ch open-drain SC1ODC2 P73 N ch open-drain control 0 Push-pull 1 N ch open-drain SC1ODC3 Figure 11-2-15 P00 N ch open-drain control P75 N ch open-drain control 0 Push-pull 1 N ch open-drain Rese
Chapter 11 Serial Interface 0, 1 Serial Interface1 Transfer Clock Selection Register (SC1CKS) SC1CKS 7 6 5 4 3 - - - - - 2 1 0 (At reset : - - - - - X X X ) SC1PSC2 SC1PSC1 SC1PSC0 SC1PSC2 SC1PSC1 SC1PSC0 Clock selection 0 fosc/2 1 fosc/4 0 fosc/16 1 fosc/64 0 0 1 fs/2 1 X Timer 4 output 0 0 1 1 Figure 11-2-16 XI - 20 fs/4 Serial Interface 1 Tranfer Clock Selection Register (SC1CKS : x'03F9F', R/W) Control Registers
Chapter 11 Serial Interface 0, 1 11-3 Operation Serial Interface 0, 1 can be used for both clock synchronous and duplex UART. 11-3-1 Clock Synchronous Serial Interface Activation Factor for Communication Table 11-3-1 shows activation factors for communication. At master, the transfer clock is generated by setting data to the transmission data buffer TXBUFn, or by receiving a start condition. Except during communication, the input signal from SBT0 pin is masked to prevent errors by noise or so.
Chapter 11 Serial Interface 0, 1 Start Condition Setup The SCnSTE flag of the SCnMD0 register sets if a start condition is enabled or not. If a start condition is enabled, and received at communication, a bit counter is cleared to restart the communication. The start condition, if the SCnCE1 flag of the SCnMD0 register is set to "0", is regarded when a data line (SBI pin (with 3 channels) or SBO pin (with 2 channels) is changed from "H" to "L" as a clock line (SBT pin) is "H".
Chapter 11 Serial Interface 0, 1 Tranfer Bit Count and First Transfer Bit When the transfer bit is 1 bit to 7 bits, the data storing method to the transmission data buffer TXBUFn is different, depending on the first transfer bit selection. At MSB first, use the upper bits of TXBUFn for storing. When there are 6 bits to be transfered, as shown on figure 11-3-1, if data "A" to "F" are stored to bp2 to bp7 of TXBUFn, the transmission is operated from "F" to "A".
Chapter 11 Serial Interface 0, 1 Continuous Communication This serial has a function for continuous communication. If data is set to the transmission data buffer TXBUFn during communication, the transmission buffer empty flag SCnTEMP is automatically set to communicate continuously. Data setup to TXBUFn should be done till the communication complete interrupt SCnTIRQ is generated after the former data is set.
Chapter 11 Serial Interface 0, 1 Clock Setup The SCnCKS register selects a clock source from the special prescaler and timer 4 output. The special prescaler starts its operation after the PSCMD (x'03F6F') register selects "prescaler operation". The SCnMST flag of the SCnMD1 register can select the internal clock (clock master), or the external clock (clock slave).
Chapter 11 Serial Interface 0, 1 Received Buffer Empty Flag When the reception is completed (the last data reception edge of the clock is input), data is stored to RXBUFn from the internal shift register, automatically. If data is stored to the shift register RXBUFn, the received buffer empty flag SCnREMP of the SCnMD3 register is set to "1". That indicates that the received data is going to be read. SCnREMP is cleared to "0" by reading out the data of RXBUFn.
Chapter 11 Serial Interface 0, 1 Emergency Reset It is possible to shut down communication. For a forced reset, the SCnSBOS flag and the SCnSBIOS flag of the SCnMD1 register should be set to "0" (SBO pin : port, input data : "1" input). At forced reset, the status registers (the SCnBRKF flag of the SCnMD2 register, all flags of the SCnMD3 register) are initialized as they are set at reset, but the control register holds the setting value.
Chapter 11 Serial Interface 0, 1 Trasnmission Timing (at master) Tmax=T (at slave) (at master) Tmax=2.5 T Tmax=2 T T Clock (SBT pin) Output data (White SBO pin) 0 Transfer bit counter 1 2 3 4 5 6 7 SCnTBSY ∆ (Write data to TXBUFn) Interrupt (SCnTIRQ) Figure 11-3-5 Transmission Timing (falling edge, start condition is enabled) (at master) Tmax=T (at slave) (at master) Tmax=1.
Chapter 11 Serial Interface 0, 1 (at master) Tmax=T (at slave) (at master) Tmax=2.5 T Tmax=2 T T Clock (SBT pin) Output data (SBO pin) 0 Transfer bit counter 1 3 2 4 5 6 7 SCnTBSY ∆ (Write data to TXBUFn) Interrupt (SCnTIRQ) Figure 11-3-7 Transmission Timing (rising edge, start condition is enabled) (at master) Tmax=T (at slave) (at master) Tmax=1.
Chapter 11 Serial Interface 0, 1 Reception Timing (at master) Tmax=2.5 T T Clock (SBT pin) Input data (SBI pin) 0 Transfer bit counter 1 2 3 4 5 6 7 SCnRBSY ∆ (Write data to TXBUFn) Interrupt (SCnTIRQ) Figure 11-3-9 Reception Timing (rising edge, start condition is enabled) (at master) Tmax=1.
Chapter 11 Serial Interface 0, 1 (at master) T Tmax=2.5 T Clock (SBT pin) Input data (SBI pin) 0 Transfer bit counter 1 2 3 4 5 6 7 SCnRBSY ∆ (Write data to TXBUFn) Interrupt (SCnTIRQ) Figure 11-3-11 Reception Timing (falling edge, start condition is enabled) (at master) Tmax=1.
Chapter 11 Serial Interface 0, 1 Transmission / Reception Timing When transmission and reception are operated at the same time, set the SCnCE1 flag of the SCnMD0 register to "0" or "1". Data is received at the opposite edge of the transmission clock, so that the reception clock should be the opposite edge of the transmission clock from the other side. SBT pin Data is received at the rising edge of clock. SBI pin Data is output at the falling edge of clock.
Chapter 11 Serial Interface 0, 1 11-3-2 Serial interface 0 Synchronous Serial Interface Pin Setup Serial Interface 0 Pins Setup (3 channels, at transmission) Table 11-3-6 shows the setup for synchronous serial interface pin with 3 channels (SBO0 pin, SBI0 pin, SBT0 pin) at transmission.
Chapter 11 Serial Interface 0, 1 Serial Interface 0 Pins Setup (3 channels, at transmission / reception) Table 11-3-8 shows the setup for synchronous serial interface pin with 3 lines (SBO0 pin, SBI0 pin, SBT0 pin) at transmission / reception.
Chapter 11 Serial Interface 0, 1 Serial Interface 0 Pins Setup (2 channels, at transmission) Table 11-3-9 shows the setup for synchronous serial interface pin with 2 channels (SBO0 pin, SBT0 pin) at transmission. SBI0 pin can be used as a general port.
Chapter 11 Serial Interface 0, 1 11-3-3 Serial interface 1 Synchronous Serial Interface Pin Setup Serial Interface 1 Pins Setup (3 channels, at transmission) Table 11-3-11 shows the setup for synchronous serial interface pin with 3 channels (SBO1 pin, SBI1 pin, SBT1 pin) at transmission.
Chapter 11 Serial Interface 0, 1 Serial Interface 1 Pins Setup (3 channels, at transmission / reception) Table 11-3-13 shows the setup for synchronous serial interface pin with 3 lines (SBO1 pin, SBI1 pin, SBT1 pin) at transmission / reception.
Chapter 11 Serial Interface 0, 1 Serial Interface 1 Pins Setup (2 channels, at transmission) Table 11-3-14 shows the setup for synchronous serial interface pin with 2 channels (SBO1 pin, SBT1 pin) at transmission. SBI1 pin can be used as a general port.
Chapter 11 Serial Interface 0, 1 11-3-4 Setup Example Transmission / Reception Setup Example The setup example for clock synchronous serial communication with serial 0 is shown. Table 11-3-16 shows the conditions at transmission / reception.
Chapter 11 Serial Interface 0, 1 Setup Procedure Description (6) Select the transfer bit count. SC0MD0 (x'3F92') (6) Set the SC0LNG2-0 flag of the serial 0 mode register (SC0MD0) to "111" to set the transfer bit count "8 bits". (7) Select the start condition. SC0MD0 (x'3F92') bp3 : SC0STE = 0 (7) Set the SC0STE flag of the SC0MD0 register to "0" to disable start condition. (8) Select the first bit to be transfered.
Chapter 11 Serial Interface 0, 1 Setup Procedure Description (15) Set the interrupt level. SC0TICR(x'3FF5') bp7-6 : SC0TLV1-0 = 10 (15) Set the interrupt level by the SC0TLV1-0 flag of the serial 0 transmission interrupt control register (SC0TICR). (Set level 2.) (16) Enable the interrupt. SC0TICR(x'3FF5') bp1 : SC0TIE = 1 (16) Set the SC0TIE flag of the SC0TICR register to "1" to enable interrupts.
Chapter 11 Serial Interface 0, 1 11-3-5 UART Serial Interface Serial 0, 1 can be used for duplex UART communication. Table 11-3-17 shows UART serial interface functions.
Chapter 11 Serial Interface 0, 1 Activation Factor for Communication At transmission, if any data is written to the transmission data buffer TXBUFn, a start condition is generated to start transfer. At reception, if a start condition is received, communication is started. At reception, if the data length of "L" for start bit is longer than 0.5 bit, that can be regarded as a start condition. Transmission Data transfer is automatically started by writing data to the transmission data buffer TXBUFn.
Chapter 11 Serial Interface 0, 1 Reception BUSY flag When the start condition is reagarded, the SCnRBSY flag of the SCnMD3 register is set to "1". That is cleared to "0" by the generation of the reception complete interrupt SCnRIRQ. If, during reception, the SCnSBIS flag is set to "0", the SCnRBSY flag is reset to "0". Transmission BUSY flag When any data is set to TXBUFn, the SCnTBSY flag of the SCnMD3 register is set to "1".
Chapter 11 Serial Interface 0, 1 The SCnFM1 to 0 flag of the SCnMD2 register sets the frame mode. Table 11-3-19 is shown the UART Serial Interface Frame Mode setting. If the SCnCMD flag of the SCnMD1 register is set to "1", and UART communication is selected, the transfer bit count on the SCnLNG2 to 0 flag of the SCnMD0 register is no more valid.
Chapter 11 Serial Interface 0, 1 Reception Error At reception , there are 3 types of error ; overrun error, parity error and framing error. Reception error can be determined by the SCnORE, SCnPEK, SCnFEF flag of the SCnMD3 register. Even one of those errors is detected, the SCnERE flag of the SCnMD3 register is set to "1". The SCnPEK, the SCnFEF flags in recepption error flag are renewed at generation of the reception complete interrupt SCnRIRQ.
Chapter 11 Serial Interface 0, 1 Transmission/reception data polarity switching In UART communication, polarity of transmission/reception data cannot be switched. At the same time, setups of the SCnTRN, SCnREN flags of the SCnMD0 register are invalid. Clock Setup At UART communication, the transfer clock is not needed, but the clock setup should be needed to decide the timing of the data transmission / reception in the serial interface.
Chapter 11 Serial Interface 0, 1 The following items are same to clock synchronous serial.
Chapter 11 Serial Interface 0, 1 Transmission Timing T parity bit TXD pin stop bit stop bit SCnTBSY ∆ write data to TXBUFn Interrupt (SCnTIRQ) Figure 11-3-16 Transmission Timing (parity bit is enabled) T stop bit TXD pin stop bit SCnTBSY ∆ write data to TXBUFn Interrupt (SCnTIRQ) Figure 11-3-17 Transmission Timing (parity bit is disabled) Operation XI - 49
Chapter 11 Serial Interface 0, 1 Reception Timing Tmin=0.5 T T Parity bit RXD pin Stop bit SCnRBSY ∆ input start condition Interrupt (SCnRIRQ) Figure 11-3-18 Tmin=0.
Chapter 11 Serial Interface 0, 1 Transfer Rate Baud rate timer (timer 2 and timer 4) can set any transfer rate. Tables 11-3-22, 23 show the setup example of the transfer rate. For detail of the baud rate timer setup, refer to chapter 6. 8-bit Timer.
Chapter 11 Serial Interface 0, 1 Table 11-3-24-1 UART Serial Interface Transfer Rate (decimal) Transfer rate (bps) fosc (MHz) Clock source (timer) 4.
Chapter 11 Serial Interface 0, 1 Table 11-3-24-2 UART Serial Interface Transfer Rate (decimal) Transfer rate (bps) fosc (MHz) Clock source (timer) 4.
Chapter 11 Serial Interface 0, 1 11-3-6 Serial interface 0 UART Serial Interface Pin Setup Serial Interface 0 Pin Setup (1, 2 channels, at transmission) Table 11-3-25 shows the pins setup at UART serial interface 0 transmission. The pins setup is common to the TXD0 pin, RXD0 pin, regardless of those pins are independent / connected.
Chapter 11 Serial Interface 0, 1 Serial Interface 0 Pin Setup (1 channel, at reception) Table 11-3-27 shows the pin setup at UART serial interface 0 reception with 1 channel (TXD0 pin). The RXD0 pin is not used, so can be used as a port.
Chapter 11 Serial Interface 0, 1 11-3-7 Serial interface 1 UART Serial Interface Pin Setup Serial Interface 1 Pin Setup (1, 2 channels, at transmission) Table 11-3-29 shows the pins setup at UART serial interface 1 transmission. The pins setup is common to the TXD1 pin, RXD1 pin, regardless of those pins are independent / connected.
Chapter 11 Serial Interface 0, 1 Serial Interface 1 Pin Setup (1 channel, at reception) Table 11-3-31 shows the pin setup at UART serial interface reception with 1 channel (TXD1 pin). The RXD1 pin is not used, so can be used as a port.
Chapter 11 Serial Interface 0, 1 11-3-8 Setup Example Transmission / Reception Setup The setup example at UART transmission / reception with serial 0 is shown. Table 11-3-33 shows the conditions at transmission / reception.
Chapter 11 Serial Interface 0, 1 Setup Procedure Description (6) Select the start condition. SC0MD0 (x'3F92') bp3 : SC0STE = 1 (6) Set the SC0STE flag of the SC0MD0 register to "1" to enable start condition. (7) Select the first bit to be transfered. SC0MD0 (x'3F92') bp4 : SC0DIR = 0 (7) Set the SC0DIR flag of the SC0MD0 register to "0" to select MSB as first transfer bit. (8) Control the output data.
Chapter 11 Serial Interface 0, 1 Setup Procedure (14) Enable the interrupt. SC0RICR(x'3FF4') bp1 : SC0RIE = 1 SC0TICR(x'3FF5') bp1 : SC0TIE = 1 Description (14) Set the SC0RIE flag of the SC0RICR register to "1", and set the SC0TIE flag ot the SC0TICR register to "1" to enable the interrupt request. If any interrupt request flag is already set, clear them. [ (15) Set the baud rate timer. Chapter 3. 3-1-4 Interrupt Flag Setup ] (15) Set the baud rate timer by the TM5MD register, the TM5OC register.
Chapter 12 Serial Interface 3 12 18
Chapter 12 Serial Interface 3 12-1 Overview This LSI contains a serial interface 3 can be used for both communication types of clock synchronous and simple IIC (single master). 12-1-1 Functions Table 12-1-1 shows the functions of serial interface 3.
Figure 12-1-1 M U X POL POL Clock SC3STE control circuit 7 SC3BSY SC3IOM 7 SC3STC IICBSY SC3CE1 SC3SBTS - SC3SBIS SC3REX SC3CMD SC3ACKS SC3ACKO SC3CTR SC3DIR SC3STE - 0 M U X 7 0 SC3IRQ SBO3/SDA/P51 SC3SBOS SC3SBOS SC3LNG2 SC3LNG1 SC3LNG0 SC3MD0 IRQ control circuit Start condition generation circuit SC3STE SC3DIR SC3MST - - SC3MD1 0 3 Transfer bit counter Shift register SC3TRB SWAP Read/Write BUSY generation circuit IIC clcok generation sircuit ACK control c
Chapter 12 Serial Interface 3 12-2 Control Registers 12-2-1 Registers Table 12-2-1 shows the registers to control serial interface 3.
Chapter 12 12-2-2 Serial Interface 3 Data Register Serial interface 3 has a 8-bit serial data register.
Chapter 12 Serial Interface 3 12-2-3 Mode Registers Serial Interface 3 Mode Register 0 (SC3MD0) SC3MD0 7 6 5 4 SC3BSY SC3CE1 - SC3DIR 3 2 1 0 (At reset: 00 - 0 0 1 1 1 ) SC3STE SC3LNG2 SC3LNG1 SC3LNG0 Transfer bit count SC3LNG2 SC3LNG1 SC3LNG0 0 0 1 0 1 1 SC3STE 0 1bit 1 2bits 0 3bits 1 4bits 0 5bits 1 6bits 0 1 8bits 7bits Synchronous serial data tranfer start condition 0 Disable start condition 1 Enable start condition SC3DIR First bit to be transferred 0 MSB
Chapter 12 Serial Interface 3 Serial Interface 3 Mode Register 1 (SC3MD1) 7 SC3MD1 6 5 4 SC3IOM SC3SBTS SC3SBIS SC3SBOS 3 2 1 0 - SC3MST - - (At reset: 0 0 0 0 - 0 - -) SC3MST 0 Slave 1 Mater SC3SBOS Selection of SBO3 pin's function 0 Port 1 Serial data output SC3SBIS Serial input control 0 "1" input 1 Serial data input SC3SBTS Selection of the SBT3 pin function 0 Port 1 Transfer clock input/output SC3IOM Serial data input selection 0 1 Figure 12-2-3 Clock master/
Chapter 12 Serial Interface 3 Serial Interface 3 Control Register (SC3CTR) SC3CTR 7 6 5 4 IICBSY SC3STC - - 3 2 1 0 SC3REX SC3CMD SC3ACKS SC3ACKO (At reset: 0 0 - - 0 0 0 0 ) SC3ACKO ACK bit level specification 0 "L" level 1 "H" level SC3ACKS ACK bit enable 0 ACK bit is disabled 1 ACK bit is enabled SC3CMD Clock synchronous / IIC selection 0 Clock synchronous 1 IIC selection SC3REX 0 1 SC3STC (at IIC communication) transmission / reception mode selection Transmission R
Chapter 12 Serial Interface 3 Serial Interface 3 Port Control Register (SC3ODC) SC3ODC 7 6 5 4 3 2 - Reserved - - - - 1 0 (At reset: - 0 - - - - 0 0 ) SC3ODC1 SC3ODC0 P51 N-ch open drain control SC3ODC0 0 Push-pull 1 N-ch open-drain P52 N-ch open-drain control SC3ODC1 0 Push-pull 1 N-ch open-drain Reserved Figure 12-2-5 Set Always to "0" Serial Interface 3 Port Control Register (SC3ODC : x'03FAE', R/W) Serial Interface 3 Transfer Clock Selection Register (SC3CKS) 7 6 5
Chapter 12 Serial Interface 3 12-3 Operation This LSI contains a serial interface 3 that can be used for both communication types of clock synchronous and single master IIC. 12-3-1 Clock Synchronous Serial Interface Activation Factor for Communication Table 12-3-1 shows the activation factor for communication. At master communication, the transfer clock is generated by setting data to the transmit/receive shift register SC3TRB, or by receiving start condition.
Chapter 12 Serial Interface 3 First Transfer Bit Setup The first bit to be transferred can be set by the SC3DIR flag of the SC3MD0 register. MSB first or LSB first can be selected. Transmit /Receive Data Buffer Data register for transmission/reception is common. That is the transmit/receive shift register SC3TRB. The transmission data should be set to SC3TRB. The transfer clock outputs data by 1 bit in shift. The received data is stored to SC3TRB by 1 bit in shift.
Chapter 12 Serial Interface 3 Continuous Communication Serial interface 3 can be started by automatic data transfer function ATC1, built-in this LSI. If ATC1 is used for activation, data can be continuously transferred up to 255 byte. The communication blank, from the generation of the communication complete interrupt SC3IRQ to the generation of the next transfer clock, is up to 18 machine cycles + 2 transfer clocks.
Chapter 12 Table 12-3-3 SC3CE1 Serial Interface 3 Input Edge/Output Edge of Transmission/Received Data Transmission data output edge Received data input edge 0 1 Data Input Pin Setup There are 2 communication modes to be selected : 3 channels type (clock pin(SBT3 pin), data output pin (SBO3 pin), data input pin (SBI3 pin)), 2 channels type (clock pin (SBT3 pin), data I/O pin (SBO3 pin)). The SBI3 pin can be used only for serial data input. The SBO3 pin can be used for serial data input or output.
Chapter 12 Serial Interface 3 Transmission Timing at master Tmax=2.5 T at slave Tmax=1.5 T T Clock (SBT3 pin) Output data (SBO3 pin) 0 Transfer bit counter 1 2 3 4 5 6 7 SC3BSY (Write data to SC3TRB) Interrupt (SC3IRQ) Figure 12-3-2 Transmission Timing (Falling edge, Enable Start Condition) at master Tmax=1.5 T at slave Tmax=1.
Chapter 12 at master Tmax=2.5 T Serial Interface 3 at slave Tmax=1.5 T T Clock (SBT3 pin) Output data (SBO3 pin) 0 Transfer bit counter 1 2 3 4 5 6 7 SC3BSY (Write data to SC3TRB) Interrupt (SC3IRQ) Figure 12-3-4 Transmission Timing (Rising edge, Enable Start Condition) at master Tmax=1.5 T at slave Tmax=1.
Chapter 12 Serial Interface 3 Reception Timing at master Tmax=2.5 T T Clock (SBT3 pin) Input data (SBI3 pin) 0 Transfer bit counter 1 2 3 4 5 6 7 SC3BSY (Write data to SC3TRB) interrupt (SC3IRQ) Figure 12-3-6 Reception Timing (Rising edge, Enable Start Condition) at master Tmax=1.
Chapter 12 at master Tmax=2.5 T Serial Interface 3 T Clock (SBT3 pin) Input data (SBI3 pin) 0 Transfer bit counter 1 2 3 4 5 6 7 SC3BSY (Write data to SC3TRB) Interrupt (SC3IRQ) Figure 12-3-8 Reception Timing (Falling edge, Enable Start Condition) at master Tmax=1.
Chapter 12 Serial Interface 3 Transmission/Reception Simultaneous timing When transmission and reception are operated at the same time, data is recieved at the opposite edge of the transmission clock. SBT3 pin Data is input at the rising edge of the clock. SBI3 pin Data is output at the falling edge of the clock. SBO3 pin Figure 12-3-10 Transmission/Reception Timing (Reception : Rising edge, Transmission : Falling edge) SBT3 pin Data is input at the falling edge of the clock.
Chapter 12 Serial Interface 3 Pin Setup (3 channels, at transmission) Table 12-3-5 shows the pins setup at synchronous serial interface transmission with 3 channels (SBO3 pin, SBI3 pin, SBT3 pin).
Chapter 12 Serial Interface 3 Pin Setup (3 channels, at reception) Table 12-3-6 shows the pins setup at synchronous serial interface reception with 3 channels (SBO3 pin, SBI3 pin, SBT3 pin).
Chapter 12 Serial Interface 3 Pin Setup (3 channels, at transmission/reception) Table 12-3-7 shows the pins setup at synchronous serial interface transmission/reception with 3 channels (SBO3 pin, SBI3 pin, SBT3 pin).
Chapter 12 Serial Interface 3 Pin Setup (2 channels, at transmission) Table 12-3-8 shows the pins setup at synchronous serial interface transmission with 2 channels (SBO3 pin, SBT3 pin). The SBI3 pin is not used, so that it can be used as a general port.
Chapter 12 Serial Interface 3 Pin Setup (2 channels, at reception) Table 12-3-9 shows the pins setup at synchronous serial interface reception with 2 channels (SBO3 pin, SBT3 pin). The SBI3 pin is not used, so that it can be used as a general port.
Chapter 12 Serial Interface 3 13-3-2 Setup Example Transmission/Reception Setup Example Here is the setup example for transmission/reception with serial interface 3. Table 12-3-10 shows the conditions.
Chapter 12 Setup Procedure Serial Interface 3 Description (6) Select the transfer bit count. SC3MD0 (x'3FA8') bp2-0 : SC3LNG2-0 = 111 (6) Set the SC3LNG2-0 flag of the serial 3 mode register (SC3MD0) to "111" to set the transfer bit count to 8 bits. (7) Select the start condition. SC3MD0 (x'3FA8') bp3 : SC3STE = 1 (7) Set the SC3STE flag of the SC3MD0 register to "1" to enable start condition. (8) Select the first transfer bit.
Chapter 12 Serial Interface 3 Setup Procedure (15) Start serial transmission. Transmission data → SC3TRB (x'3FAB') Description (15) Set the transmission data to the serial transmit/receive shift register SC3TRB. The internal clock is generated to start transmission/reception. After the communication is finished, the serial 3 interrupt SC3IRQ is generated. Note : In the above settings, (6) to (9), (10) to (11),can be set at once.
Chapter 12 12-3-3 Serial Interface 3 Single Master IIC Interface IIC serial communication in single master is available at serial interface 3. Communication of this IIC interface is based on the data transfer format of Philips, IIC-BUS. Table 12-3-11 shows the functions of IIC serial interface.
Chapter 12 Serial Interface 3 Start Condition Setup At IIC communication, enable start condition by the SC3STE flag of the SC3MD0 register at the beginning of communication. The SC3STE flag of the SC3MD0 register can select if start condition is enabled or not. If start condition is detected during data communication when the start condition is enabled, the SC3STC flag of the SC3CTR register is set to "1", and the communication complete interrupt SC3IRQ is generated to finish the transmission.
Chapter 12 Serial Interface 3 Reception of Acknowledgement (ACK) Bit after Data Transmission This LSI does not contain the function of receiving the acknowledgement (ACK) bit after data transmission. To receive ACK bit after transmitting data, select sc3acks= "0" (No ACK bit) before data transmisison. By transmitting the 8-bit data, an interrupt generates. Then switch the SBT pin function to "port" in the interrupt routine. With the port function, program a clock for ACK reception and read the ACK data.
Chapter 12 Serial Interface 3 Transfer Format On IIC bus, there are 2 transfer formats : the addressing format that transmits/receives data after 1 byte data (address data) that consists of slave address (7 bits) and R/W bit (1 bit) is transferred after start condition, and the free data format that transmits data after start condition. The serial interface of this LSI supports 2 communication formats for only master transmission and master reception at IIC communication.
Chapter 12 Serial Interface 3 Transmission/Reception Mode Setup and Operation The SC3REX flag of the SC3CTR register selects the status of the transmission or the reception. The first data is always added start condition for communication. The start condition is output from the master, this serial. If the communication is continued (no stop condition is generated), start condition should not be added from the next data.
Chapter 12 Serial Interface 3 Master Transmission Timing (1) 1 SDA (2) 8-bit transmission 2 .. 8 8-bit transmission (3) ACK 1 2 .. (4) 8 (5) (6) ACK SCL Interrupt IICBSY Set data to SC3TRB Set data to SC3TRB (1) Output start condition. (2) Bus released period, ACK bit is received. (3) Interrupt transaction. - Disable start condition : SC3STE = 1 →0 - Start communication : set data to SC3TRB (4) Receive ACK bit. (5) Interrupt transaction.
Chapter 12 Serial Interface 3 Master Reception Timing (1) SDA 8-bit transmission 1 2 .. (2) 8 (3) ACK 8-bit reception 1 2 (4) .. 8 (5) (6) ACK SCL Interrupt IICBSY Set data to SC3TRB Set data to SC3TRB Clear IICBSY flag [Set dummy data] (1) Output start condition. (2) Bus released period, ACK bit is received. (3) Interrupt transaction - Setup for the reception mode : SC3REX = 0 →1 - Disable start condition : SC3STE = 1 →0 - Start communication : set data to SC3TRB.
Chapter 12 Serial Interface 3 Pin Setup (2 channels, at transmission) Table 12-3-13 shows the pins setup at IIC serial interface transmission with 2 channels (SDA pin, SCL pin).
Chapter 12 Serial Interface 3 Pin Setup (2 channels, at reception) Table 12-3-14 shows the pins setup at IIC serial interface reception with 2 channels (SDA pin, SCL pin).
Chapter 12 Serial Interface 3 12-3-4 Setup Example Master Transmission Setup Example Here is the setup example for the transmission of the plural data to the all devices on IIC bus with IIC interface function of serial 3. Figure 12-3-15 shows the conditions.
Chapter 12 Setup Procedure Serial Interface 3 Description (5) Set ACK bit. SC3CTR (x'3FAA') bp0 : SC3ACKO = x bp1 : SC3ACKS = 1 (5) Set the SC3ACKS flag of the serial 3 control register (SC3CTR) to "1" to select "receive ACK bit". At transmission, ACK bit is received, so that the SC3ACKS flag does not need to set the ACK bit level. (6) Select the communication type. SC3CTR (x'3FAA') bp2 : SC3CMD = 1 (6) Set the SC3CMD flag of the serial 3 control register (SC3CTR) to "1" to select IIC.
Chapter 12 Serial Interface 3 Setup Procedure Description (13) Select the transfer clock. SC3MD1 (x'3FA9') bp2 : SC3MST = 1 (13) (14) Control the pin function. SC3MD1 (x'3FA9') bp4 : SC3SBOS = 1 bp5 : SC3SBIS = 1 bp6 : SC3SBTS = 1 bp7 : SC3IOM = 1 (14) Set the SC3SBOS, SC3SBIS, SC3SBTS flags of the SC3MD1 register to "1" to set the SDA pin (the SBO3 pin) to serial data output, the SBI3 pin to serial data input, and the SCL pin (the SBT3 pin)to serial clock I/O.
Chapter 12 Setup Procedure Serial Interface 3 Description (19) Judge the ACK bit level. SC3CTR (x'3FAA') bp0 : SC3ACKO (19) Confirm the level of the ACK bit, received by the SC3ACKS flag of the serial 3 control register (SC3CTR). When SC3ACKO = 0, the transmission is continued. When SC3ACKO = 1, the reception at slave may be impossible, finish the communication. (20) Select the transfer bit count.
Chapter 12 Serial Interface 3 It is possible to shut down the communication. When the communication should be stopped by force, set the SC3SBOS and the SC3SBIS of the SC3MD1 register to "0". Setup for each flag should be done in order. The activation of communication should be done after all control registers (except table 13-2-1 : SC3TRB) are set. The SC3CKS register should set the transfer clock so that the transfer rate is "under 400 kHz".
Chapter 13 Serial Interface 4 13
Chapter 13 Serial Interface 4 13-1 Overview This LSI contains a serial interface 4, which is compatible with IIC serial interface (slave) communication. 13-1-1 Functions Table 13-1-1 shows the functions of serial interface 4.
Figure 13-1-1 P54/SCL P02/SCL P53/SDA P01/SDA M U X M U X Start/stop detection circuit Bus busy detection circuit Communication mode selection circuit Addressing circuit Address compare circuit Transmission/reception Shift register ck Reception Buffer SC4RXB Read 10 / Match { { { { Overview WRS I2CINT STRT RSTRT I2CBSY SLVBSY ACKVALID - SC4STR SELI2C - - I2CPSEL I2CGEM I2CADM I2CAD9 I2CAD8 SC4AD1 I2CAD7 I2CAD6 I2CAD5 I2CAD4 I2CAD3 I2CAD2 I2CAD1 I2CAD0 SC4AD0
Chapter 13 Serial Interface 4 13-2 Control Registers 13-2-1 Registers Table 13-2-1 shows the registers to control serial interface 4.
Chapter 13 13-2-2 Serial Interface 4 Data Register Serial interface 4 has a 8-bit buffer registers for transmission/reception.
Chapter 13 Serial Interface 4 13-2-3 Mode Registers Serial interface 4 Addressing Register 0 (SC4AD0) 7 SC4AD0 6 5 4 3 2 1 0 I2CAD7 I2CAD6 I2CAD5 I2CAD4 I2CAD3 I2CAD2 I2CAD1 I2CAD0 Figure 13-2-3 ( At reset: 0 0 0 0 0 0 0 0 ) Serial interface 4 Addressing Register 0 (SC4AD0 : x'03FA3', R/W) Serial interface 4 Addressing Register 1 (SC4AD1) 7 SC4AD1 6 5 4 3 2 1 0 SELI2C RESERVED RESERVED I2CPSEL I2CGEM I2CADM I2CAD9 I2CAD8 ( At reset: 0 0 0 0 0 0 0 0 ) I2CADM 0 7 bits address mode
Chapter 13 Serial Interface 4 Serial interface 4 Status Register (SC4STR) SC4STR 7 6 WRS I2CINT 5 4 3 2 1 STRT RSTRT I2CBSY SLVBSY ACKVALID 0 - ( At reset: X X X X X X X X) ACKVALID 0 Undetected 1 Detected SLVBSY Other than during data transfer 1 During data transfer Bus busy flag 0 Bus free status 1 Bus busy status RSTRT Re-start condition detection 0 Undetected 1 Detected STRT Start condition detection 0 Undetected 1 Detected I2CINT Figure 13-2-5 Slave busy flag
Chapter 13 Serial Interface 4 Serial interface 4 Port Control Register 0 (SC4ODC0) SC4ODC0 7 6 5 4 3 2 - - - - - - 1 0 SC4ODC01 SC4ODC00 (At reset: - - - - - - 0 0 ) SC4ODC00 0 Push-pull 1 N-ch open-drain SC4ODC01 Figure 13-2-6 P01 N-ch open drain control P02 N-ch open drain control 0 Push-pull 1 N-ch open-drain Serial interface 4 Port Control Register 0 (SC4ODC0 : x'03F3F', R/W) Serial interface 4 Port Control Register 1 (SC4ODC1) SC4ODC1 7 6 5 4 3 2 - - - - -
Chapter 13 13-3 Serial Interface 4 Operation Activation and Termination Factors Set the SELI2C flag of the SC4AD1 register to "1" to activate this serial interface. For the termination, set the flag to "0". The ports used for communication can be used as general-purpose port while the serial interface is not in operative state. When the SELI2C register is set to "0", SC4AD0 register, SC4TXB register and SC4RXB register is automatically cleared.
Chapter 13 Serial Interface 4 Busy Flag This serial interface contains 2 busy flags (SLVBSY, I2CBSY). The SLVBSY flag is set to "1" when address transmitted from master matches with the slave address. The I2CBSY flag is set to "1" during communication on IIC bus. In 10 bits addresss mode, if the upper 2 bits address which is first to be transmitted from master matches with the I2CAD9-8 of the SC4AD1 register, the SLVBSY flag is set to "1" and SC4IRQ is not generated.
Chapter 13 13-3-1 Serial Interface 4 Setup Example of the Slave IIC Serial Interface Setup Example of the Data Transmission This section describes the setup example of slave transmission using serial interface 4. Table 13-3-2 shows the conditions for transmission routine. Table 13-3-2 Item Pin Setup Setup Data pin (SDA) P01 Clock pin (SCL) P02 Addressing mode 7 bits Slave address 110011 Transmission data x'55' An example setup procedure, with a description of each step is shown below.
Chapter 13 Serial Interface 4 Setup Procedure Description (5) Set the slave address. SC4AD0 (x'3FA3') bp7-1 : I2CAD7-1 = 0110011 (5) Set the slave address to the upper 7 bits of the SC4AD0 register (I2CAD7-1). (6) IIC communication start (6) Master on the IIC bus starts communication.
Chapter 14 Automatic Transfer Controller 14
Chapter 14 Automatic Transfer Controller 14-1 Overview 14-1-1 ATC1 This LSI contains an automatic transfer controller (ATC) that uses direct memory access (DMA) to transfer the contents of the whole memory space (256 KB) using the hardware. This ATC block is called ATC1. ATC1 is activated by an interrupt or a flag set by the software.
Chapter 14 14-1-2 Automatic Transfer Controller Functions Table 14-1-1 and 14-1-2 provide a list of the ATC1 trigger factors and transfer modes.
XIV - 4 Overview Figure 14-1-1 Software Start TM7 Capture Trigger TM7IRQ TM1IRQ ADIRQ SC4IRQ SC0TIRQ SC1TIRQ SC3IRQ IRQ3 IRQ2 IRQ1 IRQ0 4 AT1CNT1 0 AT1IR0 AT1IR1 AT1IR2 AT1IR3 BTSTP 7 7 0 4 IRQ0IR (IRQ0IR Interrupt Request Flag) AT1CNT0 AT1EN Reserved AT1MD0 AT1MD1 AT1MD2 AT1MD3 AT1ACT FMODE Synchronization DMA Start Request BGRNT (Bus Release Confirmation Signal) Internal Address Bus DEC Calculator AT1TRC AT1MAP1 (M) AT1MAP1 (H) AT1MAP1 (L) AT1MAP0 (L) Internal Data Bus ATC1
Chapter 14 14-2 Control Registers 14-2-1 Registers Automatic Transfer Controller Table 14-2-1 shows the registers used to control ATC1.
Chapter 14 Automatic Transfer Controller ATC1 Control Register 0 (AT1CNT0) 7 AT1CNT0 6 5 4 3 2 1 0 (At reset : 0 0 x x x x 0 0 ) FMODE AT1ACT AT1MD3 AT1MD2 AT1MD1 AT1MD0 Reserved AT1EN AT1EN 0 1 Reserved ATC1 transfer enable flag ATC1 transfer disabled ATC1 transfer enabled (ATC 1 start for burst transfers) Set always "0".
Chapter 14 Automatic Transfer Controller ATC1 Control Register 1 (AT1CNT1) AT1CNT1 7 6 5 - - - 4 3 2 BTSTP AT1IR3 1 0 (At reset : - - - x x x x x ) AT1IR2 AT1IR1 AT1IR0 ATC1 trigger AT1IR3 AT1IR2 AT1IR1 AT1IR0 factor settings 0 External interrupt 0 0 1 External interrupt 1 0 0 Serial interface 0 interrupt 1 1 Serial interface 1 interrupt 0 0 Timer 7 interrupt 0 1 Timer 7 capture trigger 1 0 A/D interrupt 1 1 Software initialization 0 External interrupt 2 0 1 External interrupt 3 0 0 (Disab
Chapter 14 Automatic Transfer Controller ATC1 Memory Pointer 0 (AT1MAP0) AT1MAP0L 7 6 5 4 3 2 bp7 bp6 bp5 bp4 bp3 bp2 Figure 14-2-4 AT1MAP0M 1 bp1 0 bp0 ATC1 Memory Pointer 0 : Lower 8 bits (AT1MAP0L : x'03FD3', R/W) 7 6 5 4 3 2 1 0 bp15 bp14 bp13 bp12 bp11 bp10 bp9 bp8 Figure 14-2-5 AT1MAP0H (At reset : x x x x x x x x ) (At reset : x x x x x x x x ) ATC1 Memory Pointer 0 : Middle 8 bits (AT1MAP0M : x'03FD4', R/W) 7 6 5 4 3 2 1 0 - - - - - - bp17 bp
Chapter 14 14-3 Operation 14-3-1 Basic Operations and Timing Automatic Transfer Controller ATC1 is a DMA block that enables the hardware to transfer the whole memory space (256 KB). This section provides a description of and timing for the basic ATC1 operations.
Chapter 14 Automatic Transfer Controller Data transfer The basic ATC1 operation cycle is the "byte-data transfer cycle", in which ATC1 transfers a single byte of data. This operation consists of two instruction cycles, a load and a store cycle. In the load cycle, ATC1 reads the data from the source address of the source memory, and in the store cycle, ATC1 stores the read data to the destination address of the destination memory.
Chapter 14 14-3-2 Automatic Transfer Controller Setting the Memory Address Setting the transfer addresses to the memory pointers The address of the memory space for an automatically data transfer of ATC1 should be set in the both of memory pointer 0 (AT1MAP0) and memory pointer 1 (AT1MAP1). In each transfer mode, one of those pointer is the source address, and another is the destination address.
Chapter 14 Automatic Transfer Controller 14-3-3 Setting the Data Transfer Count Transfer data counter (AT1TRC) function You can preset the data transfer count is preset for ATC1. Set the value in the ATC1 transfer counter (AT1TRC). The counter decrements by one each time ATC1 transfers one byte of data. The value in the transfer data counter is indeterminate upon reset. The program must initialize the counter before activating ATC1.
Chapter 14 14-3-4 Automatic Transfer Controller Setting the Data Transfer Modes Data transfer modes There are two types of ATC1 transfers, standard and burst, and sixteen transfer modes. Set the transfer mode in ATC1 control register 0 (AT1CNT0). [ Table 14-1-2 Transfer Modes ] Standard and burst transfers The ATC1 transfer modes are divided into standard transfer modes and burst transfer modes. There are fourteen standard modes, 0 to D, and two burst modes, E and F.
Chapter 14 Automatic Transfer Controller 14-3-5 Transfer Mode 0 In transfer mode 0, ATC1 automatically transfers one byte of data from any memory space to the I/O space (special registers : x'03F00' - x'03FFF') every time an ATC1 activation request occurs.
Chapter 14 14-3-6 Automatic Transfer Controller Transfer Mode 1 In transfer mode 1, ATC1 automatically transfers one byte of data from the I/O space (special registers : x'03F00' - x'03FFF') to any memory space every time an ATC1 activation request occurs.
Chapter 14 Automatic Transfer Controller 14-3-7 Transfer Mode 2 In transfer mode 2, ATC1 automatically transfers one byte of data from any memory space to the I/O space (special registers : x'03F00' - x'03FFF') every time an ATC1 activation request occurs.
Chapter 14 14-3-8 Automatic Transfer Controller Transfer Mode 3 In transfer mode 3, ATC1 automatically transfers one byte of data from the I/O space (special registers : x'03F00' - x'03FFF') to any memory space every time an ATC1 activation request occurs.
Chapter 14 Automatic Transfer Controller 14-3-9 Transfer Mode 4 In transfer mode 4, ATC1 automatically transfers two bytes (one word) of data from any memory space to the I/O space (special registers : x'03F00' - x'03FFF') every time an ATC1 activation request occurs.
Chapter 14 Automatic Transfer Controller 14-3-10 Transfer Mode 5 In transfer mode 5, ATC1 automatically transfers two bytes (one word) of data from the I/O space (special registers : x'03F00' - x'03FFF') to any memory space every time an ATC1 activation request occurs.
Chapter 14 Automatic Transfer Controller 14-3-11 Transfer Mode 6 In transfer mode 6, ATC1 automatically transfers one byte of data two times every time an ATC1 activation request occurs. 00000 - 3FFFF (2) (4) AT1MAP0 AT1MAP0 + 1 03F00 - 03FFF (1) AT1MAP1 (3) (Only lower 8 bits are valid) AT1MAP0 + 2 AT1MAP0 + 3 Figure 14-3-8 Transfer Mode 6 In this mode the transfer direction indicated by memory pointers 0 and 1 reverses for the second data byte transfer.
Chapter 14 Automatic Transfer Controller To execute a continuous serial transaction, you must pre-store the serial transmission data in the memory space that memory pointer 0 points, the transmission data must fill every other address in the space. Once the serial transaction ends, the received data is stored empty (skipped) addresses and the transmission and reception data at stored in an alternating pattern. In transfer mode 6, ATC1 executes a data byte transfer twice each time it is activated.
Chapter 14 Automatic Transfer Controller 14-3-12 Transfer Mode 7 In transfer mode 7, ATC1 automatically transfers one byte of data two times every time an ATC1 activation request occurs. Memory Pointer 0 00000 - 3FFFF (2) AT1MAP0 AT1MAP0 + 1 Memory Pointer 1 03F00 - 03FFF (1) AT1MAP1 (3) (Only lower 8 bits are valid) AT1MAP0 + 2 AT1MAP0 + 3 Figure 14-3-9 Transfer Mode 7 In this mode the transfer direction indicated by memory pointers 0 and 1 reverses for the second data byte transfer.
Chapter 14 Automatic Transfer Controller To execute a continuous serial transaction, you must pre-store the serial transmission data in the memory space that memory pointer 0 points, once the serial communication ends, the MCU has written to the reception data over the transmission data, so that only reception data remains in the memory. In transfer mode 7, ATC1 executes a data byte transfer twice each time it is activated.
Chapter 14 Automatic Transfer Controller 14-3-13 Transfer Mode 8 In transfer mode 8, ATC1 automatically transfers one byte of data two times every time an ATC1 activation request occurs.
Chapter 14 Automatic Transfer Controller Transfer mode 8 can be used to support continuous transmission/ reception for serial interface 0 and 1. Set the memory pointer 1 to point to the serial reception buffer (RXBUF0, RXBUF1) and select serial interrupts as the ATC1 trigger factor.
Chapter 14 Automatic Transfer Controller 14-3-14 Transfer Mode 9 In transfer mode 9, ATC1 automatically transfers one byte of data two times every time an ATC1 activation request occurs.
Chapter 14 Automatic Transfer Controller Transfer mode 9 can be used to support continuous transmission/ reception for serial interface 0 and 1. Set the memory pointer 1 to point to the serial reception buffer (RXBUF0, RXBUF1) and select serial interrupts as the ATC1 trigger factor.
Chapter 14 Automatic Transfer Controller 14-3-15 Transfer mode A In transfer mode A, ATC1 automatically transfers one byte of data from any memory space to any other memory space every time an ATC1 activation request occurs.
Chapter 14 Automatic Transfer Controller 14-3-16 Transfer Mode B In transfer mode B, ATC1 automatically transfers one byte of data from any memory space to any other memory space every time an ATC1 activation request occurs.
Chapter 14 Automatic Transfer Controller 14-3-17 Transfer Mode C In transfer mode C, ATC1 automatically transfers one byte of data from any memory space to any other memory space every time an ATC1 activation request occurs.
Chapter 14 Automatic Transfer Controller 14-3-18 Transfer Mode D In transfer mode D, ATC1 automatically transfers one byte of data from any memory space to any other memory space every time an ATC1 activation request occurs.
Chapter 14 Automatic Transfer Controller 14-3-19 Transfer Mode E Transfer mode E is a burst mode. In this mode, when ATC1 is activated, it automatically transfers the number of data bytes set in the transfer data counter (AT1TRC) in one continuous operation.
Chapter 14 Automatic Transfer Controller 14-3-20 Transfer Mode F Transfer mode F is a burst mode. In this mode, when ATC1 is activated, it automatically transfers the number of data bytes set in the transfer data counter (AT1TRC) in one continuous operation.
Chapter 14 Automatic Transfer Controller 14-4 Setup Example An example setup procedure, with a description of each step is as follows ; Setup Procedure Description (1) Set the data transfer mode. AT1CNT0 (x'3FD0') bp7 :FMODE bp6 :AT1ACT =0 bp5-2 :AT1MD3-0 bp0 :AT1EN =0 (1) Select the data transfer mode with the AT1MD flag in the AT1CNT0 register. No matter which mode you select, setting the FMODE flag disables the incrementing function in memory pointer 0. Normally set this flag to 0.
Chapter 14 Automatic Transfer Controller To activate ATC1 in the software, first complete steps (1) to (6), then set the AT1ACT flag in the AT1CNT0 register. After the AT1ACT flag is set, ATC1 is started and data transfer is started. The hardware automatically clears AT1ACT flag when ATC1 is activated. On the standard transfer mode, set a program that sets flags as much as the data transfer needs.
Chapter 15 A/D Converter 15
Chapter 15 A/D Converter 15-1 Overview This LSI has an A/D converter with 10 bits resolution. That has a built-in sample hold circuit, and software can switch channel 0 to 6 (AN0 to AN6) to analog input. As A/D converter is stopped, the power consumption can be reduced by a built-in ladder resistance. A/D converter is activated by 2 factors : a register setup or an external interrupt. 15-1-1 Functions Table 15-1-1 shows the A/D converter functions.
Chapter 15 15-1-2 ANCTR1 ANCHS0 ANCHS1 ANCHS2 - A/D Converter Block Diagram ANCTR0 0 ANLADE ANCK0 ANCK1 ANSH0 ANSH1 7 ANCTR2 0 ANSTSEL ANST 7 IRQ3(P23) 0 External interrupt control 7 ANBUF1 ANBUF10 ANBUF11 ANBUF12 ANBUF13 ANBUF14 ANBUF15 ANBUF16 ANBUF17 A/D conversion control 0 7 ANBUF0 ANBUF06 ANBUF07 0 7 3 VREF + AN0 AN1 AN2 AN3 AN4 AN5 AN6 2 MUX 2 Sample and hold A/D conversion data upper 8 bits 10 bits A/D comparator A/D conversion data lower 2 bits VREF fs/2 fs/4 MUX fs/8
Chapter 15 A/D Converter 15-2 Control Registers A/D converter consists of the control register (ANCTRn) and the data storage buffer (ANBUFn). 15-2-1 Registers Table 15-2-1 shows the registers used to control A/D converter.
Chapter 15 15-2-2 A/D Converter Control Registers A/D Converter Control Register 0 (ANCTR0) 7 ANCTR0 6 5 4 3 ANSH1 ANSH0 ANCK1 ANCK0 ANLADE 2 1 0 - - - (At reset : 0 0 0 0 - - - ) ANLADE ANCK1 0 1 A/D ladder resistance control 0 A/D ladder resistance OFF 1 A/D ladder resistance ON ANCK0 A/D conversion clock (ftad=1/TAD) 0 fs/2 1 fs/4 0 fs/8 1 fx × 2 * as 800 ns < TAD ANSH1 0 1 ANSH0 ≤ 15.
Chapter 15 A/D Converter A/D Converter Control Register 1 (ANCTR1) ANCTR1 7 6 5 4 - - - - 3 2 1 0 RESERVED ANCHS2 ANCHS1 ANCHS0 (At reset : - - - - 0 0 0 0) ANCHS2 ANCHS1 ANCHS0 Analog Input Channel 0 0 1 0 1 1 RESERVED 0 AN0 (PA0) 1 AN1 (PA1) 0 AN2 (PA2) 1 AN3 (PA3) 0 AN4 (PA4) 1 AN5 (PA5) 0 AN6 (PA6) 1 Reserved Set always "0".
Chapter 15 15-2-3 A/D Converter Data Buffers A/D Conversion Data Storage Buffer 0 (ANBUF0) The lower 2 bits from the result of A/D conversion are stored to this register. 7 ANBUF0 6 5 4 3 2 1 0 (At reset : X X - - - - - -) ANBUF07 ANBUF06 Figure 15-2-4 A/D Conversion Data Buffer 0 (ANBUF0 : x'03FB3', R) A/D Conversion Data Storage Buffer 1 (ANBUF1) The upper 8 bits from the result of A/D conversion are stored to this register.
Chapter 15 A/D Converter 15-3 Operation Here is a description of A/D converter circuit setup procedure. (1) (2) (3) (4) (5) (6) (7) (8) XV - 8 Set the analog pins. Set the analog input pin, set in (2), to "special function pin" by the port A input mode register (PAIMD). * Setup for the port A input mode register should be done before analog voltage is put to pins. Select the analog input pin.
Chapter 15 A/D Converter TAD 1-2 3 4 12 A/D conversion clock ANST flag A/D conversion start A/D conversion complete A/D conversion TS Sampling Hold bit 8 comparison bit 9 comparison Determine Determine bit 9 bit 8 bit 0 comparison Determine Determine bit 0 bit 1 A/D interrupt (ADIRQ) Figure 15-3-1 Operation of A/D Conversion To read the value of the A/D conversion, A/D conversion should be done several times to prevent noise error by confirming the match of level by program, or by using the
Chapter 15 A/D Converter 15-3-1 Setup Input Pins of A/D Converter Setup Input pins for A/D converter is selected by the ANCH2 to 0 flag of the ANCTR1 register. Table 15-3-1 Input Pins of A/D Converter Setup ANCHS2 ANCHS1 ANCHS0 A/D pin 0 AN0 pin 1 AN1 pin 0 AN2 pin 1 AN3 pin 0 AN4 pin 1 AN5 pin 0 AN6 pin 1 Reserved 0 0 1 0 1 1 Clock of A/D Converter Setup The A/D converter clock is set by the ANCK1 to 0 flag of the ANCTR0 register.
Chapter 15 A/D Converter Built-in Ladder Resistor Control The ANLADE flag of the ANCTR0 register is set to "1" to send a current to the ladder resistance for A/ D conversion. As A/D converter is stopped, the ANLADE flag of the ANCTR0 register is set to "0" to save the power consumption.
Chapter 15 A/D Converter 15-3-2 Setup Example A/D Converter Setup Example by Registers A/D conversion is started by setting registers. The analog input pins are set to AN0, the converter clock is set to fs/4, and the sampling hold time is set to TAD x 6. Then, A/D conversion complete interrupt is generated. An example setup procedure, with a description of each step is shown below. Description Setup Procedure (1) Set the analog input pin.
Chapter 15 Setup Procedure A/D Converter Description (7) Set the A/D ladder resistance. ANCTR0 (x'3FB0') bp3 : ANLADE = 1 (7) Set the ANLADE flag of the A/D converter control register 0 (ANCTR0) to "1" to send a current to the ladder resistance for the A/D conversion. (8) Start the A/D conversion.
Chapter 15 A/D Converter A/D Conversion Setup Example by External Interrupt 3 The A/D conversion is started by the external interrupt 3. The analog input pin is set to AN0, the converter clock is set to fs/4, and the sample hold time is set to TAD x 6. Then, the A/D conversion complete interrupt is generated. An example setup procedure, with a description of each step is shown below. Setup Procedure Description (1) Set the analog input pin.
Chapter 15 Setup Procedure A/D Converter Description (7) Enable the interrupt. ADICR (x'3FFA') bp1 : ADIE = 1 (7) Enable the interrupt by setting the ADIE flag of the ADICR register to "1". (8) Set the A/D ladder resistance. ANCTR0 (x'3FB0') bp3 : ANLADE = 1 (8) Set the ANLADE flag of the A/D converter control register 0 (ANCTR0) to "1" to send a current to the ladder resistance for the A/D conversion. (9) Select the A/D converter activation factor.
Chapter 15 A/D Converter 15-3-3 Cautions A/D conversion can be damaged by noise easily, therefore, anti-noise measures should be taken adequately . Anti-noise measures To A/D input (analog input pin), add condenser near the VSS pins of micro controller. VDD VSS VREF+ AN0 to AN6 VREF- Digital VDD Analog VDD Power supply Digital VSS Analog VSS Set near the VSS pin Figure 15-3-2 A/D Converter Recommended Example 1 VDD VDD VSS VREF+ AN0 to AN6 VREF- VSS Power supply Set near the VSS pin.
Chapter 15 A/D Converter To maintain high precision of A/D conversion, following instructions on use of A/D converter should be strictly kept. 1. 2. 3. Input impedance R of A/D input pin should be under 500 kΩ*1. And connect the external capacitor C (over 1000 pF, under 1 µF)*1 between Vss and the A/D input pin. Set the A/D conversion frequency depending on the time constant of R and C.
Chapter 16 D/A Converter 16 18
Chapter 16 D/A Converter 16-1 Overview This LSI has a built-in D/A converter with 8 bits solution. There are 2 output channels and 8-bit data registers for each channel. When the D/A converter is not used, the built-in ladder resistance can be set to OFF to save the power consumption. 16-1-1 Functions Table 16-1-1 shows the D/A converter functions.
Chapter 16 16-2 D/A Converter Operation The D/A converter circuit setup procedure is as follows: (1) (2) (3) (4) Set the analog pins. Set the analog input pin, set in (2), to "special function pin" by the port A input mode register (PAIMD). * Setup for the port A input mode register should be done before analog voltage is put to pins. Select the analog output pin. Select the analog output pin from DA1 to DA0 (PA1 to PA0) by the DACH1 to DACH0 flag of the D/A converter control register (DACTR).
Chapter 16 D/A Converter 16-3 Control Registers 16-3-1 Overview Table 16-3-1 shows the registers to control the D/A converter in MN101C77C.
Chapter 16 16-3-2 D/A Converter Control Register (DACTR) This is the 8-bit readable/writable register that controls the D/A conversion.
Chapter 16 D/A Converter 16-3-3 Input Data Registers These readable/writable registers store the A/D converter data. D/A Converter Input Data Register 01 (DADR01) This register stores the D/A conversion data (for DA01 channel).
Chapter 16 16-4 D/A Converter Setup Example Channel fixed D/A Converter Setup Example Conversion channel should be set to DA0. An example setup procedure, with a description of each step is shown below. Setup Procedure Description Set the port A pin. PAIMD (x'3F3C') bp0 : PAIMD0 = 1 PADIR (x'3F3A') bp0 : PADIR0 = 0 PAPLUD (x'3F4A') bp0 : PAPLUD0 = 0 (1) (2) Set the D/A conversion pin.
Chapter 17 Appendices 17
Chapter 17 Appendices 17-1 Probe Switches 17-1-1 PRB-MBB101C77-M - This probe must be used with the following boards. - Connector board: PX-CN101-M MBB board: PRB-MBB101C77-M Adapter board: PRB-ADP101-64-M Dummy target: PRB-DMY101C77-M The dummy target should be connected when ICE is operated independently, the adapter board should be connected at connection to the target. The power supply voltage of ICE is between 3.0 V to 3.6 V. - This probe is mounted the switches for mask option.
Chapter 17 Appendices 17-1-2 PX-CN101-M This board can be used for any MBB models (product No. PRB-MBB101∗∗∗-M) of MN101 series. (Please visit our website for the latest information on the product.) Figure1: PX-CN101-M Layout < How to connect > Connector board (PX-CN101-M) Make sure that the points marked are put together.
Chapter 17 Appendices 17-1-3 PRB-ADP101-64-M When connected to the target, use this board with MBB board. This board can be used with the following boards. (The product type is subject to change without prior notice. The latest information should be confirmed on our web site.) - PRB-MBB101C52-M - PRB-MBB101C58-M Improper matching may cause any damage to the ICE.
Chapter 17 Appendices 17-1-4 PRB-DMY101C77-M Dummy target boards differ depending upon the models. This board can be used for only 101C77 64PIN. When unconnected to the target, use this board with the PRB-MBB101C77-M. Improper matching may cause any damage to the ICE. Figure1: PRB-DMY101C77-M Layout < How to connect > Connector board: PX-CN101-M MBB board: PRB-MBB101C77-M Make sure that the points marked are put together.
Chapter 17 Appendices 17-2 Address X'3F00' Special Function Registers List Bit Symbol / Initial Value / Description Register Bit 7 Bit 6 Bit 5 Bit 4 SOSCDBL OSCSEL1 OSCSEL0 OSCDBL CPUM Clock Switching IOW1 X'3F01' MEMCTR X'3F02' IOW0 I/O Wait Setup - WDCTR AREACTR X'3F05' CSMD01 CS7EXT Page Bit 2 Bit 1 Bit 0 OSC1 OSC0 STOP HALT STOP mode HALT Mode Setup Setup IVBM EXMEM EXWH IRWE Switch Switch SoftwareWrites Address Memory Wait Setup WDTC2 WDTC1 WDTC0 WDTS1
Chapter 17 Address Register X'3F1A' PAOUT X'3F1D' P8LED X'3F1E' P6SYO X'3F20' P0IN X'3F21' P1IN X'3F22' P2IN X'3F25' P5IN X'3F26' P6IN X'3F27' P7IN X'3F28' P8IN X'3F2A' PAIN X'3F2B' KEYCNT X'3F2D' OSCMD Bit 6 Bit 5 - PAOUT6 PAOUT5 P8LED6 P8LED5 P6SYO6 P6SYO5 P6SYO1 P6SYO2 P6SYO3 P6SYO0 IV - 28 P0IN6 P0IN5 P0IN4 P0IN1 P0IN2 P0IN3 P0IN0 IV - 7 - - P1IN4 P1IN1 P1IN2 P1IN3 P1IN0 IV - 13 - - P2IN4 P2IN1 P2IN2 P2IN3 P2IN0 IV - 18 - - P5IN4 P5IN1 P
Chapter 17 Appendices Address Register X'3F36' P6DIR X'3F37' P7DIR X'3F38' P8DIR X'3F3A' PADIR X'3F3C' PAIMD X'3F3E' P6IMD X'3F40' P0PLU X'3F41' P1PLU X'3F42' P2PLU X'3F45' P5PLU X'3F46' P6PLU X'3F47' P7PLUD X'3F48' P8PLU X'3F4A' PAPLUD X'3F4D' DLYCTR Bit Symbol /Initial Value /Description Bit 7 Bit 6 Bit 5 P6DIR7 P6DIR6 P6DIR5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIR0 Port 6 I/O Direction Control P7DIR7 P7DIR6 P7DIR5 P7DIR4 P8DIR6
Chapter 17 Address Register X'3F53' TM1OC X'3F54' TM0MD Bit 7 Bit 6 Bit 5 TM1OC7 TM1OC6 TM1OC5 - TM0MOD Bit 2 Bit 1 Bit 0 TM1OC4 TM1OC3 TM1OC2 TM1OC1 TM1OC0 TM0PWM Timer 0 Pulse Width Measurement - - - TM1MD - X'3F56' Bit 3 Timer 1 Output Compare Register - X'3F55' Bit 4 - TM0EN TM0CK2 TM0CK1 TM0CK0 Timer 0 Clock Source Selection VI - 10 Control TM1CAS TM1EN Cascade Timer 1 Count Selection Control - - - Page VI - 8 PWM Operation Timer 0 Count Selection A
Chapter 17 Appendices Bit Symbol /Initial Value /Description Address Register X'3F70' TM7BCL X'3F71' TM7BCH X'3F72' TM7OC1L X'3F73' TM7OC1H X'3F74' TM7PR1L X'3F75' TM7PR1H X'3F76' TM7ICL X'3F77' TM7ICH X'3F78' TM7MD1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 7 TM7BCL7 TM7BCL6 TM7BCL5 TM7BCL4 TM7BCL3 TM7BCL2 TM7BCL1 TM7BCL0 VII - 7 Timer 7 Binary Counter Lower 8 Bits TM7BCH7 TM7BCH6 TM7BCH5 TM7BCH4 TM7BCH3 TM7BCH2 TM7BCH1 TM7BCH0 VII - 7 Timer 7 Binary Counte
Chapter 17 Address Register X'3F91' TXBUF0 X'3F92' SC0MD0 Bit Symbol /Initial Value /Description Bit 7 Bit 6 Bit 5 TXBUF07 TXBUF06 TXBUF05 X'3F94' SC0MD2 SC0REN SC0TRN Transmission/ Reception data Transmission data Reception Data Edge Selection Polarity Change Polarity Change SC0IOM SC0MD1 Bit 3 Bit 2 Bit 1 Bit 0 TXBUF04 TXBUF03 TXBUF02 TXBUF01 TXBUF00 SC0SBTS SC0SBIS SC0DIR SC0STE Specify First Bit to be Transfered Start Condition Synchronous Serial Transfer Bit Count Sel
Chapter 17 Appendices Address Register X'3FAE' SC3ODC Bit Symbol /Initial Value /Description Bit 7 - Bit 6 Reserved Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 SC3ODC1 P52 Output Type Selection SC3PSC1 Set Always to "0" - X'3FAF' - - - - SC3PSC2 SC3CKS Bit 0 SC3ODC0 P51 Output Type Selection SC3PSC0 Serial 3 Transfer Clock Selection (Prescaler Output) ANSH1 X'3FB0' ANCTR0 ANCK1 ANCK0 A/D Conversion Clock Timer Setup Selection X'3FB1' ANSH0 A/D Sample Hold - - - ANCTR1 ANLADE A/
Chapter 17 Address Register X'3FD1' ATCNT1 Bit Symbol /Initial Value /Description Bit 7 Bit 6 Bit 5 - - - Bit 4 Bit 3 BTSTP AT1IR3 Burst Transfer Bit 2 Bit 1 Bit 0 AT1IR2 AT1IR1 AT1IR0 Appendices Page XIV - 7 ATC1 Activation Factor Selection Enable flag AT1TRC7 X'3FD2' AT1TRC X'3FD3' AT1MAP0L X'3FD4' AT1MAP0M X'3FD5' AT1MAP0H AT1TRC6 AT1TRC5 AT1TRC4 AT1TRC3 AT1TRC2 AT1TRC1 AT1TRC0 XIV - 7 ATC1 Transfer Count Setting AT1MAP0L7 AT1MAP0L6 AT1MAP0L5 AT1MAP0L4 AT1MAP0L3 A
Chapter 17 Appendices Address X'3FF0' Register Bit Symbol /Initial Value /Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TBLV1 TBLV0 - - - - TBIE TBIR Specify TB Enable TB Request TB Interrupt Level Interrupt Interrupt TM7IE TM7IR TBICR TM7LV1 X'3FF1' TM7LV0 - - - - Enable TM7 Request TM7 Specify TM7 TM7ICR Interrupt Interrupt Level T7OC2LV1 X'3FF2' T7OC2ICR T7OC2IE T7OC2IR Enable T7OC2 Request T7OC2 Interrupt Level Interrupt Interrupt SC0RICR S
Chapter 17 Address Bit Symbol / Initial Value / Description Register X'3FA3' SC4AD0 X'3FA4' SC4AD1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2CAD7 I2CAD6 I2CAD5 I2CAD4 I2CAD3 I2CAD2 I2CAD1 I2CAD0 Reserved Reserved Enable I2CTXB7 SC4TXB X'3FAD' SC4RXB X'3FAC' SC4STR SC4ODC0 X'3F3D' SC4ODC1 X'3FF3' SC4ICR I2CTXB6 I2CTXB5 I2CPSEL I2CGEM Serial Interface Communication Mode Pin Selection Selection I2CTXB4 I2CTXB3 I2CADM Address Selection I2CTXB2 I2CAD9 I2CAD8 Addressin
Chapter 17 Appendices 17-3 Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag Code Cycle Repeat Ext. VF NF CF ZF Size Machine Code 1 2 3 4 5 6 .... ...
Chapter 17 Appendices MN101C SERIES INSTRUCTION SET Group PUSH POP EXT Mnemonic Operation Flag CodeCycle Re- extenpeat VF NF CF ZF Size sion 1 Machine Code 2 4 5 6 1101 111a <#16 .... .... ...
Chapter 17 Appendices MN101C SERIES INSTRUCTION SET Group Mnemonic NOT NOT Dn ASR ASR Dn Operation _ Flag CodeCycle Re- Exten peat sion VF NF CF ZF Size Machine Code 1 2 3 4 3 2 0010 0010 10Dn 0 -- 3 2 0010 0011 10Dn 0 0 3 2 0010 0011 11Dn 3 2 0010 0010 11Dn 0 5 5 0011 1000 0bp. 0 0 7 6 0011 1100 0bp.
Chapter 17 Appendices MN101C SERIES INSTRUCTION SET Group Bcc Mnemonic BGT label Operation Flag CodeCycle Re- Extenpeat sion VF NF CF ZF Size if((VF^NF)|ZF=0),PC+6+d11(label)+H→PC -- -- -- -- Machine Code 1 2 3 4 5 .... ...H 6 3/4 0010 0011 0001
Chapter 17 Appendices MN101C SERIES INSTRUCTION SET Group TBZ Mnemonic TBZ (io8)bp,label Flag CodeCycle Re- Extenpeat sion VF NF CF ZF Size Operation if(mem8(IOTOP+io8)bp=0),PC+7+d7(label)+H→PC 0 Machine Code 1 2 3 4 5 6 0 7 6/7 0011 0100 0bp.
Chapter 17 Appendices MN101C SERIES INSTRUCTION SET Group RTS Mnemonic RTS Flag CodeCycle Re- Extenpeat VF NF CF ZF Size sion 1 Operation mem8(SP)→(PC).bp7-0 Machine Code 2 --- --- --- --- 2 7 0000 0001 2 11 0000 0011 --- --- --- --- 3 2 0010 0001 1rep 3 4 5 6 7 Notes 8 9 10 11 mem8(SP+1)→(PC).bp15-8 mem8(SP+2).bp7→(PC).H mem8(SP+2).bp1-0→(PC).bp17-16 SP+3→SP RTI RTI mem8(SP)→PSW mem8(SP+1)→(PC).bp7-0 mem8(SP+2)→(PC).bp15-8 mem8(SP+3).bp7→(PC).H mem8(SP+3).bp1-0→(PC).
Chapter 17 Appendices 17-4 Instruction Map MN101C SERIES INSTRUCTION MAP 1st nibble\2nd nibble 0 1 RTS 2 3 4 5 6 7 8 9 A B C D E F 0 NOP 1 JSR d12(label) JSR d16(label) MOV #8,(abs8)/(abs12) PUSH An 2 When the exension code is b'oo10' 3 When the extension code is b'0011' 4 MOV (abs12),Dm MOV (abs8),Dm MOV (An),Dm 5 MOV Dn,(abs12) MOV Dn,(abs8) MOV Dn,(Am) 6 MOV (io8),Dm MOV (d4,SP),Dm MOV (d8,An),Dm 7 MOV Dn,(io8) MOV Dn,(d4,SP) MOV Dn,(d8,Am) 8 ADD #4,Dm SUB Dn,
Chapter 17 Appendices Extension code: b'0011' 2nd nibble\ 3rd nibble 0 1 2 3 4 5 6 7 8 9 A 0 TBZ (abs8)bp,d7 TBZ (abs8)bp,d11 1 TBNZ (abs8)bp,d7 TBNZ (abs8)bp,d11 2 CMP Dn,Dm 3 ADD Dn,Dm 4 TBZ (io8)bp,d7 TBZ (io8)bp,d11 5 TBNZ (io8)bp,d7 TBNZ (io8)bp,d11 6 OR Dn,Dm 7 AND Dn,Dm 8 BSET (io8)bp BCLR (io8)bp 9 JMP abs18(label) JSR abs18(label) A XOR Dn,Dm / XOR #8,Dm B ADDC Dn,Dm C BSET (abs16)bp BCLR (abs16)bp D BTST (abs16)bp cmp #8,(abs16) mov #8,(abs16) E T
Chapter 18 Flash EEPROM 18
Chapter 18 Flash EEPROM 18-1 Overview 18-1-1 Overview The MN101CF77G is equivalent to MN101C77C except its Mask ROM is substituted with 128 KB of flash EEPROM. Operating voltage of MN101CF77G is as follows. MN101CF77G Operating voltage: VDD=2.7 V to 3.6 V Normal operation is guaranteed with up to ten programmings. *1 The MN101CF77G is programmed in one of two modes; PROM writer mode, which uses a dedicated PROM writer for a microcontroller's stand-alone programming.
Chapter 18 Flash EEPROM If serial interface communication pins (P53, P54, P05 and P03) are in floating state, this Flash EEPROM version may enter the onboard programming mode even when the serial writer is not connected to it (on-board programming mode is not selected). To avoid this, set the pull-up resistors on the target board, or design the circuit in such a way that the pins are "H" or "L" level even at reset. If load program is not written to the Flash EEPROM, it does not happen.
Chapter 18 Flash EEPROM 18-1-2 Differences between Mask ROM version and EPROM version Table 18-1-1 shows differences between 8-bit microcontroller MN101C77C (Mask ROM version), MN101CF77G (EPROM version) . Table 18-1-1 Differences between Mask ROM version and EPROM version MN101C77C (Mask ROM Version) Operating temperature MN101CF77G (Flash EEPROM Version) - 40 oC to +85oC - 40 oC to +85 oC 2.5 V to 3.6 V (100ns / 20MHz) 2.7 V to 3.6 V (100ns / 20MHz) Operating Voltage 2.1 V to 3.
Chapter 18 P77/TCIO5 P76/TCIO1 P75/SBT1B P74/SBI1B/RXD1B 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 P86/LED6 P87/LED7 Pin Descriptions PA2/AN2 PA1/AN1/DA1 PA0/AN0/DA0 VREFP80/LED0 P81/LED1 P82/LED2 P83/LED3 P84/LED4 P85/LED5 18-2 Flash EEPROM 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 MN101CF77G (TOP VIEW) P73/SBO1B/TXD1B P72/SBT0B P71/SBI0B/RXD0B P70/SBO0B/TXD0B P67/SDO7/KEY7 P66/SDO6/KEY6 P65/SDO5/KEY5 P64/SDO4/KEY4 P63/SDO3/KEY3 P62/SDO2/KEY2 P61/SDO1/KEY1 P60/SDO0/KEY0 P54/SCL4A P53/
Chapter 18 Flash EEPROM 18-3 Electrical Characteristics This LSI user's manual describes the standard specification. Please ask our sales offices for its own product specifications. Model Contents Structure Application Function MN101CF77G CMOS integrated circuit General purpose CMOS 8-bit single-chip microcontroller Absolute Maximum Ratings*2,*3 18-3-1 Parameter Symbol Rating Unit 1 Power supply voltage VDD − 0.3 to + 4.
Chapter 18 18-3-2 Flash EEPROM Operating Conditions [ NORMAL mode : fs=fosc/2, SLOW mode : fs=fx/2 ] Ta = − 40 oC to + 85 oC Parameter Symbol Conditions VDD = 2.7 V to 3.6 V MIN Rating TYP MAX 2.7 - 3.6 2.7 - 3.6 - VDD - 2.7 - 3.6 0.100 - 125 Unit Power supply voltage *1 1 2 VDD1 Power supply voltage 3 VPP Voltage to maintain RAM data Operation speed *1 4 5 VDD2 fosc=< 20.0 MHz, fs=focs/2 VPP=VDD fx=< 32.
Chapter 18 Flash EEPROM 18-3-3 DC Characteristics Ta = − 40 oC to + 85 oC Param eter Sym bol C onditions VD D = 3.3 V MIN R ating TYP MAX - 11 24 VSS = 0 V U nit Pow er s upply current (no load at output pin) *1 1 ID D 1 fos c=20.0 MH z, fs =focs /2 VPP=VD D =3.3 V ID D 2 fos c=8.39 MH z, fs =focs /2 VPP=VD D =3.3 V - 5.5 11 ID D 3 fx=32 kH z, fs =fx/2 VPP=VD D =3.3 V - 100 160 ID D 4 fx=32 kH z, VPP=VD D =3.
Chapter 18 18-4 Flash EEPROM Reprogramming Flow Figure 18-4-1 shows the flow for reprogramming (erasing and programming) the flash EEPROM. As the figure shows, the User Data Program starts after the memory is erased. START Power ON Sequence Erase Check OK Erase User Data Program Read / Standby Power OFF Sequence END Figure 18-4-1 Reprogramming Flow of Internal Flash EEPROM Start write routine (User Data Program) only after erase routine is completely finished.
Chapter 18 Flash EEPROM 18-5 PROM writer mode In PROM writer mode, the CPU is halted for Internal flash EEPROM to be programed. The microcontroller is inserted into a dedicated adaptor socket, which connects to a PROM writer. When the microcontroller connects to the adaptor socket, it automatically enters PROM writer mode. For programming using our PanaX Flash writer, you need dedicated adapter socket and gender changer. The P/N are as follows.
Chapter 18 Flash EEPROM A15 A14 A13 A12 D6 D7 MN101CF77G P73 48 P72 47 P71 46 P70 45 P67 44 P66 43 P65 42 P64 41 P63 40 P62 39 P61 38 P60 37 P54 36 P53 35 P52 34 P51 33 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 VSS A17 A16 P24 P50 P14 P20 P21 P22 P23 (TOP VIEW) P02 P03 P04 P05 P06 P10 P11 P12 P13 PA3 PA4 PA5 PA6 VPP VREF+ VDD OSC2 OSC1 VSS XI XO MMOD XI XO MMOD Figure 18-5-2 D12 D13 D14 D15 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ERASE 1 2 3 4 5 6 7 8 9 10
Chapter 18 Flash EEPROM 18-6 Onboard Serial Programming Mode 18-6-1 Overview The onboard serial programming mode is primarily used to program the flash EEPROM in devices that are already installed on a PCB board with internal serial interface. Hardware and software requirements Hardware and software products required for onboard serial programming are as follows. Hardware requirements xOnboard serial writer (YDC MODEL: AF200) xFlash programming connectors or pins for target board.
Chapter 18 Flash EEPROM 18-6-2 Circuit Requirements for the Target Board (in Clock Synchronous Communication using the YDC Serial Writer) This section describes the circuit requirements for the target board for onboard serial programming with the serial interface 0 using YDC serial writer. Target Board YDC Serial Writer Figure 18-6-1 VPP VDD NRST P05 P04 P03 VSS MN101CF77G NRST P05 P04 P03 VPP VDD VSS Target Board for programming using the YDC Serial Writer Pins VPP : 5.
Chapter 18 Flash EEPROM This section describes each memory space of Flash EEPROM.
Chapter 18 Flash EEPROM Use of YDC serial writer xYou must write the load program to this LSI before installed in the target board. The load program usually comes with onboard serial writer. xErase block 0 (load program) is write/erase-protected in the hardware during onboard programming mode. xVPP pin pin must supply 5.0 V from external source.
Chapter 18 Flash EEPROM 18-6-3 Circuit Requirements for the Target Board (in Clock Synchronous Communication using the PanaX Serial Writer) In programming Flash EEPROM using the PanaX serial writer, you need not to write load program in advance and also be able to use all space of the Flash EEPROM as user program area. Use P53, P54 for communication with serial writer.
Chapter 18 Flash EEPROM Use of PanaX serial writer (DWIRE programming) xYou need not to write load program in advance and also be able to use all space of the Flash EEPROM as user program area. xVPP pin must supply 5.0 V from external power source. xP53 and P54 pins should be reserved as dedicated pins for serial writer to prevent other user circuits on the target board from communicating with the device. Alternatively, design your target board on which the serial writer can program the device correctly.
Chapter 18 Flash EEPROM xTo connect resistors in series with communication pins (NRST, P53, P54) When resistors are connected in series with communication pins, signal spectrum speed drops affected by the load capacity. To ensure effecting reliable communication, the required time in which the operating voltage reaches to 63% of the time constant must be shorter than 1/8 of communication cycle.
MN101C77C/F77G LSI User's Manual February, 2004 1st Edition Issued by Matsushita Electric Industrial Co., Ltd. © Matsushita Electric Industrial Co., Ltd.
SALES OFFICES NORTH AMERICA ASIA ˜ U.S.A. Sales Office: Panasonic Industrial Company [PIC] — New Jersey Office: 2 Panasonic Way Secaucus, New Jersey 07094, U.S.A. Tel:1-201-348-5257 Fax:1-201-392-4652 — Chicago Office: 1707 N. Randall Road Elgin, Illinois 60123-7847, U.S.A. Tel:1-847-468-5720 Fax:1-847-468-5725 — San Jose Office: 2033 Gateway Place, Suite 200, San Jose, California 95110, U.S.
