Datasheet

CLASSIFICATION
PRODUCT SPECIFICATION
No.
DS-1740-2400-102
REV.
1.2
SUBJECT
CLASS 2 BLUETOOTH LOW ENERGY
SINGLE MODE MODULE
PAGE
6 of 34
CUSTOMER’S CODE
PAN1740
PANASONIC’S CODE
ENW89846A1KF
DATE
22.04.2014
PANASONIC INDUSTRIAL DEVICES EUROPE GMBH
www.pideu.panasonic.de
5 SYSTEM OVERVIEW
The PAN1740 contains the following internal blocks:
5.1 ARM CORTEX M0 CPU
The Cortex-M0 processor is a 32-bit Reduced Instruction Set Computing (RISC) processor
with a von Neumann architecture (single bus interface). It uses an instruction set called
Thumb, which was first supported in the ARM7TDMI processor; however, several newer
instructions from the ARMv6 architecture and a few instructions from the Thumb-2 technology
are also included. Thumb-2 technology extended the previous Thumb instruction set to allow
all operations to be carried out in one CPU state. The instruction set in Thumb-2 includes both
16-bit and 32-bit instructions; most instructions generated by the C compiler use the 16-bit
instructions, and the 32-bit instructions are used when the 16-bit version cannot carry out the
required operations. This results in high code density and avoids the overhead of switching
between two instruction sets.
In total, the Cortex-M0 processor supports 56 base instructions, although some instructions
can have more than one form. While the instruction set is small, the Cortex-M0 processor is
highly capable because the Thumb instruction set is highly optimized.
5.2 BLUETOOTH SMART
5.2.1 BLE Core
The BLE (Bluetooth Low Energy) core is a qualified Bluetooth v4.1 baseband controller
compatible with Bluetooth Smart specification and it is in charge of packet encoding-
decoding and frame scheduling.
 Bluetooth Smart Specifications compliant according to the Specification of the
Bluetooth System, v4.1, Bluetooth SIG.
 All device classes are supported -- Broadcast, Central, Observer, Peripheral)
 All packet types (Advertising / Data / Control)
 Encryption (AES / CCM)
 Bit stream processing (CRC, Whitening)
 FDMA / TDMA / events formatting and synchronization
 Frequency Hopping calculation
 Operating clock with internal 16 MHz
 Low power modes with internal 32.678 kHz
 Supports power down of the baseband during the protocol’s idle periods.
 Advanced High performance Bus (AHB) Slave interface for register file access.
 AHB Slave interface for Exchange Memory access of CPU via BLE core.
 AHB Master interface for direct access of BLE core to Exchange Memory space